mirror of https://gitee.com/openkylin/linux.git
Merge tag 'amd-drm-fixes-5.8-2020-06-17' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
amd-drm-fixes-5.8-2020-06-17: amdgpu: - Fix kvfree/kfree mixup - Fix hawaii device id in powertune configuration - Display FP fixes - Documentation fixes amdkfd: - devcgroup check fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200617220733.3773183-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
commit
8a7a3d1d0d
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@ -197,11 +197,14 @@ pp_power_profile_mode
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.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
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:doc: pp_power_profile_mode
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busy_percent
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~~~~~~~~~~~~
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*_busy_percent
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~~~~~~~~~~~~~~
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.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
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:doc: busy_percent
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:doc: gpu_busy_percent
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.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
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:doc: mem_busy_percent
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GPU Product Information
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=======================
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@ -696,7 +696,7 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
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* default power levels, write "r" (reset) to the file to reset them.
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*
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*
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* < For Vega20 >
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* < For Vega20 and newer ASICs >
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*
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* Reading the file will display:
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*
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@ -1668,7 +1668,7 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
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}
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/**
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* DOC: busy_percent
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* DOC: gpu_busy_percent
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*
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* The amdgpu driver provides a sysfs API for reading how busy the GPU
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* is as a percentage. The file gpu_busy_percent is used for this.
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@ -40,6 +40,7 @@
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#include <drm/drm_file.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_device.h>
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#include <drm/drm_ioctl.h>
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#include <kgd_kfd_interface.h>
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#include <linux/swap.h>
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@ -1076,7 +1077,7 @@ static inline int kfd_devcgroup_check_permission(struct kfd_dev *kfd)
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#if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF)
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struct drm_device *ddev = kfd->ddev;
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return devcgroup_check_permission(DEVCG_DEV_CHAR, ddev->driver->major,
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return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR,
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ddev->render->index,
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DEVCG_ACC_WRITE | DEVCG_ACC_READ);
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#else
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@ -28,8 +28,6 @@ endif
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endif
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CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc_dpi.o := $(dsc_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dsc/dc_dsc.o := $(dsc_ccflags)
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DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o
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@ -22,10 +22,12 @@
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* Author: AMD
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*/
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#include <drm/drm_dsc.h>
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#include "dc_hw_types.h"
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#include "dsc.h"
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#include <drm/drm_dp_helper.h>
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#include "dc.h"
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#include "rc_calc.h"
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/* This module's internal functions */
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@ -304,22 +306,6 @@ static inline uint32_t dsc_div_by_10_round_up(uint32_t value)
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return (value + 9) / 10;
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}
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static inline uint32_t calc_dsc_bpp_x16(uint32_t stream_bandwidth_kbps, uint32_t pix_clk_100hz, uint32_t bpp_increment_div)
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{
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uint32_t dsc_target_bpp_x16;
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float f_dsc_target_bpp;
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float f_stream_bandwidth_100bps = stream_bandwidth_kbps * 10.0f;
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uint32_t precision = bpp_increment_div; // bpp_increment_div is actually precision
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f_dsc_target_bpp = f_stream_bandwidth_100bps / pix_clk_100hz;
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// Round down to the nearest precision stop to bring it into DSC spec range
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dsc_target_bpp_x16 = (uint32_t)(f_dsc_target_bpp * precision);
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dsc_target_bpp_x16 = (dsc_target_bpp_x16 * 16) / precision;
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return dsc_target_bpp_x16;
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}
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/* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range, and timing's pixel clock
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* and uncompressed bandwidth.
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*/
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@ -23,6 +23,7 @@
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* Authors: AMD
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*
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*/
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#include <drm/drm_dsc.h>
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#include "os_types.h"
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#include "rc_calc.h"
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@ -40,7 +41,8 @@
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break
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void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc, enum max_min max_min, float bpp)
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static void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc,
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enum max_min max_min, float bpp)
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{
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int mode = MODE_SELECT(444, 422, 420);
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int sel = table_hash(mode, bpc, max_min);
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@ -85,7 +87,7 @@ void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc, enum ma
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memcpy(qps, table[index].qps, sizeof(qp_set));
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}
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double dsc_roundf(double num)
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static double dsc_roundf(double num)
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{
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if (num < 0.0)
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num = num - 0.5;
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@ -95,7 +97,7 @@ double dsc_roundf(double num)
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return (int)(num);
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}
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double dsc_ceil(double num)
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static double dsc_ceil(double num)
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{
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double retval = (int)num;
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@ -105,7 +107,7 @@ double dsc_ceil(double num)
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return (int)retval;
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}
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void get_ofs_set(qp_set ofs, enum colour_mode mode, float bpp)
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static void get_ofs_set(qp_set ofs, enum colour_mode mode, float bpp)
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{
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int *p = ofs;
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@ -160,7 +162,7 @@ void get_ofs_set(qp_set ofs, enum colour_mode mode, float bpp)
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}
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}
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int median3(int a, int b, int c)
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static int median3(int a, int b, int c)
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{
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if (a > b)
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swap(a, b);
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@ -172,13 +174,25 @@ int median3(int a, int b, int c)
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return b;
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}
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void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_comp bpc, float bpp, int slice_width, int slice_height, int minor_version)
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static void _do_calc_rc_params(struct rc_params *rc, enum colour_mode cm,
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enum bits_per_comp bpc, u8 drm_bpp,
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bool is_navite_422_or_420,
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int slice_width, int slice_height,
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int minor_version)
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{
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float bpp;
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float bpp_group;
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float initial_xmit_delay_factor;
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int padding_pixels;
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int i;
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bpp = ((float)drm_bpp / 16.0);
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/* in native_422 or native_420 modes, the bits_per_pixel is double the
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* target bpp (the latter is what calc_rc_params expects)
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*/
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if (is_navite_422_or_420)
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bpp /= 2.0;
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rc->rc_quant_incr_limit0 = ((bpc == BPC_8) ? 11 : (bpc == BPC_10 ? 15 : 19)) - ((minor_version == 1 && cm == CM_444) ? 1 : 0);
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rc->rc_quant_incr_limit1 = ((bpc == BPC_8) ? 11 : (bpc == BPC_10 ? 15 : 19)) - ((minor_version == 1 && cm == CM_444) ? 1 : 0);
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@ -251,3 +265,128 @@ void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_com
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rc->rc_buf_thresh[13] = 8064;
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}
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static u32 _do_bytes_per_pixel_calc(int slice_width, u8 drm_bpp,
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bool is_navite_422_or_420)
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{
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float bpp;
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u32 bytes_per_pixel;
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double d_bytes_per_pixel;
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bpp = ((float)drm_bpp / 16.0);
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d_bytes_per_pixel = dsc_ceil(bpp * slice_width / 8.0) / slice_width;
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// TODO: Make sure the formula for calculating this is precise (ceiling
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// vs. floor, and at what point they should be applied)
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if (is_navite_422_or_420)
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d_bytes_per_pixel /= 2;
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bytes_per_pixel = (u32)dsc_ceil(d_bytes_per_pixel * 0x10000000);
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return bytes_per_pixel;
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}
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static u32 _do_calc_dsc_bpp_x16(u32 stream_bandwidth_kbps, u32 pix_clk_100hz,
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u32 bpp_increment_div)
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{
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u32 dsc_target_bpp_x16;
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float f_dsc_target_bpp;
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float f_stream_bandwidth_100bps;
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// bpp_increment_div is actually precision
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u32 precision = bpp_increment_div;
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f_stream_bandwidth_100bps = stream_bandwidth_kbps * 10.0f;
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f_dsc_target_bpp = f_stream_bandwidth_100bps / pix_clk_100hz;
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// Round down to the nearest precision stop to bring it into DSC spec
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// range
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dsc_target_bpp_x16 = (u32)(f_dsc_target_bpp * precision);
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dsc_target_bpp_x16 = (dsc_target_bpp_x16 * 16) / precision;
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return dsc_target_bpp_x16;
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}
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/**
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* calc_rc_params - reads the user's cmdline mode
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* @rc: DC internal DSC parameters
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* @pps: DRM struct with all required DSC values
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*
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* This function expects a drm_dsc_config data struct with all the required DSC
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* values previously filled out by our driver and based on this information it
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* computes some of the DSC values.
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*
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* @note This calculation requires float point operation, most of it executes
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* under kernel_fpu_{begin,end}.
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*/
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void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps)
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{
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enum colour_mode mode;
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enum bits_per_comp bpc;
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bool is_navite_422_or_420;
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u8 drm_bpp = pps->bits_per_pixel;
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int slice_width = pps->slice_width;
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int slice_height = pps->slice_height;
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mode = pps->convert_rgb ? CM_RGB : (pps->simple_422 ? CM_444 :
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(pps->native_422 ? CM_422 :
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pps->native_420 ? CM_420 : CM_444));
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bpc = (pps->bits_per_component == 8) ? BPC_8 : (pps->bits_per_component == 10)
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? BPC_10 : BPC_12;
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is_navite_422_or_420 = pps->native_422 || pps->native_420;
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DC_FP_START();
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_do_calc_rc_params(rc, mode, bpc, drm_bpp, is_navite_422_or_420,
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slice_width, slice_height,
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pps->dsc_version_minor);
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DC_FP_END();
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}
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/**
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* calc_dsc_bytes_per_pixel - calculate bytes per pixel
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* @pps: DRM struct with all required DSC values
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*
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* Based on the information inside drm_dsc_config, this function calculates the
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* total of bytes per pixel.
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*
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* @note This calculation requires float point operation, most of it executes
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* under kernel_fpu_{begin,end}.
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*
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* Return:
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* Return the number of bytes per pixel
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*/
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u32 calc_dsc_bytes_per_pixel(const struct drm_dsc_config *pps)
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{
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u32 ret;
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u8 drm_bpp = pps->bits_per_pixel;
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int slice_width = pps->slice_width;
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bool is_navite_422_or_420 = pps->native_422 || pps->native_420;
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DC_FP_START();
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ret = _do_bytes_per_pixel_calc(slice_width, drm_bpp,
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is_navite_422_or_420);
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DC_FP_END();
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return ret;
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}
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/**
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* calc_dsc_bpp_x16 - retrieve the dsc bits per pixel
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* @stream_bandwidth_kbps:
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* @pix_clk_100hz:
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* @bpp_increment_div:
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*
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* Calculate the total of bits per pixel for DSC configuration.
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*
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* @note This calculation requires float point operation, most of it executes
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* under kernel_fpu_{begin,end}.
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*/
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u32 calc_dsc_bpp_x16(u32 stream_bandwidth_kbps, u32 pix_clk_100hz,
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u32 bpp_increment_div)
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{
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u32 dsc_bpp;
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DC_FP_START();
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dsc_bpp = _do_calc_dsc_bpp_x16(stream_bandwidth_kbps, pix_clk_100hz,
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bpp_increment_div);
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DC_FP_END();
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return dsc_bpp;
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}
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@ -77,7 +77,10 @@ struct qp_entry {
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typedef struct qp_entry qp_table[];
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void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_comp bpc, float bpp, int slice_width, int slice_height, int minor_version);
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void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps);
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u32 calc_dsc_bytes_per_pixel(const struct drm_dsc_config *pps);
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u32 calc_dsc_bpp_x16(u32 stream_bandwidth_kbps, u32 pix_clk_100hz,
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u32 bpp_increment_div);
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#endif
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@ -27,8 +27,6 @@
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#include "dscc_types.h"
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#include "rc_calc.h"
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double dsc_ceil(double num);
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static void copy_pps_fields(struct drm_dsc_config *to, const struct drm_dsc_config *from)
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{
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to->line_buf_depth = from->line_buf_depth;
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@ -100,34 +98,13 @@ static void copy_rc_to_cfg(struct drm_dsc_config *dsc_cfg, const struct rc_param
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int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_parameters *dsc_params)
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{
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enum colour_mode mode = pps->convert_rgb ? CM_RGB :
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(pps->simple_422 ? CM_444 :
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(pps->native_422 ? CM_422 :
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pps->native_420 ? CM_420 : CM_444));
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enum bits_per_comp bpc = (pps->bits_per_component == 8) ? BPC_8 :
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(pps->bits_per_component == 10) ? BPC_10 : BPC_12;
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float bpp = ((float) pps->bits_per_pixel / 16.0);
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int slice_width = pps->slice_width;
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int slice_height = pps->slice_height;
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int ret;
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struct rc_params rc;
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struct drm_dsc_config dsc_cfg;
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double d_bytes_per_pixel = dsc_ceil(bpp * slice_width / 8.0) / slice_width;
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dsc_params->bytes_per_pixel = calc_dsc_bytes_per_pixel(pps);
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// TODO: Make sure the formula for calculating this is precise (ceiling vs. floor, and at what point they should be applied)
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if (pps->native_422 || pps->native_420)
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d_bytes_per_pixel /= 2;
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dsc_params->bytes_per_pixel = (uint32_t)dsc_ceil(d_bytes_per_pixel * 0x10000000);
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/* in native_422 or native_420 modes, the bits_per_pixel is double the target bpp
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* (the latter is what calc_rc_params expects)
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*/
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if (pps->native_422 || pps->native_420)
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bpp /= 2.0;
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calc_rc_params(&rc, mode, bpc, bpp, slice_width, slice_height, pps->dsc_version_minor);
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calc_rc_params(&rc, pps);
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dsc_params->pps = *pps;
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dsc_params->pps.initial_scale_value = 8 * rc.rc_model_size / (rc.rc_model_size - rc.initial_fullness_offset);
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|
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@ -843,7 +843,7 @@ static bool build_regamma(struct pwl_float_data_ex *rgb_regamma,
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pow_buffer_ptr = -1; // reset back to no optimize
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ret = true;
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release:
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kfree(coeff);
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kvfree(coeff);
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return ret;
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}
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@ -1777,7 +1777,7 @@ bool calculate_user_regamma_ramp(struct dc_transfer_func *output_tf,
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kfree(rgb_regamma);
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rgb_regamma_alloc_fail:
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kvfree(rgb_user);
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kfree(rgb_user);
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rgb_user_alloc_fail:
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return ret;
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}
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|
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@ -239,7 +239,7 @@ static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
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switch (dev_id) {
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case 0x67BA:
|
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case 0x66B1:
|
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case 0x67B1:
|
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smu_data->power_tune_defaults = &defaults_hawaii_pro;
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break;
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||||
case 0x67B8:
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||||
|
|
|
|||
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