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cxgb3 - Firmware update
Update FW to 4.1. Proceed to subsequent HW tuning to improve RDMA perfs.. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Divy Le Ray
Jeff Garzik
parent
cf992af561
commit
8a9fab22cf
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@ -1160,6 +1160,8 @@
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#define A_TP_MOD_CHANNEL_WEIGHT 0x434
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#define A_TP_MOD_RATE_LIMIT 0x438
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#define A_TP_PIO_ADDR 0x440
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#define A_TP_PIO_DATA 0x444
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@ -1214,6 +1216,8 @@
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#define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & \
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M_TXDROPCNTCH0RCVD)
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#define A_TP_PROXY_FLOW_CNTL 0x4b0
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#define A_ULPRX_CTL 0x500
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#define S_ROUND_ROBIN 4
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@ -921,7 +921,7 @@ static int t3_flash_erase_sectors(struct adapter *adapter, int start, int end)
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/*
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* t3_load_fw - download firmware
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* @adapter: the adapter
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* @fw_data: the firrware image to write
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* @fw_data: the firmware image to write
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* @size: image size
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*
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* Write the supplied firmware image to the card's serial flash.
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@ -2362,7 +2362,7 @@ static void tp_config(struct adapter *adap, const struct tp_params *p)
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F_TCPCHECKSUMOFFLOAD | V_IPTTL(64));
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t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
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F_MTUENABLE | V_WINDOWSCALEMODE(1) |
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V_TIMESTAMPSMODE(1) | V_SACKMODE(1) | V_SACKRX(1));
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V_TIMESTAMPSMODE(0) | V_SACKMODE(1) | V_SACKRX(1));
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t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
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V_AUTOSTATE2(1) | V_AUTOSTATE1(0) |
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V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) |
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@ -2371,16 +2371,18 @@ static void tp_config(struct adapter *adap, const struct tp_params *p)
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F_IPV6ENABLE | F_NICMODE);
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t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
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t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
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t3_set_reg_field(adap, A_TP_PARA_REG6,
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adap->params.rev > 0 ? F_ENABLEESND : F_T3A_ENABLEESND,
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0);
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t3_set_reg_field(adap, A_TP_PARA_REG6, 0,
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adap->params.rev > 0 ? F_ENABLEESND :
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F_T3A_ENABLEESND);
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t3_set_reg_field(adap, A_TP_PC_CONFIG,
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F_ENABLEEPCMDAFULL | F_ENABLEOCSPIFULL,
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F_TXDEFERENABLE | F_HEARBEATDACK | F_TXCONGESTIONMODE |
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F_RXCONGESTIONMODE);
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F_ENABLEEPCMDAFULL,
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F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK |
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F_TXCONGESTIONMODE | F_RXCONGESTIONMODE);
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t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL, 0);
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t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
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t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
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if (adap->params.rev > 0) {
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tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);
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t3_set_reg_field(adap, A_TP_PARA_REG3, F_TXPACEAUTO,
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@ -2390,9 +2392,10 @@ static void tp_config(struct adapter *adap, const struct tp_params *p)
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} else
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t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
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t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0x12121212);
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t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0x12121212);
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t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0x1212);
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t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
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t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
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t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
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t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
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}
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/* Desired TP timer resolution in usec */
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@ -2468,6 +2471,7 @@ int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh)
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val |= F_RXCOALESCEENABLE;
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if (psh)
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val |= F_RXCOALESCEPSHEN;
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size = min(MAX_RX_COALESCING_LEN, size);
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t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) |
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V_MAXRXDATA(MAX_RX_COALESCING_LEN));
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}
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@ -2496,11 +2500,11 @@ static void __devinit init_mtus(unsigned short mtus[])
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* it can accomodate max size TCP/IP headers when SACK and timestamps
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* are enabled and still have at least 8 bytes of payload.
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*/
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mtus[0] = 88;
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mtus[1] = 256;
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mtus[2] = 512;
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mtus[3] = 576;
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mtus[4] = 808;
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mtus[1] = 88;
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mtus[1] = 88;
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mtus[2] = 256;
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mtus[3] = 512;
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mtus[4] = 576;
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mtus[5] = 1024;
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mtus[6] = 1280;
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mtus[7] = 1492;
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@ -2802,7 +2806,7 @@ static void init_hw_for_avail_ports(struct adapter *adap, int nports)
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t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0);
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t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_TPTXPORT0EN |
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F_PORT0ACTIVE | F_ENFORCEPKT);
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t3_write_reg(adap, A_PM1_TX_CFG, 0xc000c000);
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t3_write_reg(adap, A_PM1_TX_CFG, 0xffffffff);
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} else {
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t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN);
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t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB);
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@ -3097,7 +3101,7 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params)
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else
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t3_set_reg_field(adapter, A_PCIX_CFG, 0, F_CLIDECEN);
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t3_write_reg(adapter, A_PM1_RX_CFG, 0xf000f000);
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t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
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init_hw_for_avail_ports(adapter, adapter->params.nports);
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t3_sge_init(adapter, &adapter->params.sge);
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@ -39,6 +39,6 @@
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/* Firmware version */
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#define FW_VERSION_MAJOR 4
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#define FW_VERSION_MINOR 0
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#define FW_VERSION_MINOR 1
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#define FW_VERSION_MICRO 0
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#endif /* __CHELSIO_VERSION_H */
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