diff --git a/drivers/staging/ti-soc-thermal/omap5-thermal-data.c b/drivers/staging/ti-soc-thermal/omap5-thermal-data.c index aa16f92e19c0..a5fa1139fac0 100644 --- a/drivers/staging/ti-soc-thermal/omap5-thermal-data.c +++ b/drivers/staging/ti-soc-thermal/omap5-thermal-data.c @@ -39,6 +39,7 @@ omap5430_mpu_temp_sensor_registers = { .mask_hot_mask = OMAP5430_MASK_HOT_MPU_MASK, .mask_cold_mask = OMAP5430_MASK_COLD_MPU_MASK, .mask_sidlemode_mask = OMAP5430_MASK_SIDLEMODE_MASK, + .mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK, .mask_freeze_mask = OMAP5430_MASK_FREEZE_MPU_MASK, .mask_clear_mask = OMAP5430_MASK_CLEAR_MPU_MASK, .mask_clear_accum_mask = OMAP5430_MASK_CLEAR_ACCUM_MPU_MASK, @@ -84,6 +85,7 @@ omap5430_gpu_temp_sensor_registers = { .mask_hot_mask = OMAP5430_MASK_HOT_GPU_MASK, .mask_cold_mask = OMAP5430_MASK_COLD_GPU_MASK, .mask_sidlemode_mask = OMAP5430_MASK_SIDLEMODE_MASK, + .mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK, .mask_freeze_mask = OMAP5430_MASK_FREEZE_GPU_MASK, .mask_clear_mask = OMAP5430_MASK_CLEAR_GPU_MASK, .mask_clear_accum_mask = OMAP5430_MASK_CLEAR_ACCUM_GPU_MASK, @@ -129,6 +131,7 @@ omap5430_core_temp_sensor_registers = { .mask_hot_mask = OMAP5430_MASK_HOT_CORE_MASK, .mask_cold_mask = OMAP5430_MASK_COLD_CORE_MASK, .mask_sidlemode_mask = OMAP5430_MASK_SIDLEMODE_MASK, + .mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK, .mask_freeze_mask = OMAP5430_MASK_FREEZE_CORE_MASK, .mask_clear_mask = OMAP5430_MASK_CLEAR_CORE_MASK, .mask_clear_accum_mask = OMAP5430_MASK_CLEAR_ACCUM_CORE_MASK, diff --git a/drivers/staging/ti-soc-thermal/omap5xxx-bandgap.h b/drivers/staging/ti-soc-thermal/omap5xxx-bandgap.h index 8824db4391c4..400b55dffadd 100644 --- a/drivers/staging/ti-soc-thermal/omap5xxx-bandgap.h +++ b/drivers/staging/ti-soc-thermal/omap5xxx-bandgap.h @@ -95,6 +95,7 @@ /* OMAP5430.BANDGAP_CTRL */ #define OMAP5430_MASK_SIDLEMODE_MASK (0x3 << 30) +#define OMAP5430_MASK_COUNTER_DELAY_MASK (0x7 << 27) #define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23) #define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22) #define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21)