mirror of https://gitee.com/openkylin/linux.git
[S390] add z196 instructions to kernel disassembler
Add the new instructions introduced with z196 to the kernel disassembler. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
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8b8c12b120
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@ -113,7 +113,7 @@ enum {
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INSTR_INVALID,
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INSTR_E,
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INSTR_RIE_R0IU, INSTR_RIE_R0UU, INSTR_RIE_RRP, INSTR_RIE_RRPU,
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INSTR_RIE_RRUUU, INSTR_RIE_RUPI, INSTR_RIE_RUPU,
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INSTR_RIE_RRUUU, INSTR_RIE_RUPI, INSTR_RIE_RUPU, INSTR_RIE_RRI0,
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INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU, INSTR_RIL_UP,
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INSTR_RIS_R0RDU, INSTR_RIS_R0UU, INSTR_RIS_RURDI, INSTR_RIS_RURDU,
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INSTR_RI_RI, INSTR_RI_RP, INSTR_RI_RU, INSTR_RI_UP,
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@ -122,13 +122,14 @@ enum {
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INSTR_RRE_RR, INSTR_RRE_RR_OPT,
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INSTR_RRF_0UFF, INSTR_RRF_F0FF, INSTR_RRF_F0FF2, INSTR_RRF_F0FR,
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INSTR_RRF_FFRU, INSTR_RRF_FUFF, INSTR_RRF_M0RR, INSTR_RRF_R0RR,
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INSTR_RRF_RURR, INSTR_RRF_U0FF, INSTR_RRF_U0RF, INSTR_RRF_U0RR,
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INSTR_RRF_UUFF, INSTR_RRR_F0FF, INSTR_RRS_RRRDU,
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INSTR_RRF_R0RR2, INSTR_RRF_RURR, INSTR_RRF_U0FF, INSTR_RRF_U0RF,
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INSTR_RRF_U0RR, INSTR_RRF_UUFF, INSTR_RRR_F0FF, INSTR_RRS_RRRDU,
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INSTR_RR_FF, INSTR_RR_R0, INSTR_RR_RR, INSTR_RR_U0, INSTR_RR_UR,
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INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD,
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INSTR_RSI_RRP,
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INSTR_RSL_R0RD,
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INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD, INSTR_RSY_RURD,
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INSTR_RSY_RDRM,
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INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD, INSTR_RS_RRRD,
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INSTR_RS_RURD,
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INSTR_RXE_FRRD, INSTR_RXE_RRRD,
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@ -139,7 +140,7 @@ enum {
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INSTR_SIY_IRD, INSTR_SIY_URD,
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INSTR_SI_URD,
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INSTR_SSE_RDRD,
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INSTR_SSF_RRDRD,
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INSTR_SSF_RRDRD, INSTR_SSF_RRDRD2,
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INSTR_SS_L0RDRD, INSTR_SS_LIRDRD, INSTR_SS_LLRDRD, INSTR_SS_RRRDRD,
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INSTR_SS_RRRDRD2, INSTR_SS_RRRDRD3,
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INSTR_S_00, INSTR_S_RD,
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@ -152,7 +153,7 @@ struct operand {
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};
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struct insn {
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const char name[6];
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const char name[5];
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unsigned char opfrag;
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unsigned char format;
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};
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@ -217,6 +218,7 @@ static const unsigned char formats[][7] = {
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[INSTR_RIE_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 },
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[INSTR_RIE_RRUUU] = { 0xff, R_8,R_12,U8_16,U8_24,U8_32,0 },
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[INSTR_RIE_RUPI] = { 0xff, R_8,I8_32,U4_12,J16_16,0,0 },
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[INSTR_RIE_RRI0] = { 0xff, R_8,R_12,I16_16,0,0,0 },
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[INSTR_RIL_RI] = { 0x0f, R_8,I32_16,0,0,0,0 },
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[INSTR_RIL_RP] = { 0x0f, R_8,J32_16,0,0,0,0 },
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[INSTR_RIL_RU] = { 0x0f, R_8,U32_16,0,0,0,0 },
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@ -248,6 +250,7 @@ static const unsigned char formats[][7] = {
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[INSTR_RRF_FUFF] = { 0xff, F_24,F_16,F_28,U4_20,0,0 },
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[INSTR_RRF_M0RR] = { 0xff, R_24,R_28,M_16,0,0,0 },
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[INSTR_RRF_R0RR] = { 0xff, R_24,R_16,R_28,0,0,0 },
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[INSTR_RRF_R0RR2] = { 0xff, R_24,R_28,R_16,0,0,0 },
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[INSTR_RRF_RURR] = { 0xff, R_24,R_28,R_16,U4_20,0,0 },
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[INSTR_RRF_U0FF] = { 0xff, F_24,U4_16,F_28,0,0,0 },
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[INSTR_RRF_U0RF] = { 0xff, R_24,U4_16,F_28,0,0,0 },
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@ -269,6 +272,7 @@ static const unsigned char formats[][7] = {
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[INSTR_RSY_CCRD] = { 0xff, C_8,C_12,D20_20,B_16,0,0 },
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[INSTR_RSY_RRRD] = { 0xff, R_8,R_12,D20_20,B_16,0,0 },
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[INSTR_RSY_RURD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 },
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[INSTR_RSY_RDRM] = { 0xff, R_8,D20_20,B_16,U4_12,0,0 },
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[INSTR_RS_AARD] = { 0xff, A_8,A_12,D_20,B_16,0,0 },
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[INSTR_RS_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 },
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[INSTR_RS_R0RD] = { 0xff, R_8,D_20,B_16,0,0,0 },
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@ -290,6 +294,7 @@ static const unsigned char formats[][7] = {
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[INSTR_SI_URD] = { 0xff, D_20,B_16,U8_8,0,0,0 },
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[INSTR_SSE_RDRD] = { 0xff, D_20,B_16,D_36,B_32,0,0 },
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[INSTR_SSF_RRDRD] = { 0x00, D_20,B_16,D_36,B_32,R_8,0 },
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[INSTR_SSF_RRDRD2]= { 0x00, R_8,D_20,B_16,D_36,B_32,0 },
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[INSTR_SS_L0RDRD] = { 0xff, D_20,L8_8,B_16,D_36,B_32,0 },
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[INSTR_SS_LIRDRD] = { 0xff, D_20,L4_8,B_16,D_36,B_32,U4_12 },
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[INSTR_SS_LLRDRD] = { 0xff, D_20,L4_8,B_16,D_36,L4_12,B_32 },
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@ -300,6 +305,36 @@ static const unsigned char formats[][7] = {
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[INSTR_S_RD] = { 0xff, D_20,B_16,0,0,0,0 },
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};
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enum {
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LONG_INSN_ALGHSIK,
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LONG_INSN_ALHSIK,
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LONG_INSN_CLFHSI,
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LONG_INSN_CLGFRL,
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LONG_INSN_CLGHRL,
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LONG_INSN_CLGHSI,
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LONG_INSN_CLHHSI,
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LONG_INSN_LLGFRL,
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LONG_INSN_LLGHRL,
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LONG_INSN_POPCNT,
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LONG_INSN_RISBHG,
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LONG_INSN_RISBLG,
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};
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static char *long_insn_name[] = {
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[LONG_INSN_ALGHSIK] = "alghsik",
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[LONG_INSN_ALHSIK] = "alhsik",
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[LONG_INSN_CLFHSI] = "clfhsi",
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[LONG_INSN_CLGFRL] = "clgfrl",
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[LONG_INSN_CLGHRL] = "clghrl",
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[LONG_INSN_CLGHSI] = "clghsi",
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[LONG_INSN_CLHHSI] = "clhhsi",
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[LONG_INSN_LLGFRL] = "llgfrl",
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[LONG_INSN_LLGHRL] = "llghrl",
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[LONG_INSN_POPCNT] = "popcnt",
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[LONG_INSN_RISBHG] = "risbhg",
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[LONG_INSN_RISBLG] = "risblk",
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};
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static struct insn opcode[] = {
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#ifdef CONFIG_64BIT
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{ "lmd", 0xef, INSTR_SS_RRRDRD3 },
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@ -881,6 +916,35 @@ static struct insn opcode_b9[] = {
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{ "pfmf", 0xaf, INSTR_RRE_RR },
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{ "trte", 0xbf, INSTR_RRF_M0RR },
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{ "trtre", 0xbd, INSTR_RRF_M0RR },
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{ "ahhhr", 0xc8, INSTR_RRF_R0RR2 },
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{ "shhhr", 0xc9, INSTR_RRF_R0RR2 },
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{ "alhhh", 0xca, INSTR_RRF_R0RR2 },
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{ "alhhl", 0xca, INSTR_RRF_R0RR2 },
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{ "slhhh", 0xcb, INSTR_RRF_R0RR2 },
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{ "chhr ", 0xcd, INSTR_RRE_RR },
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{ "clhhr", 0xcf, INSTR_RRE_RR },
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{ "ahhlr", 0xd8, INSTR_RRF_R0RR2 },
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{ "shhlr", 0xd9, INSTR_RRF_R0RR2 },
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{ "slhhl", 0xdb, INSTR_RRF_R0RR2 },
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{ "chlr", 0xdd, INSTR_RRE_RR },
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{ "clhlr", 0xdf, INSTR_RRE_RR },
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{ { 0, LONG_INSN_POPCNT }, 0xe1, INSTR_RRE_RR },
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{ "locgr", 0xe2, INSTR_RRF_M0RR },
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{ "ngrk", 0xe4, INSTR_RRF_R0RR2 },
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{ "ogrk", 0xe6, INSTR_RRF_R0RR2 },
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{ "xgrk", 0xe7, INSTR_RRF_R0RR2 },
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{ "agrk", 0xe8, INSTR_RRF_R0RR2 },
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{ "sgrk", 0xe9, INSTR_RRF_R0RR2 },
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{ "algrk", 0xea, INSTR_RRF_R0RR2 },
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{ "slgrk", 0xeb, INSTR_RRF_R0RR2 },
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{ "locr", 0xf2, INSTR_RRF_M0RR },
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{ "nrk", 0xf4, INSTR_RRF_R0RR2 },
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{ "ork", 0xf6, INSTR_RRF_R0RR2 },
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{ "xrk", 0xf7, INSTR_RRF_R0RR2 },
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{ "ark", 0xf8, INSTR_RRF_R0RR2 },
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{ "srk", 0xf9, INSTR_RRF_R0RR2 },
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{ "alrk", 0xfa, INSTR_RRF_R0RR2 },
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{ "slrk", 0xfb, INSTR_RRF_R0RR2 },
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#endif
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{ "kmac", 0x1e, INSTR_RRE_RR },
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{ "lrvr", 0x1f, INSTR_RRE_RR },
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@ -949,9 +1013,9 @@ static struct insn opcode_c4[] = {
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{ "lgfrl", 0x0c, INSTR_RIL_RP },
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{ "lhrl", 0x05, INSTR_RIL_RP },
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{ "lghrl", 0x04, INSTR_RIL_RP },
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{ "llgfrl", 0x0e, INSTR_RIL_RP },
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{ { 0, LONG_INSN_LLGFRL }, 0x0e, INSTR_RIL_RP },
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{ "llhrl", 0x02, INSTR_RIL_RP },
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{ "llghrl", 0x06, INSTR_RIL_RP },
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{ { 0, LONG_INSN_LLGHRL }, 0x06, INSTR_RIL_RP },
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{ "strl", 0x0f, INSTR_RIL_RP },
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{ "stgrl", 0x0b, INSTR_RIL_RP },
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{ "sthrl", 0x07, INSTR_RIL_RP },
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@ -968,9 +1032,9 @@ static struct insn opcode_c6[] = {
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{ "cghrl", 0x04, INSTR_RIL_RP },
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{ "clrl", 0x0f, INSTR_RIL_RP },
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{ "clgrl", 0x0a, INSTR_RIL_RP },
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{ "clgfrl", 0x0e, INSTR_RIL_RP },
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{ { 0, LONG_INSN_CLGFRL }, 0x0e, INSTR_RIL_RP },
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{ "clhrl", 0x07, INSTR_RIL_RP },
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{ "clghrl", 0x06, INSTR_RIL_RP },
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{ { 0, LONG_INSN_CLGHRL }, 0x06, INSTR_RIL_RP },
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{ "pfdrl", 0x02, INSTR_RIL_UP },
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{ "exrl", 0x00, INSTR_RIL_RP },
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#endif
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@ -982,6 +1046,20 @@ static struct insn opcode_c8[] = {
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{ "mvcos", 0x00, INSTR_SSF_RRDRD },
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{ "ectg", 0x01, INSTR_SSF_RRDRD },
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{ "csst", 0x02, INSTR_SSF_RRDRD },
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{ "lpd", 0x04, INSTR_SSF_RRDRD2 },
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{ "lpdg ", 0x05, INSTR_SSF_RRDRD2 },
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#endif
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{ "", 0, INSTR_INVALID }
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};
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static struct insn opcode_cc[] = {
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#ifdef CONFIG_64BIT
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{ "brcth", 0x06, INSTR_RIL_RP },
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{ "aih", 0x08, INSTR_RIL_RI },
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{ "alsih", 0x0a, INSTR_RIL_RI },
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{ "alsih", 0x0b, INSTR_RIL_RI },
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{ "cih", 0x0d, INSTR_RIL_RI },
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{ "clih ", 0x0f, INSTR_RIL_RI },
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#endif
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{ "", 0, INSTR_INVALID }
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};
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@ -1063,6 +1141,16 @@ static struct insn opcode_e3[] = {
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{ "mfy", 0x5c, INSTR_RXY_RRRD },
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{ "mhy", 0x7c, INSTR_RXY_RRRD },
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{ "pfd", 0x36, INSTR_RXY_URRD },
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{ "lbh", 0xc0, INSTR_RXY_RRRD },
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{ "llch", 0xc2, INSTR_RXY_RRRD },
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{ "stch", 0xc3, INSTR_RXY_RRRD },
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{ "lhh", 0xc4, INSTR_RXY_RRRD },
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{ "llhh", 0xc6, INSTR_RXY_RRRD },
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{ "sthh", 0xc7, INSTR_RXY_RRRD },
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{ "lfh", 0xca, INSTR_RXY_RRRD },
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{ "stfh", 0xcb, INSTR_RXY_RRRD },
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{ "chf", 0xcd, INSTR_RXY_RRRD },
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{ "clhf", 0xcf, INSTR_RXY_RRRD },
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#endif
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{ "lrv", 0x1e, INSTR_RXY_RRRD },
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{ "lrvh", 0x1f, INSTR_RXY_RRRD },
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@ -1080,9 +1168,9 @@ static struct insn opcode_e5[] = {
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{ "chhsi", 0x54, INSTR_SIL_RDI },
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{ "chsi", 0x5c, INSTR_SIL_RDI },
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{ "cghsi", 0x58, INSTR_SIL_RDI },
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{ "clhhsi", 0x55, INSTR_SIL_RDU },
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{ "clfhsi", 0x5d, INSTR_SIL_RDU },
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{ "clghsi", 0x59, INSTR_SIL_RDU },
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{ { 0, LONG_INSN_CLHHSI }, 0x55, INSTR_SIL_RDU },
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{ { 0, LONG_INSN_CLFHSI }, 0x5d, INSTR_SIL_RDU },
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{ { 0, LONG_INSN_CLGHSI }, 0x59, INSTR_SIL_RDU },
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{ "mvhhi", 0x44, INSTR_SIL_RDI },
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{ "mvhi", 0x4c, INSTR_SIL_RDI },
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{ "mvghi", 0x48, INSTR_SIL_RDI },
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@ -1137,6 +1225,24 @@ static struct insn opcode_eb[] = {
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{ "alsi", 0x6e, INSTR_SIY_IRD },
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{ "algsi", 0x7e, INSTR_SIY_IRD },
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{ "ecag", 0x4c, INSTR_RSY_RRRD },
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{ "srak", 0xdc, INSTR_RSY_RRRD },
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{ "slak", 0xdd, INSTR_RSY_RRRD },
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{ "srlk", 0xde, INSTR_RSY_RRRD },
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{ "sllk", 0xdf, INSTR_RSY_RRRD },
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{ "locg", 0xe2, INSTR_RSY_RDRM },
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{ "stocg", 0xe3, INSTR_RSY_RDRM },
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{ "lang", 0xe4, INSTR_RSY_RRRD },
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{ "laog", 0xe6, INSTR_RSY_RRRD },
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{ "laxg", 0xe7, INSTR_RSY_RRRD },
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{ "laag", 0xe8, INSTR_RSY_RRRD },
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{ "laalg", 0xea, INSTR_RSY_RRRD },
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{ "loc", 0xf2, INSTR_RSY_RDRM },
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{ "stoc", 0xf3, INSTR_RSY_RDRM },
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{ "lan", 0xf4, INSTR_RSY_RRRD },
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{ "lao", 0xf6, INSTR_RSY_RRRD },
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{ "lax", 0xf7, INSTR_RSY_RRRD },
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{ "laa", 0xf8, INSTR_RSY_RRRD },
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{ "laal", 0xfa, INSTR_RSY_RRRD },
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#endif
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{ "rll", 0x1d, INSTR_RSY_RRRD },
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{ "mvclu", 0x8e, INSTR_RSY_RRRD },
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@ -1172,6 +1278,12 @@ static struct insn opcode_ec[] = {
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{ "rxsbg", 0x57, INSTR_RIE_RRUUU },
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{ "rosbg", 0x56, INSTR_RIE_RRUUU },
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{ "risbg", 0x55, INSTR_RIE_RRUUU },
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{ { 0, LONG_INSN_RISBLG }, 0x51, INSTR_RIE_RRUUU },
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{ { 0, LONG_INSN_RISBHG }, 0x5D, INSTR_RIE_RRUUU },
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{ "ahik", 0xd8, INSTR_RIE_RRI0 },
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{ "aghik", 0xd9, INSTR_RIE_RRI0 },
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{ { 0, LONG_INSN_ALHSIK }, 0xda, INSTR_RIE_RRI0 },
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{ { 0, LONG_INSN_ALGHSIK }, 0xdb, INSTR_RIE_RRI0 },
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#endif
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{ "", 0, INSTR_INVALID }
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};
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@ -1321,6 +1433,9 @@ static struct insn *find_insn(unsigned char *code)
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case 0xc8:
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table = opcode_c8;
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break;
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case 0xcc:
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table = opcode_cc;
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break;
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case 0xe3:
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table = opcode_e3;
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opfrag = code[5];
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@ -1367,7 +1482,11 @@ static int print_insn(char *buffer, unsigned char *code, unsigned long addr)
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ptr = buffer;
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insn = find_insn(code);
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if (insn) {
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ptr += sprintf(ptr, "%.5s\t", insn->name);
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if (insn->name[0] == '\0')
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ptr += sprintf(ptr, "%s\t",
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long_insn_name[(int) insn->name[1]]);
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else
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ptr += sprintf(ptr, "%.5s\t", insn->name);
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/* Extract the operands. */
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separator = 0;
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for (ops = formats[insn->format] + 1, i = 0;
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