mirror of https://gitee.com/openkylin/linux.git
OMAP2, 3: DSS2: Move clocks from core driver to dss driver
All clock management is moved to dss platform driver. clk_get/put APIs use dss device instead of core platform device. Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So the device name is changed from omapdss to omapdss_dss in 2420, 2430, 3xxx clock database files. Now the core driver "omapdss" only takes care of panel registration with the custom bus. core driver also uses the clk_enable() / clk_disable() APIs exposed by DSS for clock management. DSS driver would do clock management of clocks needed by DISPC, RFBI, DSI, VENC TODO: The clock content would be adapted to omap_hwmod in a seperate series. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Senthilvadivu Guruswamy
Tomi Valkeinen
parent
96c401bcb8
commit
8b9cb3a8f3
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@ -1786,10 +1786,10 @@ static struct omap_clk omap2420_clks[] = {
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CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
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CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
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/* DSS domain clocks */
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CLK("omapdss", "ick", &dss_ick, CK_242X),
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CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X),
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CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X),
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CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X),
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CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
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CLK("omapdss_dss", "dss1_fck", &dss1_fck, CK_242X),
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CLK("omapdss_dss", "dss2_fck", &dss2_fck, CK_242X),
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CLK("omapdss_dss", "tv_fck", &dss_54m_fck, CK_242X),
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/* L3 domain clocks */
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CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
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CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
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@ -1890,10 +1890,10 @@ static struct omap_clk omap2430_clks[] = {
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CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
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CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
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/* DSS domain clocks */
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CLK("omapdss", "ick", &dss_ick, CK_243X),
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CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X),
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CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X),
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CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X),
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CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
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CLK("omapdss_dss", "dss1_fck", &dss1_fck, CK_243X),
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CLK("omapdss_dss", "dss2_fck", &dss2_fck, CK_243X),
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CLK("omapdss_dss", "tv_fck", &dss_54m_fck, CK_243X),
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/* L3 domain clocks */
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CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
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CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
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@ -3357,13 +3357,13 @@ static struct omap_clk omap3xxx_clks[] = {
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CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
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CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
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CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
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CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
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CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
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CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX),
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CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX),
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CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX),
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CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
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CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
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CLK("omapdss_dss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
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CLK("omapdss_dss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
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CLK("omapdss_dss", "tv_fck", &dss_tv_fck, CK_3XXX),
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CLK("omapdss_dss", "video_fck", &dss_96m_fck, CK_3XXX),
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CLK("omapdss_dss", "dss2_fck", &dss2_alwon_fck, CK_3XXX),
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CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
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CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
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CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
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CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
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CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
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@ -34,32 +34,18 @@
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#include <linux/regulator/consumer.h>
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#include <plat/display.h>
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#include <plat/clock.h>
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#include "dss.h"
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#include "dss_features.h"
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static struct {
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struct platform_device *pdev;
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int ctx_id;
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struct clk *dss_ick;
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struct clk *dss1_fck;
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struct clk *dss2_fck;
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struct clk *dss_54m_fck;
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struct clk *dss_96m_fck;
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unsigned num_clks_enabled;
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struct regulator *vdds_dsi_reg;
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struct regulator *vdds_sdi_reg;
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struct regulator *vdda_dac_reg;
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} core;
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static void dss_clk_enable_all_no_ctx(void);
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static void dss_clk_disable_all_no_ctx(void);
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static void dss_clk_enable_no_ctx(enum dss_clock clks);
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static void dss_clk_disable_no_ctx(enum dss_clock clks);
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static char *def_disp_name;
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module_param_named(def_disp, def_disp_name, charp, 0);
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MODULE_PARM_DESC(def_disp_name, "default display name");
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@ -69,297 +55,6 @@ unsigned int dss_debug;
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module_param_named(debug, dss_debug, bool, 0644);
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#endif
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/* CONTEXT */
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static int dss_get_ctx_id(void)
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{
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struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
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int r;
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if (!pdata->get_last_off_on_transaction_id)
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return 0;
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r = pdata->get_last_off_on_transaction_id(&core.pdev->dev);
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if (r < 0) {
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dev_err(&core.pdev->dev, "getting transaction ID failed, "
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"will force context restore\n");
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r = -1;
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}
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return r;
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}
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int dss_need_ctx_restore(void)
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{
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int id = dss_get_ctx_id();
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if (id < 0 || id != core.ctx_id) {
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DSSDBG("ctx id %d -> id %d\n",
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core.ctx_id, id);
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core.ctx_id = id;
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return 1;
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} else {
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return 0;
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}
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}
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static void save_all_ctx(void)
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{
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DSSDBG("save context\n");
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dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_save_context();
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dispc_save_context();
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#ifdef CONFIG_OMAP2_DSS_DSI
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dsi_save_context();
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#endif
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dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
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}
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static void restore_all_ctx(void)
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{
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DSSDBG("restore context\n");
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dss_clk_enable_all_no_ctx();
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dss_restore_context();
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dispc_restore_context();
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#ifdef CONFIG_OMAP2_DSS_DSI
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dsi_restore_context();
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#endif
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dss_clk_disable_all_no_ctx();
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}
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#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
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/* CLOCKS */
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static void core_dump_clocks(struct seq_file *s)
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{
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int i;
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struct clk *clocks[5] = {
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core.dss_ick,
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core.dss1_fck,
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core.dss2_fck,
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core.dss_54m_fck,
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core.dss_96m_fck
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};
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seq_printf(s, "- CORE -\n");
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seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled);
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for (i = 0; i < 5; i++) {
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if (!clocks[i])
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continue;
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seq_printf(s, "%-15s\t%lu\t%d\n",
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clocks[i]->name,
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clk_get_rate(clocks[i]),
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clocks[i]->usecount);
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}
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}
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#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
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static int dss_get_clock(struct clk **clock, const char *clk_name)
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{
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struct clk *clk;
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clk = clk_get(&core.pdev->dev, clk_name);
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if (IS_ERR(clk)) {
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DSSERR("can't get clock %s", clk_name);
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return PTR_ERR(clk);
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}
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*clock = clk;
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DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
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return 0;
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}
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static int dss_get_clocks(void)
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{
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int r;
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core.dss_ick = NULL;
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core.dss1_fck = NULL;
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core.dss2_fck = NULL;
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core.dss_54m_fck = NULL;
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core.dss_96m_fck = NULL;
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r = dss_get_clock(&core.dss_ick, "ick");
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if (r)
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goto err;
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r = dss_get_clock(&core.dss1_fck, "dss1_fck");
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if (r)
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goto err;
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r = dss_get_clock(&core.dss2_fck, "dss2_fck");
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if (r)
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goto err;
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r = dss_get_clock(&core.dss_54m_fck, "tv_fck");
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if (r)
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goto err;
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r = dss_get_clock(&core.dss_96m_fck, "video_fck");
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if (r)
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goto err;
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return 0;
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err:
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if (core.dss_ick)
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clk_put(core.dss_ick);
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if (core.dss1_fck)
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clk_put(core.dss1_fck);
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if (core.dss2_fck)
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clk_put(core.dss2_fck);
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if (core.dss_54m_fck)
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clk_put(core.dss_54m_fck);
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if (core.dss_96m_fck)
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clk_put(core.dss_96m_fck);
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return r;
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}
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static void dss_put_clocks(void)
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{
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if (core.dss_96m_fck)
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clk_put(core.dss_96m_fck);
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clk_put(core.dss_54m_fck);
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clk_put(core.dss1_fck);
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clk_put(core.dss2_fck);
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clk_put(core.dss_ick);
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}
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unsigned long dss_clk_get_rate(enum dss_clock clk)
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{
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switch (clk) {
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case DSS_CLK_ICK:
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return clk_get_rate(core.dss_ick);
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case DSS_CLK_FCK1:
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return clk_get_rate(core.dss1_fck);
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case DSS_CLK_FCK2:
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return clk_get_rate(core.dss2_fck);
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case DSS_CLK_54M:
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return clk_get_rate(core.dss_54m_fck);
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case DSS_CLK_96M:
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return clk_get_rate(core.dss_96m_fck);
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}
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BUG();
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return 0;
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}
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static unsigned count_clk_bits(enum dss_clock clks)
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{
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unsigned num_clks = 0;
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if (clks & DSS_CLK_ICK)
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++num_clks;
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if (clks & DSS_CLK_FCK1)
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++num_clks;
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if (clks & DSS_CLK_FCK2)
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++num_clks;
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if (clks & DSS_CLK_54M)
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++num_clks;
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if (clks & DSS_CLK_96M)
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++num_clks;
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return num_clks;
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}
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static void dss_clk_enable_no_ctx(enum dss_clock clks)
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{
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unsigned num_clks = count_clk_bits(clks);
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if (clks & DSS_CLK_ICK)
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clk_enable(core.dss_ick);
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if (clks & DSS_CLK_FCK1)
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clk_enable(core.dss1_fck);
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if (clks & DSS_CLK_FCK2)
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clk_enable(core.dss2_fck);
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if (clks & DSS_CLK_54M)
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clk_enable(core.dss_54m_fck);
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if (clks & DSS_CLK_96M)
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clk_enable(core.dss_96m_fck);
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core.num_clks_enabled += num_clks;
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}
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void dss_clk_enable(enum dss_clock clks)
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{
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bool check_ctx = core.num_clks_enabled == 0;
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dss_clk_enable_no_ctx(clks);
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if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
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restore_all_ctx();
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}
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static void dss_clk_disable_no_ctx(enum dss_clock clks)
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{
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unsigned num_clks = count_clk_bits(clks);
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if (clks & DSS_CLK_ICK)
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clk_disable(core.dss_ick);
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if (clks & DSS_CLK_FCK1)
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clk_disable(core.dss1_fck);
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if (clks & DSS_CLK_FCK2)
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clk_disable(core.dss2_fck);
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if (clks & DSS_CLK_54M)
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clk_disable(core.dss_54m_fck);
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if (clks & DSS_CLK_96M)
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clk_disable(core.dss_96m_fck);
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core.num_clks_enabled -= num_clks;
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}
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void dss_clk_disable(enum dss_clock clks)
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{
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if (cpu_is_omap34xx()) {
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unsigned num_clks = count_clk_bits(clks);
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BUG_ON(core.num_clks_enabled < num_clks);
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if (core.num_clks_enabled == num_clks)
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save_all_ctx();
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}
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dss_clk_disable_no_ctx(clks);
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}
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static void dss_clk_enable_all_no_ctx(void)
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{
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enum dss_clock clks;
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clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
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if (cpu_is_omap34xx())
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clks |= DSS_CLK_96M;
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dss_clk_enable_no_ctx(clks);
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}
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static void dss_clk_disable_all_no_ctx(void)
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{
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enum dss_clock clks;
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clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
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if (cpu_is_omap34xx())
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clks |= DSS_CLK_96M;
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dss_clk_disable_no_ctx(clks);
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}
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static void dss_clk_disable_all(void)
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{
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enum dss_clock clks;
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clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
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if (cpu_is_omap34xx())
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clks |= DSS_CLK_96M;
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dss_clk_disable(clks);
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}
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/* REGULATORS */
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struct regulator *dss_get_vdds_dsi(void)
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@ -404,18 +99,7 @@ struct regulator *dss_get_vdda_dac(void)
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return reg;
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}
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/* DEBUGFS */
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#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
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static void dss_debug_dump_clocks(struct seq_file *s)
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{
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core_dump_clocks(s);
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dss_dump_clocks(s);
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dispc_dump_clocks(s);
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#ifdef CONFIG_OMAP2_DSS_DSI
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dsi_dump_clocks(s);
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#endif
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}
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static int dss_debug_show(struct seq_file *s, void *unused)
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{
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void (*func)(struct seq_file *) = s->private;
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@ -508,21 +192,15 @@ static int omap_dss_probe(struct platform_device *pdev)
|
|||
dss_init_overlay_managers(pdev);
|
||||
dss_init_overlays(pdev);
|
||||
|
||||
r = dss_get_clocks();
|
||||
if (r)
|
||||
goto err_clocks;
|
||||
|
||||
dss_clk_enable_all_no_ctx();
|
||||
|
||||
core.ctx_id = dss_get_ctx_id();
|
||||
DSSDBG("initial ctx id %u\n", core.ctx_id);
|
||||
|
||||
r = dss_init_platform_driver();
|
||||
if (r) {
|
||||
DSSERR("Failed to initialize DSS platform driver\n");
|
||||
goto err_dss;
|
||||
}
|
||||
|
||||
/* keep clocks enabled to prevent context saves/restores during init */
|
||||
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
|
||||
r = rfbi_init();
|
||||
if (r) {
|
||||
DSSERR("Failed to initialize rfbi\n");
|
||||
|
|
@ -588,7 +266,7 @@ static int omap_dss_probe(struct platform_device *pdev)
|
|||
pdata->default_device = dssdev;
|
||||
}
|
||||
|
||||
dss_clk_disable_all();
|
||||
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
@ -611,9 +289,6 @@ static int omap_dss_probe(struct platform_device *pdev)
|
|||
err_rfbi:
|
||||
dss_uninit_platform_driver();
|
||||
err_dss:
|
||||
dss_clk_disable_all_no_ctx();
|
||||
dss_put_clocks();
|
||||
err_clocks:
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
@ -636,16 +311,6 @@ static int omap_dss_remove(struct platform_device *pdev)
|
|||
|
||||
dss_uninit_platform_driver();
|
||||
|
||||
/*
|
||||
* As part of hwmod changes, DSS is not the only controller of dss
|
||||
* clocks; hwmod framework itself will also enable clocks during hwmod
|
||||
* init for dss, and autoidle is set in h/w for DSS. Hence, there's no
|
||||
* need to disable clocks if their usecounts > 1.
|
||||
*/
|
||||
WARN_ON(core.num_clks_enabled > 0);
|
||||
|
||||
dss_put_clocks();
|
||||
|
||||
dss_uninit_overlays(pdev);
|
||||
dss_uninit_overlay_managers(pdev);
|
||||
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
#include <linux/clk.h>
|
||||
|
||||
#include <plat/display.h>
|
||||
#include <plat/clock.h>
|
||||
#include "dss.h"
|
||||
|
||||
#define DSS_BASE 0x48050000
|
||||
|
|
@ -61,8 +62,15 @@ struct dss_reg {
|
|||
static struct {
|
||||
struct platform_device *pdev;
|
||||
void __iomem *base;
|
||||
int ctx_id;
|
||||
|
||||
struct clk *dpll4_m4_ck;
|
||||
struct clk *dss_ick;
|
||||
struct clk *dss1_fck;
|
||||
struct clk *dss2_fck;
|
||||
struct clk *dss_54m_fck;
|
||||
struct clk *dss_96m_fck;
|
||||
unsigned num_clks_enabled;
|
||||
|
||||
unsigned long cache_req_pck;
|
||||
unsigned long cache_prate;
|
||||
|
|
@ -75,6 +83,11 @@ static struct {
|
|||
u32 ctx[DSS_SZ_REGS / sizeof(u32)];
|
||||
} dss;
|
||||
|
||||
static void dss_clk_enable_all_no_ctx(void);
|
||||
static void dss_clk_disable_all_no_ctx(void);
|
||||
static void dss_clk_enable_no_ctx(enum dss_clock clks);
|
||||
static void dss_clk_disable_no_ctx(enum dss_clock clks);
|
||||
|
||||
static int _omap_dss_wait_reset(void);
|
||||
|
||||
static inline void dss_write_reg(const struct dss_reg idx, u32 val)
|
||||
|
|
@ -640,6 +653,301 @@ static void dss_exit(void)
|
|||
iounmap(dss.base);
|
||||
}
|
||||
|
||||
/* CONTEXT */
|
||||
static int dss_get_ctx_id(void)
|
||||
{
|
||||
struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
|
||||
int r;
|
||||
|
||||
if (!pdata->board_data->get_last_off_on_transaction_id)
|
||||
return 0;
|
||||
r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev);
|
||||
if (r < 0) {
|
||||
dev_err(&dss.pdev->dev, "getting transaction ID failed, "
|
||||
"will force context restore\n");
|
||||
r = -1;
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
||||
int dss_need_ctx_restore(void)
|
||||
{
|
||||
int id = dss_get_ctx_id();
|
||||
|
||||
if (id < 0 || id != dss.ctx_id) {
|
||||
DSSDBG("ctx id %d -> id %d\n",
|
||||
dss.ctx_id, id);
|
||||
dss.ctx_id = id;
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void save_all_ctx(void)
|
||||
{
|
||||
DSSDBG("save context\n");
|
||||
|
||||
dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
|
||||
dss_save_context();
|
||||
dispc_save_context();
|
||||
#ifdef CONFIG_OMAP2_DSS_DSI
|
||||
dsi_save_context();
|
||||
#endif
|
||||
|
||||
dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
|
||||
}
|
||||
|
||||
static void restore_all_ctx(void)
|
||||
{
|
||||
DSSDBG("restore context\n");
|
||||
|
||||
dss_clk_enable_all_no_ctx();
|
||||
|
||||
dss_restore_context();
|
||||
dispc_restore_context();
|
||||
#ifdef CONFIG_OMAP2_DSS_DSI
|
||||
dsi_restore_context();
|
||||
#endif
|
||||
|
||||
dss_clk_disable_all_no_ctx();
|
||||
}
|
||||
|
||||
static int dss_get_clock(struct clk **clock, const char *clk_name)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
clk = clk_get(&dss.pdev->dev, clk_name);
|
||||
|
||||
if (IS_ERR(clk)) {
|
||||
DSSERR("can't get clock %s", clk_name);
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
*clock = clk;
|
||||
|
||||
DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dss_get_clocks(void)
|
||||
{
|
||||
int r;
|
||||
|
||||
dss.dss_ick = NULL;
|
||||
dss.dss1_fck = NULL;
|
||||
dss.dss2_fck = NULL;
|
||||
dss.dss_54m_fck = NULL;
|
||||
dss.dss_96m_fck = NULL;
|
||||
|
||||
r = dss_get_clock(&dss.dss_ick, "ick");
|
||||
if (r)
|
||||
goto err;
|
||||
|
||||
r = dss_get_clock(&dss.dss1_fck, "dss1_fck");
|
||||
if (r)
|
||||
goto err;
|
||||
|
||||
r = dss_get_clock(&dss.dss2_fck, "dss2_fck");
|
||||
if (r)
|
||||
goto err;
|
||||
|
||||
r = dss_get_clock(&dss.dss_54m_fck, "tv_fck");
|
||||
if (r)
|
||||
goto err;
|
||||
|
||||
r = dss_get_clock(&dss.dss_96m_fck, "video_fck");
|
||||
if (r)
|
||||
goto err;
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
if (dss.dss_ick)
|
||||
clk_put(dss.dss_ick);
|
||||
if (dss.dss1_fck)
|
||||
clk_put(dss.dss1_fck);
|
||||
if (dss.dss2_fck)
|
||||
clk_put(dss.dss2_fck);
|
||||
if (dss.dss_54m_fck)
|
||||
clk_put(dss.dss_54m_fck);
|
||||
if (dss.dss_96m_fck)
|
||||
clk_put(dss.dss_96m_fck);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static void dss_put_clocks(void)
|
||||
{
|
||||
if (dss.dss_96m_fck)
|
||||
clk_put(dss.dss_96m_fck);
|
||||
clk_put(dss.dss_54m_fck);
|
||||
clk_put(dss.dss1_fck);
|
||||
clk_put(dss.dss2_fck);
|
||||
clk_put(dss.dss_ick);
|
||||
}
|
||||
|
||||
unsigned long dss_clk_get_rate(enum dss_clock clk)
|
||||
{
|
||||
switch (clk) {
|
||||
case DSS_CLK_ICK:
|
||||
return clk_get_rate(dss.dss_ick);
|
||||
case DSS_CLK_FCK1:
|
||||
return clk_get_rate(dss.dss1_fck);
|
||||
case DSS_CLK_FCK2:
|
||||
return clk_get_rate(dss.dss2_fck);
|
||||
case DSS_CLK_54M:
|
||||
return clk_get_rate(dss.dss_54m_fck);
|
||||
case DSS_CLK_96M:
|
||||
return clk_get_rate(dss.dss_96m_fck);
|
||||
}
|
||||
|
||||
BUG();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned count_clk_bits(enum dss_clock clks)
|
||||
{
|
||||
unsigned num_clks = 0;
|
||||
|
||||
if (clks & DSS_CLK_ICK)
|
||||
++num_clks;
|
||||
if (clks & DSS_CLK_FCK1)
|
||||
++num_clks;
|
||||
if (clks & DSS_CLK_FCK2)
|
||||
++num_clks;
|
||||
if (clks & DSS_CLK_54M)
|
||||
++num_clks;
|
||||
if (clks & DSS_CLK_96M)
|
||||
++num_clks;
|
||||
|
||||
return num_clks;
|
||||
}
|
||||
|
||||
static void dss_clk_enable_no_ctx(enum dss_clock clks)
|
||||
{
|
||||
unsigned num_clks = count_clk_bits(clks);
|
||||
|
||||
if (clks & DSS_CLK_ICK)
|
||||
clk_enable(dss.dss_ick);
|
||||
if (clks & DSS_CLK_FCK1)
|
||||
clk_enable(dss.dss1_fck);
|
||||
if (clks & DSS_CLK_FCK2)
|
||||
clk_enable(dss.dss2_fck);
|
||||
if (clks & DSS_CLK_54M)
|
||||
clk_enable(dss.dss_54m_fck);
|
||||
if (clks & DSS_CLK_96M)
|
||||
clk_enable(dss.dss_96m_fck);
|
||||
|
||||
dss.num_clks_enabled += num_clks;
|
||||
}
|
||||
|
||||
void dss_clk_enable(enum dss_clock clks)
|
||||
{
|
||||
bool check_ctx = dss.num_clks_enabled == 0;
|
||||
|
||||
dss_clk_enable_no_ctx(clks);
|
||||
|
||||
if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
|
||||
restore_all_ctx();
|
||||
}
|
||||
|
||||
static void dss_clk_disable_no_ctx(enum dss_clock clks)
|
||||
{
|
||||
unsigned num_clks = count_clk_bits(clks);
|
||||
|
||||
if (clks & DSS_CLK_ICK)
|
||||
clk_disable(dss.dss_ick);
|
||||
if (clks & DSS_CLK_FCK1)
|
||||
clk_disable(dss.dss1_fck);
|
||||
if (clks & DSS_CLK_FCK2)
|
||||
clk_disable(dss.dss2_fck);
|
||||
if (clks & DSS_CLK_54M)
|
||||
clk_disable(dss.dss_54m_fck);
|
||||
if (clks & DSS_CLK_96M)
|
||||
clk_disable(dss.dss_96m_fck);
|
||||
|
||||
dss.num_clks_enabled -= num_clks;
|
||||
}
|
||||
|
||||
void dss_clk_disable(enum dss_clock clks)
|
||||
{
|
||||
if (cpu_is_omap34xx()) {
|
||||
unsigned num_clks = count_clk_bits(clks);
|
||||
|
||||
BUG_ON(dss.num_clks_enabled < num_clks);
|
||||
|
||||
if (dss.num_clks_enabled == num_clks)
|
||||
save_all_ctx();
|
||||
}
|
||||
|
||||
dss_clk_disable_no_ctx(clks);
|
||||
}
|
||||
|
||||
static void dss_clk_enable_all_no_ctx(void)
|
||||
{
|
||||
enum dss_clock clks;
|
||||
|
||||
clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
|
||||
if (cpu_is_omap34xx())
|
||||
clks |= DSS_CLK_96M;
|
||||
dss_clk_enable_no_ctx(clks);
|
||||
}
|
||||
|
||||
static void dss_clk_disable_all_no_ctx(void)
|
||||
{
|
||||
enum dss_clock clks;
|
||||
|
||||
clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
|
||||
if (cpu_is_omap34xx())
|
||||
clks |= DSS_CLK_96M;
|
||||
dss_clk_disable_no_ctx(clks);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
|
||||
/* CLOCKS */
|
||||
static void core_dump_clocks(struct seq_file *s)
|
||||
{
|
||||
int i;
|
||||
struct clk *clocks[5] = {
|
||||
dss.dss_ick,
|
||||
dss.dss1_fck,
|
||||
dss.dss2_fck,
|
||||
dss.dss_54m_fck,
|
||||
dss.dss_96m_fck
|
||||
};
|
||||
|
||||
seq_printf(s, "- CORE -\n");
|
||||
|
||||
seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled);
|
||||
|
||||
for (i = 0; i < 5; i++) {
|
||||
if (!clocks[i])
|
||||
continue;
|
||||
seq_printf(s, "%-15s\t%lu\t%d\n",
|
||||
clocks[i]->name,
|
||||
clk_get_rate(clocks[i]),
|
||||
clocks[i]->usecount);
|
||||
}
|
||||
}
|
||||
#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
|
||||
|
||||
/* DEBUGFS */
|
||||
#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
|
||||
void dss_debug_dump_clocks(struct seq_file *s)
|
||||
{
|
||||
core_dump_clocks(s);
|
||||
dss_dump_clocks(s);
|
||||
dispc_dump_clocks(s);
|
||||
#ifdef CONFIG_OMAP2_DSS_DSI
|
||||
dsi_dump_clocks(s);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* DSS HW IP initialisation */
|
||||
static int omap_dsshw_probe(struct platform_device *pdev)
|
||||
{
|
||||
|
|
@ -648,6 +956,15 @@ static int omap_dsshw_probe(struct platform_device *pdev)
|
|||
|
||||
dss.pdev = pdev;
|
||||
|
||||
r = dss_get_clocks();
|
||||
if (r)
|
||||
goto err_clocks;
|
||||
|
||||
dss_clk_enable_all_no_ctx();
|
||||
|
||||
dss.ctx_id = dss_get_ctx_id();
|
||||
DSSDBG("initial ctx id %u\n", dss.ctx_id);
|
||||
|
||||
#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
|
||||
/* DISPC_CONTROL */
|
||||
if (omap_readl(0x48050440) & 1) /* LCD enabled? */
|
||||
|
|
@ -660,15 +977,30 @@ static int omap_dsshw_probe(struct platform_device *pdev)
|
|||
goto err_dss;
|
||||
}
|
||||
|
||||
err_dss:
|
||||
dss_clk_disable_all_no_ctx();
|
||||
return 0;
|
||||
|
||||
err_dss:
|
||||
dss_clk_disable_all_no_ctx();
|
||||
dss_put_clocks();
|
||||
err_clocks:
|
||||
return r;
|
||||
}
|
||||
|
||||
static int omap_dsshw_remove(struct platform_device *pdev)
|
||||
{
|
||||
|
||||
dss_exit();
|
||||
|
||||
/*
|
||||
* As part of hwmod changes, DSS is not the only controller of dss
|
||||
* clocks; hwmod framework itself will also enable clocks during hwmod
|
||||
* init for dss, and autoidle is set in h/w for DSS. Hence, there's no
|
||||
* need to disable clocks if their usecounts > 1.
|
||||
*/
|
||||
WARN_ON(dss.num_clks_enabled > 0);
|
||||
|
||||
dss_put_clocks();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -169,11 +169,6 @@ struct seq_file;
|
|||
struct platform_device;
|
||||
|
||||
/* core */
|
||||
void dss_clk_enable(enum dss_clock clks);
|
||||
void dss_clk_disable(enum dss_clock clks);
|
||||
unsigned long dss_clk_get_rate(enum dss_clock clk);
|
||||
int dss_need_ctx_restore(void);
|
||||
void dss_dump_clocks(struct seq_file *s);
|
||||
struct bus_type *dss_get_bus(void);
|
||||
struct regulator *dss_get_vdds_dsi(void);
|
||||
struct regulator *dss_get_vdds_sdi(void);
|
||||
|
|
@ -219,8 +214,16 @@ void dss_uninit_platform_driver(void);
|
|||
|
||||
void dss_save_context(void);
|
||||
void dss_restore_context(void);
|
||||
void dss_clk_enable(enum dss_clock clks);
|
||||
void dss_clk_disable(enum dss_clock clks);
|
||||
unsigned long dss_clk_get_rate(enum dss_clock clk);
|
||||
int dss_need_ctx_restore(void);
|
||||
void dss_dump_clocks(struct seq_file *s);
|
||||
|
||||
void dss_dump_regs(struct seq_file *s);
|
||||
#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
|
||||
void dss_debug_dump_clocks(struct seq_file *s);
|
||||
#endif
|
||||
|
||||
void dss_sdi_init(u8 datapairs);
|
||||
int dss_sdi_enable(void);
|
||||
|
|
|
|||
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Reference in New Issue