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drm/i915/skl: Implement WaDisableLSQCROPERFforOCL 

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Damien Lespiau 2015-02-09 19:33:18 +00:00 committed by Daniel Vetter
parent 9370cd987e
commit 8bc0ccf6b1
3 changed files with 9 additions and 0 deletions
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1
drivers/gpu/drm/i915/i915_drv.h
View File

@ -2396,6 +2396,7 @@ struct drm_i915_cmd_table {
#define SKL_REVID_B0 (0x1)
#define SKL_REVID_C0 (0x2)
#define SKL_REVID_D0 (0x3)
#define SKL_REVID_E0 (0x4)
/*
* The genX designation typically refers to the render engine, so render

3
drivers/gpu/drm/i915/i915_reg.h
View File

@ -5259,6 +5259,9 @@ enum skl_disp_power_wells {
#define GEN7_L3SQCREG4 0xb034
#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
#define GEN8_L3SQCREG4 0xb118
#define GEN8_LQSC_RO_PERF_DIS (1<<27)
/* GEN8 chicken */
#define HDC_CHICKEN0 0x7300
#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)

5
drivers/gpu/drm/i915/intel_pm.c
View File

@ -65,6 +65,11 @@ static void skl_init_clock_gating(struct drm_device *dev)
GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
}
if (INTEL_REVID(dev) <= SKL_REVID_E0)
/* WaDisableLSQCROPERFforOCL:skl */
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_RO_PERF_DIS);
}
static void i915_pineview_get_mem_freq(struct drm_device *dev)