mirror of https://gitee.com/openkylin/linux.git
ARM: dts: exynos: Remove Exynos5440
The Exynos5440 (quad-core A15 with GMAC, PCIe, SATA) was targeting server platforms but it did not make it to the market really. There are no development boards with it and probably there are no real products neither. The development for Exynos5440 ended in 2013 and since then the platform is in maintenance mode. Remove all Device Tree sources for Exynos5440, as first step of removal of the platform to simplify the code and drivers. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Andi Shyti <andi@etezian.org> Reviewed-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
parent
c5154ca502
commit
8c83315da1
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@ -21,8 +21,6 @@ Required root node properties:
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- "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
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- "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
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- "samsung,tm2e" - for Exynos5433-based Samsung TM2E board.
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- "samsung,sd5v1" - for Exynos5440-based Samsung board.
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- "samsung,ssdk5440" - for Exynos5440-based Samsung board.
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* Other companies Exynos SoC based
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* FriendlyARM
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@ -190,8 +190,6 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
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exynos5422-odroidxu3.dtb \
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exynos5422-odroidxu3-lite.dtb \
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exynos5422-odroidxu4.dtb \
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exynos5440-sd5v1.dtb \
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exynos5440-ssdk5440.dtb \
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exynos5800-peach-pi.dtb
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dtb-$(CONFIG_ARCH_GEMINI) += \
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gemini-dlink-dir-685.dtb \
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@ -1,42 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* SAMSUNG SD5v1 board device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*/
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/dts-v1/;
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#include "exynos5440.dtsi"
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/ {
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model = "SAMSUNG SD5v1 board based on EXYNOS5440";
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compatible = "samsung,sd5v1", "samsung,exynos5440", "samsung,exynos5";
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chosen {
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bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
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};
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/* FIXME: set reg property with correct start address and size */
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memory@0 {
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device_type = "memory";
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reg = <0 0>;
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};
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fixed-rate-clocks {
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xtal {
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compatible = "samsung,clock-xtal";
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clock-frequency = <50000000>;
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};
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};
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spi {
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status = "disabled";
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};
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};
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&gmac {
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fixed_phy;
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phy_addr = <1>;
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};
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@ -1,81 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* SAMSUNG SSDK5440 board device tree source
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*/
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/dts-v1/;
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#include "exynos5440.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
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compatible = "samsung,ssdk5440", "samsung,exynos5440", "samsung,exynos5";
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chosen {
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bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
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};
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/* FIXME: set reg property with correct start address and size */
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memory@0 {
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device_type = "memory";
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reg = <0 0>;
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};
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fixed-rate-clocks {
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xtal {
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compatible = "samsung,clock-xtal";
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clock-frequency = <50000000>;
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};
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};
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};
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&pcie_0 {
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reset-gpio = <&pin_ctrl 5 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&pcie_1 {
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reset-gpio = <&pin_ctrl 22 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&spi_0 {
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flash: w25q128@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "winbond,w25q128";
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spi-max-frequency = <15625000>;
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reg = <0>;
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controller-data {
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samsung,spi-feedback-delay = <0>;
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};
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partition@0 {
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label = "BootLoader";
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reg = <0x60000 0x80000>;
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read-only;
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};
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partition@e0000 {
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label = "Recovery-Kernel";
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reg = <0xe0000 0x300000>;
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read-only;
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};
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partition@3e0000 {
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label = "CRAM-FS";
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reg = <0x3e0000 0x700000>;
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read-only;
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};
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partition@ae0000 {
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label = "User-Data";
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reg = <0xae0000 0x520000>;
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};
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};
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};
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@ -1,20 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device tree sources for Exynos5440 TMU sensor configuration
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*
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* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
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*/
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#include <dt-bindings/thermal/thermal_exynos.h>
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#thermal-sensor-cells = <0>;
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samsung,tmu_gain = <5>;
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samsung,tmu_reference_voltage = <16>;
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samsung,tmu_noise_cancel_mode = <4>;
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samsung,tmu_efuse_value = <0x5d2d>;
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samsung,tmu_min_efuse_value = <16>;
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samsung,tmu_max_efuse_value = <76>;
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samsung,tmu_first_point_trim = <25>;
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samsung,tmu_second_point_trim = <70>;
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samsung,tmu_default_temp_offset = <25>;
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samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;
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@ -1,21 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device tree sources for default Exynos5440 thermal zone definition
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*
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* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
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*/
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polling-delay-passive = <0>;
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polling-delay = <0>;
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trips {
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cpu-alert-0 {
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temperature = <100000>; /* millicelsius */
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hysteresis = <0>; /* millicelsius */
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type = "active";
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};
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cpu-crit-0 {
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temperature = <105000>; /* millicelsius */
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hysteresis = <0>; /* millicelsius */
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type = "critical";
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};
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};
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@ -1,355 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* SAMSUNG EXYNOS5440 SoC device tree source
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*/
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#include <dt-bindings/clock/exynos5440.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "samsung,exynos5440", "samsung,exynos5";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &serial_0;
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serial1 = &serial_1;
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spi0 = &spi_0;
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tmuctrl0 = &tmuctrl_0;
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tmuctrl1 = &tmuctrl_1;
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tmuctrl2 = &tmuctrl_2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <3>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock: clock-controller@160000 {
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compatible = "samsung,exynos5440-clock";
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reg = <0x160000 0x1000>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@2e0000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x2E1000 0x1000>,
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<0x2E2000 0x2000>,
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<0x2E4000 0x2000>,
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<0x2E6000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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arm-pmu {
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compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,cortex-a15-timer",
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"arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <50000000>;
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};
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cpufreq@160000 {
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compatible = "samsung,exynos5440-cpufreq";
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reg = <0x160000 0x1000>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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operating-points = <
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/* KHz uV */
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1500000 1100000
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1400000 1075000
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1300000 1050000
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1200000 1025000
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1100000 1000000
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1000000 975000
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900000 950000
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800000 925000
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>;
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};
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serial_0: serial@b0000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0xB0000 0x1000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
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clock-names = "uart", "clk_uart_baud0";
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};
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serial_1: serial@c0000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0xC0000 0x1000>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
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clock-names = "uart", "clk_uart_baud0";
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};
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spi_0: spi@d0000 {
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compatible = "samsung,exynos5440-spi";
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reg = <0xD0000 0x100>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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samsung,spi-src-clk = <0>;
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num-cs = <1>;
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clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
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clock-names = "spi", "spi_busclk0";
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};
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pin_ctrl: pinctrl@e0000 {
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compatible = "samsung,exynos5440-pinctrl";
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reg = <0xE0000 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#gpio-cells = <2>;
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fan: fan {
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samsung,exynos5440-pin-function = <1>;
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};
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hdd_led0: hdd_led0 {
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samsung,exynos5440-pin-function = <2>;
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};
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hdd_led1: hdd_led1 {
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samsung,exynos5440-pin-function = <3>;
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};
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uart1: uart1 {
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samsung,exynos5440-pin-function = <4>;
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};
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};
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i2c@f0000 {
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compatible = "samsung,exynos5440-i2c";
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reg = <0xF0000 0x1000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_B_125>;
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clock-names = "i2c";
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};
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i2c@100000 {
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compatible = "samsung,exynos5440-i2c";
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reg = <0x100000 0x1000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_B_125>;
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clock-names = "i2c";
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};
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watchdog@110000 {
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compatible = "samsung,s3c6410-wdt";
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reg = <0x110000 0x1000>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "watchdog";
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};
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gmac: ethernet@230000 {
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compatible = "snps,dwmac-3.70a", "snps,dwmac";
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reg = <0x00230000 0x8000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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phy-mode = "sgmii";
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clocks = <&clock CLK_GMAC0>;
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clock-names = "stmmaceth";
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};
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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};
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rtc@130000 {
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compatible = "samsung,s3c6410-rtc";
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reg = <0x130000 0x1000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "rtc";
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};
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tmuctrl_0: tmuctrl@160118 {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x160118 0x230>, <0x160368 0x10>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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#include "exynos5440-tmu-sensor-conf.dtsi"
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};
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tmuctrl_1: tmuctrl@16011c {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x16011C 0x230>, <0x160368 0x10>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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#include "exynos5440-tmu-sensor-conf.dtsi"
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};
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tmuctrl_2: tmuctrl@160120 {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x160120 0x230>, <0x160368 0x10>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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#include "exynos5440-tmu-sensor-conf.dtsi"
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};
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sata@210000 {
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compatible = "snps,exynos5440-ahci";
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reg = <0x210000 0x10000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_SATA>;
|
||||
clock-names = "sata";
|
||||
};
|
||||
|
||||
ohci@220000 {
|
||||
compatible = "samsung,exynos5440-ohci";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_USB>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
ehci@221000 {
|
||||
compatible = "samsung,exynos5440-ehci";
|
||||
reg = <0x221000 0x1000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_USB>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
pcie_phy0: pcie-phy@270000 {
|
||||
#phy-cells = <0>;
|
||||
compatible = "samsung,exynos5440-pcie-phy";
|
||||
reg = <0x270000 0x1000>, <0x271000 0x40>;
|
||||
};
|
||||
|
||||
pcie_phy1: pcie-phy@272000 {
|
||||
#phy-cells = <0>;
|
||||
compatible = "samsung,exynos5440-pcie-phy";
|
||||
reg = <0x272000 0x1000>, <0x271040 0x40>;
|
||||
};
|
||||
|
||||
pcie_0: pcie@290000 {
|
||||
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
|
||||
reg = <0x290000 0x1000>, <0x40000000 0x1000>;
|
||||
reg-names = "elbi", "config";
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
phys = <&pcie_phy0>;
|
||||
ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
|
||||
bus-range = <0x00 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0x0 0 &gic 53>;
|
||||
num-lanes = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie_1: pcie@2a0000 {
|
||||
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
|
||||
reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
|
||||
reg-names = "elbi", "config";
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
phys = <&pcie_phy1>;
|
||||
ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
|
||||
bus-range = <0x00 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0x0 0 &gic 56>;
|
||||
num-lanes = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu0_thermal: cpu0-thermal {
|
||||
thermal-sensors = <&tmuctrl_0>;
|
||||
#include "exynos5440-trip-points.dtsi"
|
||||
};
|
||||
cpu1_thermal: cpu1-thermal {
|
||||
thermal-sensors = <&tmuctrl_1>;
|
||||
#include "exynos5440-trip-points.dtsi"
|
||||
};
|
||||
cpu2_thermal: cpu2-thermal {
|
||||
thermal-sensors = <&tmuctrl_2>;
|
||||
#include "exynos5440-trip-points.dtsi"
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue