mirror of https://gitee.com/openkylin/linux.git
Realtek Arm based SoC DT for v5.8
Add RTD1195, RTD1395 and RTD1619 SoCs as well as Xnano X5 TV box. Clean up memory nodes and /soc ranges. Factor out r-bus and partition it into CRT, Iso, Misc, SB2 and SCPU Wrapper blocks. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEF08DRxvMIhphdW+W+i7RLT5+AT8FAl64dfoRHGFmYWVyYmVy QHN1c2UuZGUACgkQ+i7RLT5+AT+iXA//eNc5DNAN7/B3GcoSaKd4jUfh4aCo2FkO octvWWuPdMom1zzzpR5GTi4AxFAj3V4gAwFc0SLxXRC1Mwb1QFoGVXsDsFXclhsA LdF73S2umVkl65kDvS8rLqq/1e4TidYI6Nlo5MQWcGrTrrkSZdLxiQlhokwsSoLf 6lS5SqTXuU0Y7b8TOAgsHXZ8HdeNuM0MBvLrNkWSQokFO8tRPYzP6FmrGCK0Z0DE dEarIAgrqw5OOoDgSNH80AWzUZGWJSR9gLsl9JwxgmQoG4b66HJrTYZHZ4ylFaeQ GsSwiuy7SM1NrU25i6qIGtj7WueGLYczLEBWwKg5AgNcFqq/hGwmoxsLRhJAyb1J jcUiH+sfR5fmcuFjA6k3MRD5rTporkS6e44Xni8/AaElSRgu+YYpsXAUeOenMR9m cDuR8DrOKkPWyipRK32WyQsF7P3JPaL9gD6q5hSdIAolEncR6LcHNkMUx0zgb/BL +gakFU4lmsV9SEFFVyKUr5w0fZLPPWdeXRFtKNZTsPI/AT4jPztIiszB9NWeumMZ 54uqsm9ct5flLFbqJ/575NDLQHoIY4uz6gZq/oRKdQ/g0AyCI80ZkqnMzm4om4GZ Fpdi63l+e2VAJE77R9tqxmj8LQJE9PfTZNo41zFA8gzCqmBN9Rrzs/E47KCLKQYq k54Vwaf891g= =wdYa -----END PGP SIGNATURE----- Merge tag 'realtek-dt-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek into arm/dt Realtek Arm based SoC DT for v5.8 Add RTD1195, RTD1395 and RTD1619 SoCs as well as Xnano X5 TV box. Clean up memory nodes and /soc ranges. Factor out r-bus and partition it into CRT, Iso, Misc, SB2 and SCPU Wrapper blocks. * tag 'realtek-dt-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek: (35 commits) dt-bindings: reset: rtd1295: Add SB2 reset arm64: dts: realtek: rtd16xx: Add SB2 and SCPU Wrapper syscon nodes arm64: dts: realtek: rtd139x: Add SB2 and SCPU Wrapper syscon nodes arm64: dts: realtek: rtd129x: Add SB2 and SCPU Wrapper syscon nodes ARM: dts: rtd1195: Add SB2 and SCPU Wrapper syscon nodes arm64: dts: realtek: rtd16xx: Add CRT syscon node ARM: dts: rtd1195: Add UART resets ARM: dts: rtd1195: Add reset nodes dt-bindings: reset: Add Realtek RTD1195 ARM: dts: rtd1195: Add CRT syscon node arm64: dts: realtek: rtd16xx: Introduce iso and misc syscon arm64: dts: realtek: rtd139x: Introduce CRT, iso and misc syscon arm64: dts: realtek: rtd129x: Introduce CRT, iso and misc syscon ARM: dts: rtd1195: Introduce iso and misc syscon arm64: dts: realtek: rtd1295: Add Xnano X5 dt-bindings: arm: realtek: Add Xnano X5 dt-bindings: vendor-prefixes: Add Xnano arm64: dts: realtek: rtd16xx: Add memory reservations arm64: dts: realtek: rtd16xx: Carve out boot ROM from memory arm64: dts: realtek: Add RTD1619 SoC and Realtek Mjolnir EVB ... Link: https://lore.kernel.org/r/20200510232158.18477-2-afaerber@suse.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
8c915019e3
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@ -14,6 +14,13 @@ properties:
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const: '/'
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compatible:
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oneOf:
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# RTD1195 SoC based boards
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- items:
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- enum:
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- mele,x1000 # MeLE X1000
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- realtek,horseradish # Realtek Horseradish EVB
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- const: realtek,rtd1195
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# RTD1293 SoC based boards
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- items:
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- enum:
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@ -25,6 +32,7 @@ properties:
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- enum:
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- mele,v9 # MeLE V9
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- probox2,ava # ProBox2 AVA
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- xnano,x5 # Xnano X5
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- zidoo,x9s # Zidoo X9S
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- const: realtek,rtd1295
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@ -33,4 +41,17 @@ properties:
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- enum:
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- synology,ds418 # Synology DiskStation DS418
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- const: realtek,rtd1296
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# RTD1395 SoC based boards
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- items:
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- enum:
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- bananapi,bpi-m4 # Banana Pi BPI-M4
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- realtek,lion-skin # Realtek Lion Skin EVB
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- const: realtek,rtd1395
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# RTD1619 SoC based boards
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- items:
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- enum:
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- realtek,mjolnir # Realtek Mjolnir EVB
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- const: realtek,rtd1619
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...
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@ -1125,6 +1125,8 @@ patternProperties:
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description: Shenzhen Xinpeng Technology Co., Ltd
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"^xlnx,.*":
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description: Xilinx
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"^xnano,.*":
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description: Xnano
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"^xunlong,.*":
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description: Shenzhen Xunlong Software CO.,Limited
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"^xylon,.*":
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@ -898,6 +898,9 @@ dtb-$(CONFIG_ARCH_QCOM) += \
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dtb-$(CONFIG_ARCH_RDA) += \
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rda8810pl-orangepi-2g-iot.dtb \
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rda8810pl-orangepi-i96.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += \
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rtd1195-horseradish.dtb \
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rtd1195-mele-x1000.dtb
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dtb-$(CONFIG_ARCH_REALVIEW) += \
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arm-realview-pb1176.dtb \
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arm-realview-pb11mp.dtb \
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@ -0,0 +1,32 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
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/*
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* Copyright (c) 2019 Andreas Färber
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*/
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/dts-v1/;
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#include "rtd1195.dtsi"
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/ {
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compatible = "realtek,horseradish", "realtek,rtd1195";
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model = "Realtek Horseradish EVB";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@a800 {
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device_type = "memory";
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reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */
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<0x18070000 0x00090000>, /* r-bus to NOR flash */
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<0x19100000 0x26f00000>; /* NOR flash to 1 GiB */
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};
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};
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&uart0 {
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status = "okay";
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};
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@ -0,0 +1,32 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
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/*
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* Copyright (c) 2017-2019 Andreas Färber
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*/
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/dts-v1/;
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#include "rtd1195.dtsi"
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/ {
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compatible = "mele,x1000", "realtek,rtd1195";
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model = "MeLE X1000";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@a800 {
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device_type = "memory";
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reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */
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<0x18070000 0x00090000>, /* r-bus to NOR flash */
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<0x19100000 0x26f00000>; /* NOR flash to 1 GiB */
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};
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};
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&uart0 {
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status = "okay";
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};
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@ -0,0 +1,217 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
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/*
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* Copyright (c) 2017-2019 Andreas Färber
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*/
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/memreserve/ 0x00000000 0x0000a800; /* boot code */
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/memreserve/ 0x0000a800 0x000f5800;
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/memreserve/ 0x17fff000 0x00001000;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/realtek,rtd1195.h>
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/ {
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compatible = "realtek,rtd1195";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clock-frequency = <1000000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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clock-frequency = <1000000000>;
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};
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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rpc_comm: rpc@b000 {
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reg = <0x0000b000 0x1000>;
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};
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audio@1b00000 {
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reg = <0x01b00000 0x400000>;
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};
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rpc_ringbuf: rpc@1ffe000 {
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reg = <0x01ffe000 0x4000>;
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};
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secure@10000000 {
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reg = <0x10000000 0x100000>;
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no-map;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <27000000>;
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};
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osc27M: osc {
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compatible = "fixed-clock";
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clock-frequency = <27000000>;
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#clock-cells = <0>;
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clock-output-names = "osc27M";
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0x0000a800>,
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<0x18000000 0x18000000 0x00070000>,
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<0x18100000 0x18100000 0x01000000>,
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<0x80000000 0x80000000 0x80000000>;
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rbus: bus@18000000 {
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compatible = "simple-bus";
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reg = <0x18000000 0x70000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x18000000 0x70000>;
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crt: syscon@0 {
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x1000>;
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reg-io-width = <4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x1000>;
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};
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iso: syscon@7000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x7000 0x1000>;
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reg-io-width = <4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x7000 0x1000>;
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};
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sb2: syscon@1a000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x1a000 0x1000>;
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reg-io-width = <4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1a000 0x1000>;
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};
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misc: syscon@1b000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x1b000 0x1000>;
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reg-io-width = <4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1b000 0x1000>;
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};
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scpu_wrapper: syscon@1d000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x1d000 0x1000>;
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reg-io-width = <4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1d000 0x1000>;
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};
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};
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gic: interrupt-controller@ff011000 {
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compatible = "arm,cortex-a7-gic";
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reg = <0xff011000 0x1000>,
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<0xff012000 0x2000>,
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<0xff014000 0x2000>,
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<0xff016000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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};
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&crt {
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reset1: reset-controller@0 {
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compatible = "snps,dw-low-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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};
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reset2: reset-controller@4 {
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compatible = "snps,dw-low-reset";
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reg = <0x4 0x4>;
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#reset-cells = <1>;
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};
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reset3: reset-controller@8 {
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compatible = "snps,dw-low-reset";
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reg = <0x8 0x4>;
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#reset-cells = <1>;
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};
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};
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&iso {
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iso_reset: reset-controller@88 {
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compatible = "snps,dw-low-reset";
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reg = <0x88 0x4>;
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#reset-cells = <1>;
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};
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wdt: watchdog@680 {
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compatible = "realtek,rtd1295-watchdog";
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reg = <0x680 0x100>;
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clocks = <&osc27M>;
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};
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uart0: serial@800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x800 0x400>;
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&iso_reset RTD1195_ISO_RSTN_UR0>;
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clock-frequency = <27000000>;
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status = "disabled";
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};
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};
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&misc {
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uart1: serial@200 {
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compatible = "snps,dw-apb-uart";
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reg = <0x200 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&reset2 RTD1195_RSTN_UR1>;
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clock-frequency = <27000000>;
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status = "disabled";
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};
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};
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@ -4,6 +4,12 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-xnano-x5.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb
|
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb
|
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb
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|
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
* Copyright (c) 2017-2019 Andreas Färber
|
||||
*/
|
||||
|
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/dts-v1/;
|
||||
|
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@ -11,9 +11,9 @@ / {
|
|||
compatible = "synology,ds418j", "realtek,rtd1293";
|
||||
model = "Synology DiskStation DS418j";
|
||||
|
||||
memory@0 {
|
||||
memory@1f000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>;
|
||||
reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
|
|
|
|||
|
|
@ -36,16 +36,20 @@ l2: l2-cache {
|
|||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
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(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
|
||||
&arm_pmu {
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
|
||||
&gic {
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
* Copyright (c) 2017-2019 Andreas Färber
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*/
|
||||
|
|
@ -12,9 +12,9 @@ / {
|
|||
compatible = "mele,v9", "realtek,rtd1295";
|
||||
model = "MeLE V9";
|
||||
|
||||
memory@0 {
|
||||
memory@1f000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000>;
|
||||
reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
* Copyright (c) 2017-2019 Andreas Färber
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*/
|
||||
|
|
@ -12,9 +12,9 @@ / {
|
|||
compatible = "probox2,ava", "realtek,rtd1295";
|
||||
model = "PROBOX2 AVA";
|
||||
|
||||
memory@0 {
|
||||
memory@1f000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000>;
|
||||
reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,30 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright (c) 2017-2019 Andreas Färber
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rtd1295.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "xnano,x5", "realtek,rtd1295";
|
||||
model = "Xnano X5";
|
||||
|
||||
memory@1f000 {
|
||||
device_type = "memory";
|
||||
reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB or 2 GiB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -11,9 +11,9 @@ / {
|
|||
compatible = "zidoo,x9s", "realtek,rtd1295";
|
||||
model = "Zidoo X9S";
|
||||
|
||||
memory@0 {
|
||||
memory@1f000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000>;
|
||||
reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Realtek RTD1295 SoC
|
||||
*
|
||||
* Copyright (c) 2016-2017 Andreas Färber
|
||||
* Copyright (c) 2016-2019 Andreas Färber
|
||||
*/
|
||||
|
||||
#include "rtd129x.dtsi"
|
||||
|
|
@ -47,27 +47,16 @@ l2: l2-cache {
|
|||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
tee@10100000 {
|
||||
reg = <0x10100000 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -11,9 +11,9 @@ / {
|
|||
compatible = "synology,ds418", "realtek,rtd1296";
|
||||
model = "Synology DiskStation DS418";
|
||||
|
||||
memory@0 {
|
||||
memory@1f000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000>;
|
||||
reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
|
|
|
|||
|
|
@ -50,13 +50,13 @@ l2: l2-cache {
|
|||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2,14 +2,12 @@
|
|||
/*
|
||||
* Realtek RTD1293/RTD1295/RTD1296 SoC
|
||||
*
|
||||
* Copyright (c) 2016-2017 Andreas Färber
|
||||
* Copyright (c) 2016-2019 Andreas Färber
|
||||
*/
|
||||
|
||||
/memreserve/ 0x0000000000000000 0x0000000000030000;
|
||||
/memreserve/ 0x000000000001f000 0x0000000000001000;
|
||||
/memreserve/ 0x0000000000030000 0x00000000000d0000;
|
||||
/memreserve/ 0x0000000000000000 0x000000000001f000;
|
||||
/memreserve/ 0x000000000001f000 0x00000000000e1000;
|
||||
/memreserve/ 0x0000000001b00000 0x00000000004be000;
|
||||
/memreserve/ 0x0000000001ffe000 0x0000000000004000;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/reset/realtek,rtd1295.h>
|
||||
|
|
@ -19,6 +17,25 @@ / {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
rpc_comm: rpc@1f000 {
|
||||
reg = <0x1f000 0x1000>;
|
||||
};
|
||||
|
||||
rpc_ringbuf: rpc@1ffe000 {
|
||||
reg = <0x1ffe000 0x4000>;
|
||||
};
|
||||
|
||||
tee: tee@10100000 {
|
||||
reg = <0x10100000 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
arm_pmu: arm-pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -35,73 +52,61 @@ soc {
|
|||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Exclude up to 2 GiB of RAM */
|
||||
ranges = <0x80000000 0x80000000 0x80000000>;
|
||||
ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
|
||||
/* Exclude up to 2 GiB of RAM */
|
||||
<0x80000000 0x80000000 0x80000000>;
|
||||
|
||||
reset1: reset-controller@98000000 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x98000000 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
rbus: bus@98000000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x98000000 0x200000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x98000000 0x200000>;
|
||||
|
||||
reset2: reset-controller@98000004 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x98000004 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
crt: syscon@0 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x0 0x1800>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x1800>;
|
||||
};
|
||||
|
||||
reset3: reset-controller@98000008 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x98000008 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
iso: syscon@7000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x7000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x7000 0x1000>;
|
||||
};
|
||||
|
||||
reset4: reset-controller@98000050 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x98000050 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
sb2: syscon@1a000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x1a000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1a000 0x1000>;
|
||||
};
|
||||
|
||||
iso_reset: reset-controller@98007088 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x98007088 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
misc: syscon@1b000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x1b000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1b000 0x1000>;
|
||||
};
|
||||
|
||||
wdt: watchdog@98007680 {
|
||||
compatible = "realtek,rtd1295-watchdog";
|
||||
reg = <0x98007680 0x100>;
|
||||
clocks = <&osc27M>;
|
||||
};
|
||||
|
||||
uart0: serial@98007800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x98007800 0x400>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <27000000>;
|
||||
resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@9801b200 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x9801b200 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <432000000>;
|
||||
resets = <&reset2 RTD1295_RSTN_UR1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@9801b400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x9801b400 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <432000000>;
|
||||
resets = <&reset2 RTD1295_RSTN_UR2>;
|
||||
status = "disabled";
|
||||
scpu_wrapper: syscon@1d000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x1d000 0x2000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1d000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@ff011000 {
|
||||
|
|
@ -116,3 +121,75 @@ gic: interrupt-controller@ff011000 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&crt {
|
||||
reset1: reset-controller@0 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
reset2: reset-controller@4 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x4 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
reset3: reset-controller@8 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x8 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
reset4: reset-controller@50 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x50 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&iso {
|
||||
iso_reset: reset-controller@88 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x88 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
wdt: watchdog@680 {
|
||||
compatible = "realtek,rtd1295-watchdog";
|
||||
reg = <0x680 0x100>;
|
||||
clocks = <&osc27M>;
|
||||
};
|
||||
|
||||
uart0: serial@800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x800 0x400>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <27000000>;
|
||||
resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&misc {
|
||||
uart1: serial@200 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x200 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <432000000>;
|
||||
resets = <&reset2 RTD1295_RSTN_UR1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x400 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <432000000>;
|
||||
resets = <&reset2 RTD1295_RSTN_UR2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,30 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright (c) 2019 Andreas Färber
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rtd1395.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "bananapi,bpi-m4", "realtek,rtd1395";
|
||||
model = "Banana Pi BPI-M4";
|
||||
|
||||
memory@2f000 {
|
||||
device_type = "memory";
|
||||
reg = <0x2f000 0x3ffd1000>; /* boot ROM to 1 GiB or 2 GiB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright (c) 2019 Andreas Färber
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rtd1395.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "realtek,lion-skin", "realtek,rtd1395";
|
||||
model = "Realtek Lion Skin EVB";
|
||||
|
||||
memory@2f000 {
|
||||
device_type = "memory";
|
||||
reg = <0x2f000 0x3ffd1000>; /* boot ROM to 1 GiB or 2 GiB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
/* debug console (J1) */
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* M.2 slot (CON1) */
|
||||
&uart1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
|
||||
/*
|
||||
* Realtek RTD1395 SoC
|
||||
*
|
||||
* Copyright (c) 2019 Andreas Färber
|
||||
*/
|
||||
|
||||
#include "rtd139x.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "realtek,rtd1395";
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x0>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x1>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x2>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x3>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
|
||||
&arm_pmu {
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
||||
};
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
|
||||
/*
|
||||
* Realtek RTD1395 SoC family
|
||||
*
|
||||
* Copyright (c) 2019 Andreas Färber
|
||||
*/
|
||||
|
||||
/memreserve/ 0x0000000000000000 0x000000000002f000;
|
||||
/memreserve/ 0x000000000002f000 0x00000000000d1000;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/reset/realtek,rtd1295.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
rpc_comm: rpc@2f000 {
|
||||
reg = <0x2f000 0x1000>;
|
||||
};
|
||||
|
||||
rpc_ringbuf: rpc@1ffe000 {
|
||||
reg = <0x1ffe000 0x4000>;
|
||||
};
|
||||
|
||||
tee: tee@10100000 {
|
||||
reg = <0x10100000 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
arm_pmu: arm-pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
osc27M: osc {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <27000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "osc27M";
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
|
||||
<0x98000000 0x98000000 0x68000000>;
|
||||
|
||||
rbus: bus@98000000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x98000000 0x200000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x98000000 0x200000>;
|
||||
|
||||
crt: syscon@0 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x0 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x1000>;
|
||||
};
|
||||
|
||||
iso: syscon@7000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x7000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x7000 0x1000>;
|
||||
};
|
||||
|
||||
sb2: syscon@1a000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x1a000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1a000 0x1000>;
|
||||
};
|
||||
|
||||
misc: syscon@1b000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x1b000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1b000 0x1000>;
|
||||
};
|
||||
|
||||
scpu_wrapper: syscon@1d000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x1d000 0x2000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1d000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@ff011000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0xff011000 0x1000>,
|
||||
<0xff012000 0x2000>,
|
||||
<0xff014000 0x2000>,
|
||||
<0xff016000 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&crt {
|
||||
reset1: reset-controller@0 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
reset2: reset-controller@4 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x4 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
reset3: reset-controller@8 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x8 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
reset4: reset-controller@50 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x50 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&iso {
|
||||
iso_reset: reset-controller@88 {
|
||||
compatible = "snps,dw-low-reset";
|
||||
reg = <0x88 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
wdt: watchdog@680 {
|
||||
compatible = "realtek,rtd1295-watchdog";
|
||||
reg = <0x680 0x100>;
|
||||
clocks = <&osc27M>;
|
||||
};
|
||||
|
||||
uart0: serial@800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x800 0x400>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <27000000>;
|
||||
resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&misc {
|
||||
uart1: serial@200 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x200 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <432000000>;
|
||||
resets = <&reset2 RTD1295_RSTN_UR1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x400 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <432000000>;
|
||||
resets = <&reset2 RTD1295_RSTN_UR2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright (c) 2019 Realtek Semiconductor Corp.
|
||||
* Copyright (c) 2019 Andreas Färber
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rtd1619.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "realtek,mjolnir", "realtek,rtd1619";
|
||||
model = "Realtek Mjolnir EVB";
|
||||
|
||||
memory@2e000 {
|
||||
device_type = "memory";
|
||||
reg = <0x2e000 0x7ffd2000>; /* boot ROM to 2 GiB */
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
};
|
||||
};
|
||||
|
||||
/* debug console (J1) */
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* M.2 slot (CON4) */
|
||||
&uart1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* GPIO connector (T1) */
|
||||
&uart2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
|
||||
/*
|
||||
* Realtek RTD1619 SoC
|
||||
*
|
||||
* Copyright (c) 2019 Realtek Semiconductor Corp.
|
||||
*/
|
||||
|
||||
#include "rtd16xx.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "realtek,rtd1619";
|
||||
};
|
||||
|
|
@ -0,0 +1,229 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
|
||||
/*
|
||||
* Realtek RTD16xx SoC family
|
||||
*
|
||||
* Copyright (c) 2019 Realtek Semiconductor Corp.
|
||||
* Copyright (c) 2019 Andreas Färber
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
rpc_comm: rpc@2f000 {
|
||||
reg = <0x2f000 0x1000>;
|
||||
};
|
||||
|
||||
rpc_ringbuf: rpc@1ffe000 {
|
||||
reg = <0x1ffe000 0x4000>;
|
||||
};
|
||||
|
||||
tee: tee@10100000 {
|
||||
reg = <0x10100000 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l3>;
|
||||
};
|
||||
|
||||
cpu2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x200>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l3>;
|
||||
};
|
||||
|
||||
cpu3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x300>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l3>;
|
||||
};
|
||||
|
||||
cpu4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x400>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l3>;
|
||||
};
|
||||
|
||||
cpu5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x500>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l3>;
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&l3>;
|
||||
|
||||
};
|
||||
|
||||
l3: l3-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
arm_pmu: pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
|
||||
<&cpu3>, <&cpu4>, <&cpu5>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
osc27M: osc {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <27000000>;
|
||||
clock-output-names = "osc27M";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x00000000 0x0002e000>, /* boot ROM */
|
||||
<0x98000000 0x98000000 0x68000000>;
|
||||
|
||||
rbus: bus@98000000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x98000000 0x200000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x98000000 0x200000>;
|
||||
|
||||
crt: syscon@0 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x0 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x1000>;
|
||||
};
|
||||
|
||||
iso: syscon@7000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x7000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x7000 0x1000>;
|
||||
};
|
||||
|
||||
sb2: syscon@1a000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x1a000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1a000 0x1000>;
|
||||
};
|
||||
|
||||
misc: syscon@1b000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x1b000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1b000 0x1000>;
|
||||
};
|
||||
|
||||
scpu_wrapper: syscon@1d000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x1d000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1d000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@ff100000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0xff100000 0x10000>,
|
||||
<0xff140000 0xc0000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iso {
|
||||
uart0: serial0@800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x800 0x400>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <27000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&misc {
|
||||
uart1: serial1@200 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x200 0x400>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <432000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial2@400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x400 0x400>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <432000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
|
||||
/*
|
||||
* Realtek RTD1195 reset controllers
|
||||
*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
*/
|
||||
#ifndef DT_BINDINGS_RESET_RTD1195_H
|
||||
#define DT_BINDINGS_RESET_RTD1195_H
|
||||
|
||||
/* soft reset 1 */
|
||||
#define RTD1195_RSTN_MISC 0
|
||||
#define RTD1195_RSTN_RNG 1
|
||||
#define RTD1195_RSTN_USB3_POW 2
|
||||
#define RTD1195_RSTN_GSPI 3
|
||||
#define RTD1195_RSTN_USB3_P0_MDIO 4
|
||||
#define RTD1195_RSTN_VE_H265 5
|
||||
#define RTD1195_RSTN_USB 6
|
||||
#define RTD1195_RSTN_USB_PHY0 8
|
||||
#define RTD1195_RSTN_USB_PHY1 9
|
||||
#define RTD1195_RSTN_HDMIRX 11
|
||||
#define RTD1195_RSTN_HDMI 12
|
||||
#define RTD1195_RSTN_ETN 14
|
||||
#define RTD1195_RSTN_AIO 15
|
||||
#define RTD1195_RSTN_GPU 16
|
||||
#define RTD1195_RSTN_VE_H264 17
|
||||
#define RTD1195_RSTN_VE_JPEG 18
|
||||
#define RTD1195_RSTN_TVE 19
|
||||
#define RTD1195_RSTN_VO 20
|
||||
#define RTD1195_RSTN_LVDS 21
|
||||
#define RTD1195_RSTN_SE 22
|
||||
#define RTD1195_RSTN_DCU 23
|
||||
#define RTD1195_RSTN_DC_PHY 24
|
||||
#define RTD1195_RSTN_CP 25
|
||||
#define RTD1195_RSTN_MD 26
|
||||
#define RTD1195_RSTN_TP 27
|
||||
#define RTD1195_RSTN_AE 28
|
||||
#define RTD1195_RSTN_NF 29
|
||||
#define RTD1195_RSTN_MIPI 30
|
||||
|
||||
/* soft reset 2 */
|
||||
#define RTD1195_RSTN_ACPU 0
|
||||
#define RTD1195_RSTN_VCPU 1
|
||||
#define RTD1195_RSTN_PCR 9
|
||||
#define RTD1195_RSTN_CR 10
|
||||
#define RTD1195_RSTN_EMMC 11
|
||||
#define RTD1195_RSTN_SDIO 12
|
||||
#define RTD1195_RSTN_I2C_5 18
|
||||
#define RTD1195_RSTN_RTC 20
|
||||
#define RTD1195_RSTN_I2C_4 23
|
||||
#define RTD1195_RSTN_I2C_3 24
|
||||
#define RTD1195_RSTN_I2C_2 25
|
||||
#define RTD1195_RSTN_I2C_1 26
|
||||
#define RTD1195_RSTN_UR1 28
|
||||
|
||||
/* soft reset 3 */
|
||||
#define RTD1195_RSTN_SB2 0
|
||||
|
||||
/* iso soft reset */
|
||||
#define RTD1195_ISO_RSTN_VFD 0
|
||||
#define RTD1195_ISO_RSTN_IR 1
|
||||
#define RTD1195_ISO_RSTN_CEC0 2
|
||||
#define RTD1195_ISO_RSTN_CEC1 3
|
||||
#define RTD1195_ISO_RSTN_DP 4
|
||||
#define RTD1195_ISO_RSTN_CBUSTX 5
|
||||
#define RTD1195_ISO_RSTN_CBUSRX 6
|
||||
#define RTD1195_ISO_RSTN_EFUSE 7
|
||||
#define RTD1195_ISO_RSTN_UR0 8
|
||||
#define RTD1195_ISO_RSTN_GMAC 9
|
||||
#define RTD1195_ISO_RSTN_GPHY 10
|
||||
#define RTD1195_ISO_RSTN_I2C_0 11
|
||||
#define RTD1195_ISO_RSTN_I2C_6 12
|
||||
#define RTD1195_ISO_RSTN_CBUS 13
|
||||
|
||||
#endif
|
||||
|
|
@ -75,6 +75,9 @@
|
|||
#define RTD1295_RSTN_CBUS_TX 30
|
||||
#define RTD1295_RSTN_SDS_PHY 31
|
||||
|
||||
/* soft reset 3 */
|
||||
#define RTD1295_RSTN_SB2 0
|
||||
|
||||
/* soft reset 4 */
|
||||
#define RTD1295_RSTN_DCPHY_CRT 0
|
||||
#define RTD1295_RSTN_DCPHY_ALERT_RX 1
|
||||
|
|
|
|||
Loading…
Reference in New Issue