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ARM: socfpga: dts: Add div-reg to the main_pll clocks
The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a pre-divider. Update socfpga.dtsi to represent those dividers for these clocks. Re-use the "div-reg" property that was used for the socfpga-gate-clock as this is the same thing. Also update the documentation. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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@ -21,8 +21,8 @@ Optional properties:
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- fixed-divider : If clocks have a fixed divider value, use this property.
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- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
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and the bit index.
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- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
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and width.
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- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
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the divider register, bit shift, and width.
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- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
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the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
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value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
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@ -148,7 +148,7 @@ mpuclk: mpuclk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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fixed-divider = <2>;
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div-reg = <0xe0 0 9>;
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reg = <0x48>;
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};
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@ -156,7 +156,7 @@ mainclk: mainclk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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fixed-divider = <4>;
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div-reg = <0xe4 0 9>;
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reg = <0x4C>;
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};
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@ -164,7 +164,7 @@ dbg_base_clk: dbg_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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fixed-divider = <4>;
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div-reg = <0xe8 0 9>;
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reg = <0x50>;
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};
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