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ARM: OMAP: PRM: Remove hardcoding of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 register offsets 

The register offsets of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 are hardcoded.
This makes it difficult to reuse the code for SoCs like AM437x that have
a single instance of IRQENABLE_MPU and IRQSTATUS_MPU registers.
Hence handling the case using offset of 4 to accommodate single set of IRQ*
registers generically.

Signed-off-by: Keerthy <j-keerthy@ti.com>
[paul@pwsan.com: fixed whitespace alignment problems reported by checkpatch.pl]
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Keerthy 2015-07-08 11:12:26 +05:30 committed by Paul Walmsley
parent 6e487001c5
commit 8d4be7d8bf
1 changed files with 20 additions and 18 deletions
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38
arch/arm/mach-omap2/prm44xx.c
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@ -217,11 +217,11 @@ static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
*/ */
static void omap44xx_prm_read_pending_irqs(unsigned long *events) static void omap44xx_prm_read_pending_irqs(unsigned long *events)
{ {
events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET, int i;
OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET, for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); events[i] = _read_pending_irq_reg(omap4_prcm_irq_setup.mask +
i * 4, omap4_prcm_irq_setup.ack + i * 4);
} }
/** /**
@ -251,17 +251,17 @@ static void omap44xx_prm_ocp_barrier(void)
*/ */
static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
{ {
saved_mask[0] = int i;
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, u16 reg;
OMAP4_PRM_IRQENABLE_MPU_OFFSET);
saved_mask[1] =
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++) {
OMAP4_PRM_IRQENABLE_MPU_OFFSET); reg = omap4_prcm_irq_setup.mask + i * 4;
omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); saved_mask[i] =
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
reg);
omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, reg);
}
/* OCP barrier */ /* OCP barrier */
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
@ -280,10 +280,12 @@ static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
*/ */
static void omap44xx_prm_restore_irqen(u32 *saved_mask) static void omap44xx_prm_restore_irqen(u32 *saved_mask)
{ {
omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST, int i;
OMAP4_PRM_IRQENABLE_MPU_OFFSET);
omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_OCP_SOCKET_INST, for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); omap4_prm_write_inst_reg(saved_mask[i],
OMAP4430_PRM_OCP_SOCKET_INST,
omap4_prcm_irq_setup.mask + i * 4);
} }
/** /**