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[PATCH] pcnet32: break in 2.6.18-rc1 identified
A change I made for 2.6.17 and another for 2.6.18 do not work on older pcnet32 chips which I do not have access to. If the chip is a 79C970 or 79C965, do not try and suspend or check the link status. I have tested with a 79C970A, 79C971, 79C972, 79C973, 79C975, 79C976, and 79C978. Signed-off-by: Don Fry <brazilnut@us.ibm.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -202,6 +202,8 @@ static int homepna[MAX_UNITS];
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#define CSR15 15
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#define CSR15 15
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#define PCNET32_MC_FILTER 8
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#define PCNET32_MC_FILTER 8
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#define PCNET32_79C970A 0x2621
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/* The PCNET32 Rx and Tx ring descriptors. */
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/* The PCNET32 Rx and Tx ring descriptors. */
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struct pcnet32_rx_head {
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struct pcnet32_rx_head {
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u32 base;
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u32 base;
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@ -289,6 +291,7 @@ struct pcnet32_private {
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/* each bit indicates an available PHY */
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/* each bit indicates an available PHY */
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u32 phymask;
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u32 phymask;
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unsigned short chip_version; /* which variant this is */
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};
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};
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static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
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static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
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@ -724,9 +727,11 @@ static u32 pcnet32_get_link(struct net_device *dev)
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spin_lock_irqsave(&lp->lock, flags);
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spin_lock_irqsave(&lp->lock, flags);
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if (lp->mii) {
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if (lp->mii) {
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r = mii_link_ok(&lp->mii_if);
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r = mii_link_ok(&lp->mii_if);
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} else {
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} else if (lp->chip_version >= PCNET32_79C970A) {
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ulong ioaddr = dev->base_addr; /* card base I/O address */
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ulong ioaddr = dev->base_addr; /* card base I/O address */
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r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
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r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
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} else { /* can not detect link on really old chips */
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r = 1;
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}
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}
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spin_unlock_irqrestore(&lp->lock, flags);
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spin_unlock_irqrestore(&lp->lock, flags);
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@ -1091,6 +1096,10 @@ static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
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ulong ioaddr = dev->base_addr;
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ulong ioaddr = dev->base_addr;
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int ticks;
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int ticks;
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/* really old chips have to be stopped. */
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if (lp->chip_version < PCNET32_79C970A)
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return 0;
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/* set SUSPEND (SPND) - CSR5 bit 0 */
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/* set SUSPEND (SPND) - CSR5 bit 0 */
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csr5 = a->read_csr(ioaddr, CSR5);
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csr5 = a->read_csr(ioaddr, CSR5);
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a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
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a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
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@ -1529,6 +1538,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
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lp->mii_if.reg_num_mask = 0x1f;
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lp->mii_if.reg_num_mask = 0x1f;
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lp->dxsuflo = dxsuflo;
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lp->dxsuflo = dxsuflo;
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lp->mii = mii;
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lp->mii = mii;
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lp->chip_version = chip_version;
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lp->msg_enable = pcnet32_debug;
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lp->msg_enable = pcnet32_debug;
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if ((cards_found >= MAX_UNITS)
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if ((cards_found >= MAX_UNITS)
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|| (options[cards_found] > sizeof(options_mapping)))
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|| (options[cards_found] > sizeof(options_mapping)))
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@ -1839,10 +1849,7 @@ static int pcnet32_open(struct net_device *dev)
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val |= 2;
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val |= 2;
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} else if (lp->options & PCNET32_PORT_ASEL) {
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} else if (lp->options & PCNET32_PORT_ASEL) {
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/* workaround of xSeries250, turn on for 79C975 only */
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/* workaround of xSeries250, turn on for 79C975 only */
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i = ((lp->a.read_csr(ioaddr, 88) |
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if (lp->chip_version == 0x2627)
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(lp->a.
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read_csr(ioaddr, 89) << 16)) >> 12) & 0xffff;
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if (i == 0x2627)
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val |= 3;
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val |= 3;
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}
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}
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lp->a.write_bcr(ioaddr, 9, val);
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lp->a.write_bcr(ioaddr, 9, val);
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@ -1986,9 +1993,11 @@ static int pcnet32_open(struct net_device *dev)
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netif_start_queue(dev);
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netif_start_queue(dev);
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/* Print the link status and start the watchdog */
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if (lp->chip_version >= PCNET32_79C970A) {
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pcnet32_check_media(dev, 1);
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/* Print the link status and start the watchdog */
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mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
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pcnet32_check_media(dev, 1);
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mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
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}
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i = 0;
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i = 0;
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while (i++ < 100)
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while (i++ < 100)
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