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cxgb4: Check alignment constraint for T6 

Update the check for setting  IPV4 filters and align filter_id
to multiple of 2, only for IPv6 filters in case of T6.

Signed-off-by: Arjun Vynipadath <arjun@chelsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ganesh Goudar 2017-12-29 12:48:04 +05:30 committed by David S. Miller
parent e3485df488
commit 8d93ac003f
1 changed files with 12 additions and 5 deletions
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17
drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c
View File

@ -1189,6 +1189,7 @@ int __cxgb4_set_filter(struct net_device *dev, int filter_id,
struct filter_ctx *ctx)
{
struct adapter *adapter = netdev2adap(dev);
unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
unsigned int max_fidx, fidx;
struct filter_entry *f;
u32 iconf;
@ -1225,12 +1226,18 @@ int __cxgb4_set_filter(struct net_device *dev, int filter_id,
* insertion.
*/
if (fs->type == 0) { /* IPv4 */
/* If our IPv4 filter isn't being written to a
* multiple of four filter index and there's an IPv6
* filter at the multiple of 4 base slot, then we
* prevent insertion.
/* For T6, If our IPv4 filter isn't being written to a
* multiple of two filter index and there's an IPv6
* filter at the multiple of 2 base slot, then we need
* to delete that IPv6 filter ...
* For adapters below T6, IPv6 filter occupies 4 entries.
* Hence we need to delete the filter in multiple of 4 slot.
*/
fidx = filter_id & ~0x3;
if (chip_ver < CHELSIO_T6)
fidx = filter_id & ~0x3;
else
fidx = filter_id & ~0x1;
if (fidx != filter_id &&
adapter->tids.ftid_tab[fidx].fs.type) {
f = &adapter->tids.ftid_tab[fidx];