mirror of https://gitee.com/openkylin/linux.git
iwlwifi: pcie: generalize and increase the size of scratchbuf
Currently the scratch buffer is set to 16 bytes and indicates the size of the bi-directional DMA. However, next HW generation will perform additional offloading, and will write the result in the key location of the TX command, so the size of the bi-directional consistent memory should grow accordingly - increase it to 40. Generalize the code to get rid of now irrelevant scratch references. Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
Sara Sharon
Luca Coelho
parent
b1753c62c7
commit
8de437c71e
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@ -232,15 +232,16 @@ struct iwl_queue {
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#define TFD_CMD_SLOTS 32
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/*
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* The FH will write back to the first TB only, so we need
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* to copy some data into the buffer regardless of whether
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* it should be mapped or not. This indicates how big the
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* first TB must be to include the scratch buffer. Since
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* the scratch is 4 bytes at offset 12, it's 16 now. If we
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* make it bigger then allocations will be bigger and copy
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* slower, so that's probably not useful.
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* The FH will write back to the first TB only, so we need to copy some data
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* into the buffer regardless of whether it should be mapped or not.
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* This indicates how big the first TB must be to include the scratch buffer
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* and the assigned PN.
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* Since PN location is 16 bytes at offset 24, it's 40 now.
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* If we make it bigger then allocations will be bigger and copy slower, so
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* that's probably not useful.
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*/
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#define IWL_HCMD_SCRATCHBUF_SIZE 16
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#define IWL_FIRST_TB_SIZE 40
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#define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64)
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struct iwl_pcie_txq_entry {
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struct iwl_device_cmd *cmd;
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@ -250,20 +251,18 @@ struct iwl_pcie_txq_entry {
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struct iwl_cmd_meta meta;
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};
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struct iwl_pcie_txq_scratch_buf {
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struct iwl_cmd_header hdr;
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u8 buf[8];
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__le32 scratch;
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struct iwl_pcie_first_tb_buf {
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u8 buf[IWL_FIRST_TB_SIZE_ALIGN];
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};
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/**
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* struct iwl_txq - Tx Queue for DMA
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* @q: generic Rx/Tx queue descriptor
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* @tfds: transmit frame descriptors (DMA memory)
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* @scratchbufs: start of command headers, including scratch buffers, for
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* @first_tb_bufs: start of command headers, including scratch buffers, for
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* the writeback -- this is DMA memory and an array holding one buffer
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* for each command on the queue
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* @scratchbufs_dma: DMA address for the scratchbufs start
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* @first_tb_dma: DMA address for the first_tb_bufs start
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* @entries: transmit entries (driver state)
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* @lock: queue lock
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* @stuck_timer: timer that fires if queue gets stuck
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@ -281,8 +280,8 @@ struct iwl_pcie_txq_scratch_buf {
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struct iwl_txq {
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struct iwl_queue q;
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struct iwl_tfd *tfds;
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struct iwl_pcie_txq_scratch_buf *scratchbufs;
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dma_addr_t scratchbufs_dma;
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struct iwl_pcie_first_tb_buf *first_tb_bufs;
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dma_addr_t first_tb_dma;
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struct iwl_pcie_txq_entry *entries;
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spinlock_t lock;
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unsigned long frozen_expiry_remainder;
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@ -298,10 +297,10 @@ struct iwl_txq {
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};
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static inline dma_addr_t
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iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx)
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iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx)
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{
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return txq->scratchbufs_dma +
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sizeof(struct iwl_pcie_txq_scratch_buf) * idx;
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return txq->first_tb_dma +
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sizeof(struct iwl_pcie_first_tb_buf) * idx;
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}
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struct iwl_tso_hdr_page {
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@ -393,7 +393,7 @@ static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
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return;
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}
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/* first TB is never freed - it's the scratchbuf data */
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/* first TB is never freed - it's the bidirectional DMA data */
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for (i = 1; i < num_tbs; i++) {
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if (meta->flags & BIT(i + CMD_TB_BITMAP_POS))
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@ -491,7 +491,7 @@ static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
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size_t scratchbuf_sz;
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size_t tb0_buf_sz;
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int i;
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if (WARN_ON(txq->entries || txq->tfds))
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@ -526,17 +526,14 @@ static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
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if (!txq->tfds)
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goto error;
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BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
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BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
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sizeof(struct iwl_cmd_header) +
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offsetof(struct iwl_tx_cmd, scratch));
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BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs));
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scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
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tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num;
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txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
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&txq->scratchbufs_dma,
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txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
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&txq->first_tb_dma,
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GFP_KERNEL);
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if (!txq->scratchbufs)
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if (!txq->first_tb_bufs)
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goto err_free_tfds;
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txq->q.id = txq_id;
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@ -708,8 +705,8 @@ static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
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txq->tfds = NULL;
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dma_free_coherent(dev,
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sizeof(*txq->scratchbufs) * txq->q.n_window,
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txq->scratchbufs, txq->scratchbufs_dma);
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sizeof(*txq->first_tb_bufs) * txq->q.n_window,
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txq->first_tb_bufs, txq->first_tb_dma);
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}
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kfree(txq->entries);
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@ -1422,7 +1419,7 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
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void *dup_buf = NULL;
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dma_addr_t phys_addr;
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int idx;
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u16 copy_size, cmd_size, scratch_size;
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u16 copy_size, cmd_size, tb0_size;
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bool had_nocopy = false;
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u8 group_id = iwl_cmd_groupid(cmd->id);
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int i, ret;
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@ -1453,9 +1450,9 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
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if (!cmd->len[i])
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continue;
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/* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
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if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
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int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
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/* need at least IWL_FIRST_TB_SIZE copied */
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if (copy_size < IWL_FIRST_TB_SIZE) {
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int copy = IWL_FIRST_TB_SIZE - copy_size;
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if (copy > cmdlen[i])
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copy = cmdlen[i];
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@ -1576,8 +1573,8 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
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}
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/*
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* Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
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* in total (for the scratchbuf handling), but copy up to what
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* Otherwise we need at least IWL_FIRST_TB_SIZE copied
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* in total (for bi-directional DMA), but copy up to what
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* we can fit into the payload for debug dump purposes.
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*/
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copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
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@ -1586,8 +1583,8 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
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cmd_pos += copy;
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/* However, treat copy_size the proper way, we need it below */
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if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
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copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
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if (copy_size < IWL_FIRST_TB_SIZE) {
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copy = IWL_FIRST_TB_SIZE - copy_size;
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if (copy > cmd->len[i])
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copy = cmd->len[i];
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@ -1602,18 +1599,18 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
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le16_to_cpu(out_cmd->hdr.sequence),
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cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
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/* start the TFD with the scratchbuf */
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scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
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memcpy(&txq->scratchbufs[idx], &out_cmd->hdr, scratch_size);
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/* start the TFD with the minimum copy bytes */
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tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
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memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
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iwl_pcie_txq_build_tfd(trans, txq,
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iwl_pcie_get_scratchbuf_dma(txq, idx),
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scratch_size, true);
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iwl_pcie_get_first_tb_dma(txq, idx),
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tb0_size, true);
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/* map first command fragment, if any remains */
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if (copy_size > scratch_size) {
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if (copy_size > tb0_size) {
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phys_addr = dma_map_single(trans->dev,
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((u8 *)&out_cmd->hdr) + scratch_size,
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copy_size - scratch_size,
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((u8 *)&out_cmd->hdr) + tb0_size,
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copy_size - tb0_size,
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DMA_TO_DEVICE);
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if (dma_mapping_error(trans->dev, phys_addr)) {
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iwl_pcie_tfd_unmap(trans, out_meta,
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@ -1623,7 +1620,7 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
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}
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iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
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copy_size - scratch_size, false);
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copy_size - tb0_size, false);
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}
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/* map the remaining (adjusted) nocopy/dup fragments */
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@ -1968,7 +1965,7 @@ static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
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trace_iwlwifi_dev_tx(trans->dev, skb,
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&txq->tfds[txq->q.write_ptr],
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sizeof(struct iwl_tfd),
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&dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
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&dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
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skb->data + hdr_len, tb2_len);
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trace_iwlwifi_dev_tx_data(trans->dev, skb,
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hdr_len, skb->len - hdr_len);
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@ -2044,7 +2041,7 @@ static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
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trace_iwlwifi_dev_tx(trans->dev, skb,
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&txq->tfds[txq->q.write_ptr],
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sizeof(struct iwl_tfd),
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&dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
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&dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
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NULL, 0);
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ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
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@ -2306,7 +2303,7 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
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INDEX_TO_SEQ(q->write_ptr)));
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tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
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tb0_phys = iwl_pcie_get_first_tb_dma(txq, q->write_ptr);
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scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
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offsetof(struct iwl_tx_cmd, scratch);
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@ -2324,7 +2321,7 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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* setup of the first TB)
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*/
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len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
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hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
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hdr_len - IWL_FIRST_TB_SIZE;
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/* do not align A-MSDU to dword as the subframe header aligns it */
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amsdu = ieee80211_is_data_qos(fc) &&
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(*ieee80211_get_qos_ctl(hdr) &
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@ -2338,17 +2335,17 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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tb1_len = len;
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}
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/* The first TB points to the scratchbuf data - min_copy bytes */
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memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
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IWL_HCMD_SCRATCHBUF_SIZE);
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/* The first TB points to bi-directional DMA data */
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memcpy(&txq->first_tb_bufs[q->write_ptr], &dev_cmd->hdr,
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IWL_FIRST_TB_SIZE);
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iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
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IWL_HCMD_SCRATCHBUF_SIZE, true);
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IWL_FIRST_TB_SIZE, true);
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/* there must be data left over for TB1 or this code must be changed */
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BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
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BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
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/* map the data for TB1 */
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tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
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tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
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tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
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if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
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goto out_err;
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