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arm64: perf: Report the PC value in REGS_ABI_32 mode
A 32-bit perf querying the registers of a compat task using REGS_ABI_32 will receive zeroes from w15, when it expects to find the PC. Return the PC value for register dwarf register 15 when returning register values for a compat task to perf. Cc: <stable@vger.kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Jiping Ma <jiping.ma2@windriver.com> Link: https://lore.kernel.org/r/1589165527-188401-1-git-send-email-jiping.ma2@windriver.com [will: Shuffled code and added a comment] Signed-off-by: Will Deacon <will@kernel.org>
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@ -15,15 +15,34 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)
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return 0;
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/*
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* Compat (i.e. 32 bit) mode:
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* - PC has been set in the pt_regs struct in kernel_entry,
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* - Handle SP and LR here.
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* Our handling of compat tasks (PERF_SAMPLE_REGS_ABI_32) is weird, but
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* we're stuck with it for ABI compatability reasons.
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*
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* For a 32-bit consumer inspecting a 32-bit task, then it will look at
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* the first 16 registers (see arch/arm/include/uapi/asm/perf_regs.h).
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* These correspond directly to a prefix of the registers saved in our
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* 'struct pt_regs', with the exception of the PC, so we copy that down
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* (x15 corresponds to SP_hyp in the architecture).
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*
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* So far, so good.
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*
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* The oddity arises when a 64-bit consumer looks at a 32-bit task and
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* asks for registers beyond PERF_REG_ARM_MAX. In this case, we return
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* SP_usr, LR_usr and PC in the positions where the AArch64 SP, LR and
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* PC registers would normally live. The initial idea was to allow a
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* 64-bit unwinder to unwind a 32-bit task and, although it's not clear
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* how well that works in practice, somebody might be relying on it.
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*
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* At the time we make a sample, we don't know whether the consumer is
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* 32-bit or 64-bit, so we have to cater for both possibilities.
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*/
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if (compat_user_mode(regs)) {
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if ((u32)idx == PERF_REG_ARM64_SP)
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return regs->compat_sp;
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if ((u32)idx == PERF_REG_ARM64_LR)
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return regs->compat_lr;
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if (idx == 15)
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return regs->pc;
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}
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if ((u32)idx == PERF_REG_ARM64_SP)
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