mirror of https://gitee.com/openkylin/linux.git
RDMA/mlx5: Delete unreachable handle_atomic code by simplifying SW completion
Handle atomic was left as unimplemented from 2013, remove the code till
this part will be developed.
Remove the dead code by simplifying SW completion logic which is supposed
to be the same for send and receive paths.
Fixes: e126ba97db ("mlx5: Add driver for Mellanox Connect-IB adapters")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Tested-by: Stephen Rothwell <sfr@canb.auug.org.au> # compile tested
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
Leon Romanovsky
Jason Gunthorpe
parent
4785860e04
commit
8e3b688301
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@ -330,67 +330,6 @@ static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
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dump_cqe(dev, cqe);
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}
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static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx)
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{
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/* TBD: waiting decision
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*/
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return 0;
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}
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static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx)
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{
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struct mlx5_wqe_data_seg *dpseg;
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void *addr;
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dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) +
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sizeof(struct mlx5_wqe_raddr_seg) +
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sizeof(struct mlx5_wqe_atomic_seg);
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addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr);
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return addr;
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}
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static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
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uint16_t idx)
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{
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void *addr;
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int byte_count;
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int i;
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if (!is_atomic_response(qp, idx))
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return;
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byte_count = be32_to_cpu(cqe64->byte_cnt);
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addr = mlx5_get_atomic_laddr(qp, idx);
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if (byte_count == 4) {
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*(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr));
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} else {
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for (i = 0; i < byte_count; i += 8) {
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*(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr));
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addr += 8;
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}
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}
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return;
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}
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static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
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u16 tail, u16 head)
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{
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u16 idx;
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do {
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idx = tail & (qp->sq.wqe_cnt - 1);
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handle_atomic(qp, cqe64, idx);
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if (idx == head)
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break;
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tail = qp->sq.w_list[idx].next;
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} while (1);
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tail = qp->sq.w_list[idx].next;
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qp->sq.last_poll = tail;
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}
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static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
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{
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mlx5_frag_buf_free(dev->mdev, &buf->frag_buf);
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@ -428,45 +367,15 @@ static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
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item->key = be32_to_cpu(cqe->mkey);
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}
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static void sw_send_comp(struct mlx5_ib_qp *qp, int num_entries,
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struct ib_wc *wc, int *npolled)
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{
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struct mlx5_ib_wq *wq;
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unsigned int cur;
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unsigned int idx;
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int np;
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int i;
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wq = &qp->sq;
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cur = wq->head - wq->tail;
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np = *npolled;
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if (cur == 0)
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return;
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for (i = 0; i < cur && np < num_entries; i++) {
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idx = wq->last_poll & (wq->wqe_cnt - 1);
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wc->wr_id = wq->wrid[idx];
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wc->status = IB_WC_WR_FLUSH_ERR;
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wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
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wq->tail++;
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np++;
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wc->qp = &qp->ibqp;
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wc++;
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wq->last_poll = wq->w_list[idx].next;
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}
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*npolled = np;
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}
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static void sw_recv_comp(struct mlx5_ib_qp *qp, int num_entries,
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struct ib_wc *wc, int *npolled)
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static void sw_comp(struct mlx5_ib_qp *qp, int num_entries, struct ib_wc *wc,
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int *npolled, int is_send)
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{
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struct mlx5_ib_wq *wq;
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unsigned int cur;
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int np;
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int i;
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wq = &qp->rq;
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wq = (is_send) ? &qp->sq : &qp->rq;
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cur = wq->head - wq->tail;
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np = *npolled;
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@ -493,13 +402,13 @@ static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
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*npolled = 0;
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/* Find uncompleted WQEs belonging to that cq and return mmics ones */
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list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
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sw_send_comp(qp, num_entries, wc + *npolled, npolled);
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sw_comp(qp, num_entries, wc + *npolled, npolled, true);
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if (*npolled >= num_entries)
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return;
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}
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list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
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sw_recv_comp(qp, num_entries, wc + *npolled, npolled);
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sw_comp(qp, num_entries, wc + *npolled, npolled, false);
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if (*npolled >= num_entries)
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return;
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}
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@ -567,7 +476,6 @@ static int mlx5_poll_one(struct mlx5_ib_cq *cq,
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wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
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idx = wqe_ctr & (wq->wqe_cnt - 1);
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handle_good_req(wc, cqe64, wq, idx);
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handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
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wc->wr_id = wq->wrid[idx];
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wq->tail = wq->wqe_head[idx] + 1;
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wc->status = IB_WC_SUCCESS;
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@ -275,7 +275,6 @@ struct mlx5_ib_wq {
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unsigned head;
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unsigned tail;
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u16 cur_post;
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u16 last_poll;
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void *cur_edge;
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};
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@ -1070,7 +1069,6 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
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const struct ib_send_wr **bad_wr);
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int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
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const struct ib_recv_wr **bad_wr);
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void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n);
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int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
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void *buffer, u32 length,
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struct mlx5_ib_qp_base *base);
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@ -3516,7 +3516,6 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
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qp->sq.cur_post = 0;
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if (qp->sq.wqe_cnt)
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qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
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qp->sq.last_poll = 0;
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qp->db.db[MLX5_RCV_DBR] = 0;
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qp->db.db[MLX5_SND_DBR] = 0;
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}
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