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drm/amd/display: Modified set bandwidth sequence. 

This change make sure bandwidth is set properly.
For increase bandwidth, set bandwidth before backend
and front end programming.
For decrease bandwidth, set bandwidth after.
To avoid smu hang when reboot and dpms due to 0 disp clk,
keep min disp clock as 100Mhz.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yongqiang Sun 2018-02-27 15:06:31 -05:00 committed by Alex Deucher
parent d03f3f6304
commit 8e437c7991
3 changed files with 38 additions and 12 deletions
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4
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -871,11 +871,11 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
context->streams[i]->timing.pix_clk_khz); context->streams[i]->timing.pix_clk_khz);
} }
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
/* pplib is notified if disp_num changed */ /* pplib is notified if disp_num changed */
dc->hwss.set_bandwidth(dc, context, true); dc->hwss.set_bandwidth(dc, context, true);
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
dc_release_state(dc->current_state); dc_release_state(dc->current_state);
dc->current_state = context; dc->current_state = context;

40
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -2088,6 +2088,11 @@ static void dcn10_apply_ctx_for_surface(
*/ */
} }
static inline bool should_set_clock(bool decrease_allowed, int calc_clk, int cur_clk)
{
return ((decrease_allowed && calc_clk < cur_clk) || calc_clk > cur_clk);
}
static void dcn10_set_bandwidth( static void dcn10_set_bandwidth(
struct dc *dc, struct dc *dc,
struct dc_state *context, struct dc_state *context,
@ -2105,29 +2110,40 @@ static void dcn10_set_bandwidth(
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
return; return;
if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz if (should_set_clock(
> dc->current_state->bw.dcn.cur_clk.dispclk_khz) { decrease_allowed,
context->bw.dcn.calc_clk.dispclk_khz,
dc->current_state->bw.dcn.cur_clk.dispclk_khz)) {
dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock->funcs->set_clock(
dc->res_pool->display_clock, dc->res_pool->display_clock,
context->bw.dcn.calc_clk.dispclk_khz); context->bw.dcn.calc_clk.dispclk_khz);
context->bw.dcn.cur_clk.dispclk_khz = context->bw.dcn.cur_clk.dispclk_khz =
context->bw.dcn.calc_clk.dispclk_khz; context->bw.dcn.calc_clk.dispclk_khz;
} }
if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
> dc->current_state->bw.dcn.cur_clk.dcfclk_khz) { if (should_set_clock(
decrease_allowed,
context->bw.dcn.calc_clk.dcfclk_khz,
dc->current_state->bw.dcn.cur_clk.dcfclk_khz)) {
context->bw.dcn.cur_clk.dcfclk_khz = context->bw.dcn.cur_clk.dcfclk_khz =
context->bw.dcn.calc_clk.dcfclk_khz; context->bw.dcn.calc_clk.dcfclk_khz;
smu_req.hard_min_dcefclk_khz = smu_req.hard_min_dcefclk_khz =
context->bw.dcn.calc_clk.dcfclk_khz; context->bw.dcn.calc_clk.dcfclk_khz;
} }
if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
> dc->current_state->bw.dcn.cur_clk.fclk_khz) { if (should_set_clock(
decrease_allowed,
context->bw.dcn.calc_clk.fclk_khz,
dc->current_state->bw.dcn.cur_clk.fclk_khz)) {
context->bw.dcn.cur_clk.fclk_khz = context->bw.dcn.cur_clk.fclk_khz =
context->bw.dcn.calc_clk.fclk_khz; context->bw.dcn.calc_clk.fclk_khz;
smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz; smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
} }
if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
> dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) { if (should_set_clock(
decrease_allowed,
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz)) {
context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
} }
@ -2140,12 +2156,16 @@ static void dcn10_set_bandwidth(
*smu_req_cur = smu_req; *smu_req_cur = smu_req;
/* Decrease in freq is increase in period so opposite comparison for dram_ccm */ /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us if ((decrease_allowed && context->bw.dcn.calc_clk.dram_ccm_us
> dc->current_state->bw.dcn.cur_clk.dram_ccm_us) ||
context->bw.dcn.calc_clk.dram_ccm_us
< dc->current_state->bw.dcn.cur_clk.dram_ccm_us) { < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) {
context->bw.dcn.cur_clk.dram_ccm_us = context->bw.dcn.cur_clk.dram_ccm_us =
context->bw.dcn.calc_clk.dram_ccm_us; context->bw.dcn.calc_clk.dram_ccm_us;
} }
if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us if ((decrease_allowed && context->bw.dcn.calc_clk.min_active_dram_ccm_us
> dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) ||
context->bw.dcn.calc_clk.min_active_dram_ccm_us
< dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) { < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) {
context->bw.dcn.cur_clk.min_active_dram_ccm_us = context->bw.dcn.cur_clk.min_active_dram_ccm_us =
context->bw.dcn.calc_clk.min_active_dram_ccm_us; context->bw.dcn.calc_clk.min_active_dram_ccm_us;

6
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View File

@ -440,6 +440,12 @@ static const struct dc_debug debug_defaults_drv = {
.timing_trace = false, .timing_trace = false,
.clock_trace = true, .clock_trace = true,
/* raven smu dones't allow 0 disp clk,
* smu min disp clk limit is 50Mhz
* keep min disp clk 100Mhz avoid smu hang
*/
.min_disp_clk_khz = 100000,
.disable_pplib_clock_request = true, .disable_pplib_clock_request = true,
.disable_pplib_wm_range = false, .disable_pplib_wm_range = false,
.pplib_wm_report_mode = WM_REPORT_DEFAULT, .pplib_wm_report_mode = WM_REPORT_DEFAULT,