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drm/i915/icl: Use helper functions to classify the ports 

Use intel_port_is_tc and intel_port_is_combophy
functions to replace the individual port checks
from port C to F and port A to B respectively.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181003072203.12848-5-mahesh1.kumar@intel.com
This commit is contained in:
Vandita Kulkarni 2018-10-03 12:51:59 +05:30 committed by Rodrigo Vivi
parent cb6caf7e39
commit 8ea59e6739
2 changed files with 8 additions and 21 deletions
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15
drivers/gpu/drm/i915/intel_display.c
View File

@ -9269,24 +9269,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
u32 temp; u32 temp;
/* TODO: TBT pll not implemented. */ /* TODO: TBT pll not implemented. */
switch (port) { if (intel_port_is_combophy(dev_priv, port)) {
case PORT_A:
case PORT_B:
temp = I915_READ(DPCLKA_CFGCR0_ICL) & temp = I915_READ(DPCLKA_CFGCR0_ICL) &
DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1)) if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
return; return;
break; } else if (intel_port_is_tc(dev_priv, port)) {
case PORT_C:
case PORT_D:
case PORT_E:
case PORT_F:
id = icl_port_to_mg_pll_id(port); id = icl_port_to_mg_pll_id(port);
break; } else {
default: WARN(1, "Invalid port %x\n", port);
MISSING_CASE(port);
return; return;
} }

14
drivers/gpu/drm/i915/intel_dpll_mgr.c
View File

@ -2867,6 +2867,7 @@ static struct intel_shared_dpll *
icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder) struct intel_encoder *encoder)
{ {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *intel_dig_port = struct intel_digital_port *intel_dig_port =
enc_to_dig_port(&encoder->base); enc_to_dig_port(&encoder->base);
struct intel_shared_dpll *pll; struct intel_shared_dpll *pll;
@ -2876,18 +2877,12 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
int clock = crtc_state->port_clock; int clock = crtc_state->port_clock;
bool ret; bool ret;
switch (port) { if (intel_port_is_combophy(dev_priv, port)) {
case PORT_A:
case PORT_B:
min = DPLL_ID_ICL_DPLL0; min = DPLL_ID_ICL_DPLL0;
max = DPLL_ID_ICL_DPLL1; max = DPLL_ID_ICL_DPLL1;
ret = icl_calc_dpll_state(crtc_state, encoder, clock, ret = icl_calc_dpll_state(crtc_state, encoder, clock,
&pll_state); &pll_state);
break; } else if (intel_port_is_tc(dev_priv, port)) {
case PORT_C:
case PORT_D:
case PORT_E:
case PORT_F:
if (intel_dig_port->tc_type == TC_PORT_TBT) { if (intel_dig_port->tc_type == TC_PORT_TBT) {
min = DPLL_ID_ICL_TBTPLL; min = DPLL_ID_ICL_TBTPLL;
max = min; max = min;
@ -2899,8 +2894,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
ret = icl_calc_mg_pll_state(crtc_state, encoder, clock, ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
&pll_state); &pll_state);
} }
break; } else {
default:
MISSING_CASE(port); MISSING_CASE(port);
return NULL; return NULL;
} }