mirror of https://gitee.com/openkylin/linux.git
pasemi: DMA engine management library
pasemi: DMA engine management library Introduce a DMA management library to manage the various DMA resources on the PA Semi SoCs. Since several drivers need to allocate these shared resources, provide some abstractions as well as allocation/free functions for channels, etc. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Olof Johansson
David S. Miller
parent
40afa53158
commit
8ee9d85779
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@ -1,4 +1,4 @@
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obj-y += setup.o pci.o time.o idle.o powersave.o iommu.o
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obj-y += setup.o pci.o time.o idle.o powersave.o iommu.o dma_lib.o
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obj-$(CONFIG_PPC_PASEMI_MDIO) += gpio_mdio.o
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obj-$(CONFIG_ELECTRA_IDE) += electra_ide.o
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obj-$(CONFIG_PPC_PASEMI_CPUFREQ) += cpufreq.o
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@ -0,0 +1,487 @@
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/*
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* Copyright (C) 2006-2007 PA Semi, Inc
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*
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* Common functions for DMA access on PA Semi PWRficient
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/of.h>
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#include <asm/pasemi_dma.h>
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#define MAX_TXCH 64
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#define MAX_RXCH 64
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static struct pasdma_status *dma_status;
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static void __iomem *iob_regs;
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static void __iomem *mac_regs[6];
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static void __iomem *dma_regs;
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static int base_hw_irq;
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static int num_txch, num_rxch;
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static struct pci_dev *dma_pdev;
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/* Bitmaps to handle allocation of channels */
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static DECLARE_BITMAP(txch_free, MAX_TXCH);
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static DECLARE_BITMAP(rxch_free, MAX_RXCH);
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/* pasemi_read_iob_reg - read IOB register
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* @reg: Register to read (offset into PCI CFG space)
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*/
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unsigned int pasemi_read_iob_reg(unsigned int reg)
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{
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return in_le32(iob_regs+reg);
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}
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EXPORT_SYMBOL(pasemi_read_iob_reg);
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/* pasemi_write_iob_reg - write IOB register
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* @reg: Register to write to (offset into PCI CFG space)
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* @val: Value to write
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*/
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void pasemi_write_iob_reg(unsigned int reg, unsigned int val)
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{
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out_le32(iob_regs+reg, val);
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}
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EXPORT_SYMBOL(pasemi_write_iob_reg);
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/* pasemi_read_mac_reg - read MAC register
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* @intf: MAC interface
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* @reg: Register to read (offset into PCI CFG space)
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*/
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unsigned int pasemi_read_mac_reg(int intf, unsigned int reg)
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{
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return in_le32(mac_regs[intf]+reg);
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}
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EXPORT_SYMBOL(pasemi_read_mac_reg);
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/* pasemi_write_mac_reg - write MAC register
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* @intf: MAC interface
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* @reg: Register to write to (offset into PCI CFG space)
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* @val: Value to write
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*/
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void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val)
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{
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out_le32(mac_regs[intf]+reg, val);
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}
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EXPORT_SYMBOL(pasemi_write_mac_reg);
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/* pasemi_read_dma_reg - read DMA register
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* @reg: Register to read (offset into PCI CFG space)
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*/
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unsigned int pasemi_read_dma_reg(unsigned int reg)
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{
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return in_le32(dma_regs+reg);
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}
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EXPORT_SYMBOL(pasemi_read_dma_reg);
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/* pasemi_write_dma_reg - write DMA register
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* @reg: Register to write to (offset into PCI CFG space)
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* @val: Value to write
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*/
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void pasemi_write_dma_reg(unsigned int reg, unsigned int val)
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{
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out_le32(dma_regs+reg, val);
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}
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EXPORT_SYMBOL(pasemi_write_dma_reg);
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static int pasemi_alloc_tx_chan(enum pasemi_dmachan_type type)
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{
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int bit;
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int start, limit;
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switch (type & (TXCHAN_EVT0|TXCHAN_EVT1)) {
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case TXCHAN_EVT0:
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start = 0;
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limit = 10;
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break;
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case TXCHAN_EVT1:
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start = 10;
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limit = MAX_TXCH;
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break;
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default:
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start = 0;
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limit = MAX_TXCH;
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break;
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}
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retry:
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bit = find_next_bit(txch_free, MAX_TXCH, start);
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if (bit >= limit)
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return -ENOSPC;
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if (!test_and_clear_bit(bit, txch_free))
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goto retry;
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return bit;
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}
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static void pasemi_free_tx_chan(int chan)
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{
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BUG_ON(test_bit(chan, txch_free));
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set_bit(chan, txch_free);
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}
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static int pasemi_alloc_rx_chan(void)
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{
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int bit;
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retry:
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bit = find_first_bit(rxch_free, MAX_RXCH);
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if (bit >= MAX_TXCH)
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return -ENOSPC;
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if (!test_and_clear_bit(bit, rxch_free))
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goto retry;
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return bit;
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}
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static void pasemi_free_rx_chan(int chan)
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{
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BUG_ON(test_bit(chan, rxch_free));
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set_bit(chan, rxch_free);
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}
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/* pasemi_dma_alloc_chan - Allocate a DMA channel
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* @type: Type of channel to allocate
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* @total_size: Total size of structure to allocate (to allow for more
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* room behind the structure to be used by the client)
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* @offset: Offset in bytes from start of the total structure to the beginning
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* of struct pasemi_dmachan. Needed when struct pasemi_dmachan is
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* not the first member of the client structure.
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*
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* pasemi_dma_alloc_chan allocates a DMA channel for use by a client. The
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* type argument specifies whether it's a RX or TX channel, and in the case
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* of TX channels which group it needs to belong to (if any).
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*
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* Returns a pointer to the total structure allocated on success, NULL
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* on failure.
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*/
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void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type,
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int total_size, int offset)
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{
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void *buf;
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struct pasemi_dmachan *chan;
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int chno;
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BUG_ON(total_size < sizeof(struct pasemi_dmachan));
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buf = kzalloc(total_size, GFP_KERNEL);
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if (!buf)
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return NULL;
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chan = buf + offset;
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chan->priv = buf;
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switch (type & (TXCHAN|RXCHAN)) {
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case RXCHAN:
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chno = pasemi_alloc_rx_chan();
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chan->chno = chno;
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chan->irq = irq_create_mapping(NULL,
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base_hw_irq + num_txch + chno);
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chan->status = &dma_status->rx_sta[chno];
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break;
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case TXCHAN:
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chno = pasemi_alloc_tx_chan(type);
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chan->chno = chno;
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chan->irq = irq_create_mapping(NULL, base_hw_irq + chno);
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chan->status = &dma_status->tx_sta[chno];
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break;
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}
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chan->chan_type = type;
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return chan;
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}
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EXPORT_SYMBOL(pasemi_dma_alloc_chan);
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/* pasemi_dma_free_chan - Free a previously allocated channel
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* @chan: Channel to free
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*
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* Frees a previously allocated channel. It will also deallocate any
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* descriptor ring associated with the channel, if allocated.
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*/
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void pasemi_dma_free_chan(struct pasemi_dmachan *chan)
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{
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if (chan->ring_virt)
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pasemi_dma_free_ring(chan);
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switch (chan->chan_type & (RXCHAN|TXCHAN)) {
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case RXCHAN:
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pasemi_free_rx_chan(chan->chno);
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break;
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case TXCHAN:
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pasemi_free_tx_chan(chan->chno);
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break;
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}
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kfree(chan->priv);
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}
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EXPORT_SYMBOL(pasemi_dma_free_chan);
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/* pasemi_dma_alloc_ring - Allocate descriptor ring for a channel
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* @chan: Channel for which to allocate
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* @ring_size: Ring size in 64-bit (8-byte) words
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*
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* Allocate a descriptor ring for a channel. Returns 0 on success, errno
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* on failure. The passed in struct pasemi_dmachan is updated with the
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* virtual and DMA addresses of the ring.
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*/
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int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size)
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{
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BUG_ON(chan->ring_virt);
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chan->ring_size = ring_size;
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chan->ring_virt = dma_alloc_coherent(&dma_pdev->dev,
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ring_size * sizeof(u64),
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&chan->ring_dma, GFP_KERNEL);
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if (!chan->ring_virt)
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return -ENOMEM;
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memset(chan->ring_virt, 0, ring_size * sizeof(u64));
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return 0;
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}
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EXPORT_SYMBOL(pasemi_dma_alloc_ring);
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/* pasemi_dma_free_ring - Free an allocated descriptor ring for a channel
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* @chan: Channel for which to free the descriptor ring
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*
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* Frees a previously allocated descriptor ring for a channel.
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*/
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void pasemi_dma_free_ring(struct pasemi_dmachan *chan)
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{
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BUG_ON(!chan->ring_virt);
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dma_free_coherent(&dma_pdev->dev, chan->ring_size * sizeof(u64),
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chan->ring_virt, chan->ring_dma);
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chan->ring_virt = NULL;
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chan->ring_size = 0;
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chan->ring_dma = 0;
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}
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EXPORT_SYMBOL(pasemi_dma_free_ring);
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/* pasemi_dma_start_chan - Start a DMA channel
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* @chan: Channel to start
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* @cmdsta: Additional CCMDSTA/TCMDSTA bits to write
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*
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* Enables (starts) a DMA channel with optional additional arguments.
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*/
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void pasemi_dma_start_chan(const struct pasemi_dmachan *chan, const u32 cmdsta)
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{
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if (chan->chan_type == RXCHAN)
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pasemi_write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno),
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cmdsta | PAS_DMA_RXCHAN_CCMDSTA_EN);
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else
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pasemi_write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno),
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cmdsta | PAS_DMA_TXCHAN_TCMDSTA_EN);
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}
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EXPORT_SYMBOL(pasemi_dma_start_chan);
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/* pasemi_dma_stop_chan - Stop a DMA channel
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* @chan: Channel to stop
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*
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* Stops (disables) a DMA channel. This is done by setting the ST bit in the
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* CMDSTA register and waiting on the ACT (active) bit to clear, then
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* finally disabling the whole channel.
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*
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* This function will only try for a short while for the channel to stop, if
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* it doesn't it will return failure.
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*
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* Returns 1 on success, 0 on failure.
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*/
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#define MAX_RETRIES 5000
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int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan)
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{
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int reg, retries;
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u32 sta;
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if (chan->chan_type == RXCHAN) {
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reg = PAS_DMA_RXCHAN_CCMDSTA(chan->chno);
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pasemi_write_dma_reg(reg, PAS_DMA_RXCHAN_CCMDSTA_ST);
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for (retries = 0; retries < MAX_RETRIES; retries++) {
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sta = pasemi_read_dma_reg(reg);
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if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) {
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pasemi_write_dma_reg(reg, 0);
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return 1;
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}
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cond_resched();
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}
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} else {
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reg = PAS_DMA_TXCHAN_TCMDSTA(chan->chno);
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pasemi_write_dma_reg(reg, PAS_DMA_TXCHAN_TCMDSTA_ST);
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for (retries = 0; retries < MAX_RETRIES; retries++) {
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sta = pasemi_read_dma_reg(reg);
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if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) {
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pasemi_write_dma_reg(reg, 0);
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return 1;
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}
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cond_resched();
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}
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}
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return 0;
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}
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EXPORT_SYMBOL(pasemi_dma_stop_chan);
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/* pasemi_dma_alloc_buf - Allocate a buffer to use for DMA
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* @chan: Channel to allocate for
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* @size: Size of buffer in bytes
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* @handle: DMA handle
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*
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* Allocate a buffer to be used by the DMA engine for read/write,
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* similar to dma_alloc_coherent().
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*
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* Returns the virtual address of the buffer, or NULL in case of failure.
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*/
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void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
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dma_addr_t *handle)
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{
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return dma_alloc_coherent(&dma_pdev->dev, size, handle, GFP_KERNEL);
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}
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EXPORT_SYMBOL(pasemi_dma_alloc_buf);
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/* pasemi_dma_free_buf - Free a buffer used for DMA
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* @chan: Channel the buffer was allocated for
|
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* @size: Size of buffer in bytes
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* @handle: DMA handle
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*
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* Frees a previously allocated buffer.
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*/
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void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
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dma_addr_t *handle)
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{
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dma_free_coherent(&dma_pdev->dev, size, handle, GFP_KERNEL);
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}
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EXPORT_SYMBOL(pasemi_dma_free_buf);
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static void *map_onedev(struct pci_dev *p, int index)
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{
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struct device_node *dn;
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void __iomem *ret;
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dn = pci_device_to_OF_node(p);
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if (!dn)
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goto fallback;
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ret = of_iomap(dn, index);
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if (!ret)
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goto fallback;
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return ret;
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fallback:
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/* This is hardcoded and ugly, but we have some firmware versions
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* that don't provide the register space in the device tree. Luckily
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* they are at well-known locations so we can just do the math here.
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*/
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return ioremap(0xe0000000 + (p->devfn << 12), 0x2000);
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}
|
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/* pasemi_dma_init - Initialize the PA Semi DMA library
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*
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* This function initializes the DMA library. It must be called before
|
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* any other function in the library.
|
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*
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* Returns 0 on success, errno on failure.
|
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*/
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int pasemi_dma_init(void)
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{
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static spinlock_t init_lock = SPIN_LOCK_UNLOCKED;
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struct pci_dev *iob_pdev;
|
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struct pci_dev *pdev;
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struct resource res;
|
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struct device_node *dn;
|
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int i, intf, err = 0;
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u32 tmp;
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if (!machine_is(pasemi))
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return -ENODEV;
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spin_lock(&init_lock);
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/* Make sure we haven't already initialized */
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if (dma_pdev)
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goto out;
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iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
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if (!iob_pdev) {
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BUG();
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printk(KERN_WARNING "Can't find I/O Bridge\n");
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err = -ENODEV;
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goto out;
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}
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iob_regs = map_onedev(iob_pdev, 0);
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dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
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if (!dma_pdev) {
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BUG();
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printk(KERN_WARNING "Can't find DMA controller\n");
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err = -ENODEV;
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goto out;
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}
|
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dma_regs = map_onedev(dma_pdev, 0);
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base_hw_irq = virq_to_hw(dma_pdev->irq);
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pci_read_config_dword(dma_pdev, PAS_DMA_CAP_TXCH, &tmp);
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num_txch = (tmp & PAS_DMA_CAP_TXCH_TCHN_M) >> PAS_DMA_CAP_TXCH_TCHN_S;
|
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|
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pci_read_config_dword(dma_pdev, PAS_DMA_CAP_RXCH, &tmp);
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num_rxch = (tmp & PAS_DMA_CAP_RXCH_RCHN_M) >> PAS_DMA_CAP_RXCH_RCHN_S;
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|
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intf = 0;
|
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for (pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa006, NULL);
|
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pdev;
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pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa006, pdev))
|
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mac_regs[intf++] = map_onedev(pdev, 0);
|
||||
|
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pci_dev_put(pdev);
|
||||
|
||||
for (pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa005, NULL);
|
||||
pdev;
|
||||
pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa005, pdev))
|
||||
mac_regs[intf++] = map_onedev(pdev, 0);
|
||||
|
||||
pci_dev_put(pdev);
|
||||
|
||||
dn = pci_device_to_OF_node(iob_pdev);
|
||||
if (dn)
|
||||
err = of_address_to_resource(dn, 1, &res);
|
||||
if (!dn || err) {
|
||||
/* Fallback for old firmware */
|
||||
res.start = 0xfd800000;
|
||||
res.end = res.start + 0x1000;
|
||||
}
|
||||
dma_status = __ioremap(res.start, res.end-res.start, 0);
|
||||
pci_dev_put(iob_pdev);
|
||||
|
||||
for (i = 0; i < MAX_TXCH; i++)
|
||||
__set_bit(i, txch_free);
|
||||
|
||||
for (i = 0; i < MAX_RXCH; i++)
|
||||
__set_bit(i, rxch_free);
|
||||
|
||||
printk(KERN_INFO "PA Semi PWRficient DMA library initialized "
|
||||
"(%d tx, %d rx channels)\n", num_txch, num_rxch);
|
||||
|
||||
out:
|
||||
spin_unlock(&init_lock);
|
||||
return err;
|
||||
}
|
||||
|
|
@ -9,6 +9,7 @@ extern void __devinit pas_pci_dma_dev_setup(struct pci_dev *dev);
|
|||
extern void __iomem *pasemi_pci_getcfgaddr(struct pci_dev *dev, int offset);
|
||||
|
||||
extern void __init alloc_iobmap_l2(void);
|
||||
extern void __init pasemi_map_registers(void);
|
||||
|
||||
/* Power savings modes, implemented in asm */
|
||||
extern void idle_spin(void);
|
||||
|
|
|
|||
|
|
@ -33,11 +33,27 @@ struct pasdma_status {
|
|||
* device. Use the normal PCI config access functions for them.
|
||||
*/
|
||||
enum {
|
||||
PAS_DMA_CAP_TXCH = 0x44, /* Transmit Channel Info */
|
||||
PAS_DMA_CAP_RXCH = 0x48, /* Transmit Channel Info */
|
||||
PAS_DMA_CAP_IFI = 0x4c, /* Interface Info */
|
||||
PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
|
||||
PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
|
||||
PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
|
||||
PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
|
||||
};
|
||||
|
||||
|
||||
#define PAS_DMA_CAP_TXCH_TCHN_M 0x00ff0000 /* # of TX channels */
|
||||
#define PAS_DMA_CAP_TXCH_TCHN_S 16
|
||||
|
||||
#define PAS_DMA_CAP_RXCH_RCHN_M 0x00ff0000 /* # of RX channels */
|
||||
#define PAS_DMA_CAP_RXCH_RCHN_S 16
|
||||
|
||||
#define PAS_DMA_CAP_IFI_IOFF_M 0xff000000 /* Cfg reg for intf pointers */
|
||||
#define PAS_DMA_CAP_IFI_IOFF_S 24
|
||||
#define PAS_DMA_CAP_IFI_NIN_M 0x00ff0000 /* # of interfaces */
|
||||
#define PAS_DMA_CAP_IFI_NIN_S 16
|
||||
|
||||
#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */
|
||||
#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */
|
||||
#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */
|
||||
|
|
@ -388,4 +404,64 @@ enum {
|
|||
CTRL_CMD_REG_M)
|
||||
|
||||
|
||||
|
||||
/* Prototypes for the shared DMA functions in the platform code. */
|
||||
|
||||
/* DMA TX Channel type. Right now only limitations used are event types 0/1,
|
||||
* for event-triggered DMA transactions.
|
||||
*/
|
||||
|
||||
enum pasemi_dmachan_type {
|
||||
RXCHAN = 0, /* Any RX chan */
|
||||
TXCHAN = 1, /* Any TX chan */
|
||||
TXCHAN_EVT0 = 0x1001, /* TX chan in event class 0 (chan 0-9) */
|
||||
TXCHAN_EVT1 = 0x2001, /* TX chan in event class 1 (chan 10-19) */
|
||||
};
|
||||
|
||||
struct pasemi_dmachan {
|
||||
int chno; /* Channel number */
|
||||
enum pasemi_dmachan_type chan_type; /* TX / RX */
|
||||
u64 *status; /* Ptr to cacheable status */
|
||||
int irq; /* IRQ used by channel */
|
||||
unsigned int ring_size; /* size of allocated ring */
|
||||
dma_addr_t ring_dma; /* DMA address for ring */
|
||||
u64 *ring_virt; /* Virt address for ring */
|
||||
void *priv; /* Ptr to start of client struct */
|
||||
};
|
||||
|
||||
/* Read/write the different registers in the I/O Bridge, Ethernet
|
||||
* and DMA Controller
|
||||
*/
|
||||
extern unsigned int pasemi_read_iob_reg(unsigned int reg);
|
||||
extern void pasemi_write_iob_reg(unsigned int reg, unsigned int val);
|
||||
|
||||
extern unsigned int pasemi_read_mac_reg(int intf, unsigned int reg);
|
||||
extern void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val);
|
||||
|
||||
extern unsigned int pasemi_read_dma_reg(unsigned int reg);
|
||||
extern void pasemi_write_dma_reg(unsigned int reg, unsigned int val);
|
||||
|
||||
/* Channel management routines */
|
||||
|
||||
extern void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type,
|
||||
int total_size, int offset);
|
||||
extern void pasemi_dma_free_chan(struct pasemi_dmachan *chan);
|
||||
|
||||
extern void pasemi_dma_start_chan(const struct pasemi_dmachan *chan,
|
||||
const u32 cmdsta);
|
||||
extern int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan);
|
||||
|
||||
/* Common routines to allocate rings and buffers */
|
||||
|
||||
extern int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size);
|
||||
extern void pasemi_dma_free_ring(struct pasemi_dmachan *chan);
|
||||
|
||||
extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
|
||||
dma_addr_t *handle);
|
||||
extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
|
||||
dma_addr_t *handle);
|
||||
|
||||
/* Initialize the library, must be called before any other functions */
|
||||
extern int pasemi_dma_init(void);
|
||||
|
||||
#endif /* ASM_PASEMI_DMA_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue