mirror of https://gitee.com/openkylin/linux.git
drm/radeon/kms: cleanup r600 blit code
reorganize the code such that only the primitives (i.e., the functions that load the CP ring) are hardware specific; dynamically link the primitives in a (new) pointer structure inside r600_blit at blit initialization time so that the functions that control the blit operations can be made common for r600 and evergreen parts Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Ilija Hadzic
Dave Airlie
parent
638dd7db59
commit
8eec9d6f74
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@ -44,7 +44,6 @@
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#define RECT_UNIT_H 32
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#define RECT_UNIT_W (RADEON_GPU_PAGE_SIZE / 4 / RECT_UNIT_H)
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#define MAX_RECT_DIM 8192
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/* emits 21 on rv770+, 23 on r600 */
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static void
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@ -491,6 +490,27 @@ int r600_blit_init(struct radeon_device *rdev)
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u32 packet2s[16];
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int num_packet2s = 0;
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rdev->r600_blit.primitives.set_render_target = set_render_target;
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rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
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rdev->r600_blit.primitives.set_shaders = set_shaders;
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rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
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rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
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rdev->r600_blit.primitives.set_scissors = set_scissors;
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rdev->r600_blit.primitives.draw_auto = draw_auto;
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rdev->r600_blit.primitives.set_default_state = set_default_state;
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rdev->r600_blit.ring_size_common = 40; /* shaders + def state */
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rdev->r600_blit.ring_size_common += 10; /* fence emit for VB IB */
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rdev->r600_blit.ring_size_common += 5; /* done copy */
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rdev->r600_blit.ring_size_common += 10; /* fence emit for done copy */
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rdev->r600_blit.ring_size_per_loop = 76;
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/* set_render_target emits 2 extra dwords on rv6xx */
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if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
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rdev->r600_blit.ring_size_per_loop += 2;
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rdev->r600_blit.max_dim = 8192;
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/* pin copy shader into vram if already initialized */
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if (rdev->r600_blit.shader_obj)
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goto done;
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@ -608,9 +628,8 @@ static void r600_vb_ib_put(struct radeon_device *rdev)
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radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
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}
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/* FIXME: the function is very similar to evergreen_blit_create_rect, except
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that it different predefined constants; consider commonizing */
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static unsigned r600_blit_create_rect(unsigned num_pages, int *width, int *height)
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static unsigned r600_blit_create_rect(unsigned num_pages,
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int *width, int *height, int max_dim)
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{
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unsigned max_pages;
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unsigned pages = num_pages;
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@ -628,12 +647,12 @@ static unsigned r600_blit_create_rect(unsigned num_pages, int *width, int *heigh
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while (num_pages / rect_order) {
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h *= 2;
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rect_order *= 4;
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if (h >= MAX_RECT_DIM) {
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h = MAX_RECT_DIM;
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if (h >= max_dim) {
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h = max_dim;
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break;
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}
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}
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max_pages = (MAX_RECT_DIM * h) / (RECT_UNIT_W * RECT_UNIT_H);
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max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H);
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if (pages > max_pages)
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pages = max_pages;
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w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
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@ -659,36 +678,29 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_pages)
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{
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int r;
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int ring_size;
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/* loops of emits 64 + fence emit possible */
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int dwords_per_loop = 76, num_loops = 0;
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int num_loops = 0;
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int dwords_per_loop = rdev->r600_blit.ring_size_per_loop;
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r = r600_vb_ib_get(rdev);
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if (r)
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return r;
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/* set_render_target emits 2 extra dwords on rv6xx */
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if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
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dwords_per_loop += 2;
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/* num loops */
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while (num_pages) {
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num_pages -= r600_blit_create_rect(num_pages, NULL, NULL);
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num_pages -= r600_blit_create_rect(num_pages, NULL, NULL,
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rdev->r600_blit.max_dim);
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num_loops++;
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}
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/* calculate number of loops correctly */
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ring_size = num_loops * dwords_per_loop;
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/* set default + shaders */
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ring_size += 40; /* shaders + def state */
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ring_size += 10; /* fence emit for VB IB */
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ring_size += 5; /* done copy */
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ring_size += 10; /* fence emit for done copy */
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ring_size += rdev->r600_blit.ring_size_common;
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r = radeon_ring_lock(rdev, ring_size);
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if (r)
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return r;
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set_default_state(rdev); /* 14 */
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set_shaders(rdev); /* 26 */
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rdev->r600_blit.primitives.set_default_state(rdev);
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rdev->r600_blit.primitives.set_shaders(rdev);
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return 0;
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}
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@ -712,14 +724,17 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
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u64 vb_gpu_addr;
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u32 *vb;
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DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
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DRM_DEBUG("emitting copy %16llx %16llx %d %d\n",
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src_gpu_addr, dst_gpu_addr,
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num_pages, rdev->r600_blit.vb_used);
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vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
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while (num_pages) {
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int w, h;
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unsigned size_in_bytes;
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unsigned pages_per_loop = r600_blit_create_rect(num_pages, &w, &h);
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unsigned pages_per_loop =
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r600_blit_create_rect(num_pages, &w, &h,
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rdev->r600_blit.max_dim);
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size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
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DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
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@ -743,32 +758,21 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
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vb[10] = i2f(w);
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vb[11] = i2f(h);
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/* src 9 */
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set_tex_resource(rdev, FMT_8_8_8_8, w, h, w, src_gpu_addr);
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/* 5 */
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cp_set_surface_sync(rdev,
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PACKET3_TC_ACTION_ENA, size_in_bytes, src_gpu_addr);
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/* dst 23 */
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set_render_target(rdev, COLOR_8_8_8_8, w, h, dst_gpu_addr);
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/* scissors 12 */
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set_scissors(rdev, 0, 0, w, h);
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/* Vertex buffer setup 14 */
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rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8,
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w, h, w, src_gpu_addr);
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rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
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PACKET3_TC_ACTION_ENA,
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size_in_bytes, src_gpu_addr);
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rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8,
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w, h, dst_gpu_addr);
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rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h);
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vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
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set_vtx_resource(rdev, vb_gpu_addr);
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/* draw 10 */
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draw_auto(rdev);
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/* 5 */
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cp_set_surface_sync(rdev,
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rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr);
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rdev->r600_blit.primitives.draw_auto(rdev);
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rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
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PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
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size_in_bytes, dst_gpu_addr);
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/* 78 ring dwords per loop */
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vb += 12;
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rdev->r600_blit.vb_used += 4*12;
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src_gpu_addr += size_in_bytes;
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@ -522,9 +522,30 @@ struct r600_ih {
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bool enabled;
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};
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struct r600_blit_cp_primitives {
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void (*set_render_target)(struct radeon_device *rdev, int format,
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int w, int h, u64 gpu_addr);
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void (*cp_set_surface_sync)(struct radeon_device *rdev,
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u32 sync_type, u32 size,
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u64 mc_addr);
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void (*set_shaders)(struct radeon_device *rdev);
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void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
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void (*set_tex_resource)(struct radeon_device *rdev,
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int format, int w, int h, int pitch,
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u64 gpu_addr);
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void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
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int x2, int y2);
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void (*draw_auto)(struct radeon_device *rdev);
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void (*set_default_state)(struct radeon_device *rdev);
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};
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struct r600_blit {
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struct mutex mutex;
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struct radeon_bo *shader_obj;
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struct r600_blit_cp_primitives primitives;
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int max_dim;
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int ring_size_common;
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int ring_size_per_loop;
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u64 shader_gpu_addr;
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u32 vs_offset, ps_offset;
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u32 state_offset;
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