mirror of https://gitee.com/openkylin/linux.git
qed: Correct slowpath interrupt scheme
When using INTa, ISR might be called before device is configured for INTa [E.g., due to other device asserting the shared interrupt line], in which case the ISR would read the SISR registers that shouldn't be read unless HW is already configured for INTa. This might break interrupts later on. There's also an MSI-X issue due to this difference, although it's mostly theoretical. This patch changes the initialization order, calling request_irq() for the slowpath interrupt only after the chip is configured for working in the preferred interrupt mode. Signed-off-by: Sudarsana Kalluru <Sudarsana.Kalluru@qlogic.com> Signed-off-by: Manish Chopra <manish.chopra@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -299,6 +299,7 @@ struct qed_hwfn {
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/* Flag indicating whether interrupts are enabled or not*/
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bool b_int_enabled;
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bool b_int_requested;
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struct qed_mcp_info *mcp_info;
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@ -491,6 +492,8 @@ u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
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u32 input_len, u8 *input_buf,
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u32 max_size, u8 *unzip_buf);
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int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
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#define QED_ETH_INTERFACE_VERSION 300
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#endif /* _QED_H */
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@ -783,22 +783,16 @@ void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
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qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
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}
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void qed_int_igu_enable(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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enum qed_int_mode int_mode)
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int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
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enum qed_int_mode int_mode)
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{
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int i;
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p_hwfn->b_int_enabled = 1;
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int rc, i;
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/* Mask non-link attentions */
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for (i = 0; i < 9; i++)
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qed_wr(p_hwfn, p_ptt,
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MISC_REG_AEU_ENABLE1_IGU_OUT_0 + (i << 2), 0);
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/* Enable interrupt Generation */
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qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
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/* Configure AEU signal change to produce attentions for link */
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qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
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qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
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@ -808,6 +802,19 @@ void qed_int_igu_enable(struct qed_hwfn *p_hwfn,
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/* Unmask AEU signals toward IGU */
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qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
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if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
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rc = qed_slowpath_irq_req(p_hwfn);
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if (rc != 0) {
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DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n");
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return -EINVAL;
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}
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p_hwfn->b_int_requested = true;
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}
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/* Enable interrupt Generation */
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qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
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p_hwfn->b_int_enabled = 1;
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return rc;
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}
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void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
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@ -1127,3 +1134,11 @@ int qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
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return info->igu_sb_cnt;
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}
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void qed_int_disable_post_isr_release(struct qed_dev *cdev)
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{
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int i;
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for_each_hwfn(cdev, i)
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cdev->hwfns[i].b_int_requested = false;
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}
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@ -169,10 +169,14 @@ int qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
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int *p_iov_blks);
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/**
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* @file
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* @brief qed_int_disable_post_isr_release - performs the cleanup post ISR
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* release. The API need to be called after releasing all slowpath IRQs
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* of the device.
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*
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* @param cdev
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*
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* @brief Interrupt handler
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*/
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void qed_int_disable_post_isr_release(struct qed_dev *cdev);
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#define QED_CAU_DEF_RX_TIMER_RES 0
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#define QED_CAU_DEF_TX_TIMER_RES 0
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@ -366,10 +370,11 @@ void qed_int_setup(struct qed_hwfn *p_hwfn,
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* @param p_hwfn
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* @param p_ptt
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* @param int_mode
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*
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* @return int
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*/
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void qed_int_igu_enable(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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enum qed_int_mode int_mode);
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int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
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enum qed_int_mode int_mode);
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/**
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* @brief - Initialize CAU status block entry
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@ -476,41 +476,22 @@ static irqreturn_t qed_single_int(int irq, void *dev_instance)
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return rc;
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}
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static int qed_slowpath_irq_req(struct qed_dev *cdev)
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int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
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{
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int i = 0, rc = 0;
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struct qed_dev *cdev = hwfn->cdev;
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int rc = 0;
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u8 id;
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if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
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/* Request all the slowpath MSI-X vectors */
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for (i = 0; i < cdev->num_hwfns; i++) {
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snprintf(cdev->hwfns[i].name, NAME_SIZE,
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"sp-%d-%02x:%02x.%02x",
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i, cdev->pdev->bus->number,
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PCI_SLOT(cdev->pdev->devfn),
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cdev->hwfns[i].abs_pf_id);
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rc = request_irq(cdev->int_params.msix_table[i].vector,
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qed_msix_sp_int, 0,
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cdev->hwfns[i].name,
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cdev->hwfns[i].sp_dpc);
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if (rc)
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break;
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DP_VERBOSE(&cdev->hwfns[i],
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(NETIF_MSG_INTR | QED_MSG_SP),
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id = hwfn->my_id;
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snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
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id, cdev->pdev->bus->number,
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PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
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rc = request_irq(cdev->int_params.msix_table[id].vector,
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qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
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if (!rc)
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DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
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"Requested slowpath MSI-X\n");
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}
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if (i != cdev->num_hwfns) {
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/* Free already request MSI-X vectors */
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for (i--; i >= 0; i--) {
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unsigned int vec =
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cdev->int_params.msix_table[i].vector;
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synchronize_irq(vec);
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free_irq(cdev->int_params.msix_table[i].vector,
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cdev->hwfns[i].sp_dpc);
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}
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}
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} else {
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unsigned long flags = 0;
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@ -534,13 +515,17 @@ static void qed_slowpath_irq_free(struct qed_dev *cdev)
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if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
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for_each_hwfn(cdev, i) {
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if (!cdev->hwfns[i].b_int_requested)
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break;
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synchronize_irq(cdev->int_params.msix_table[i].vector);
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free_irq(cdev->int_params.msix_table[i].vector,
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cdev->hwfns[i].sp_dpc);
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}
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} else {
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free_irq(cdev->pdev->irq, cdev);
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if (QED_LEADING_HWFN(cdev)->b_int_requested)
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free_irq(cdev->pdev->irq, cdev);
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}
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qed_int_disable_post_isr_release(cdev);
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}
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static int qed_nic_stop(struct qed_dev *cdev)
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@ -765,16 +750,11 @@ static int qed_slowpath_start(struct qed_dev *cdev,
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if (rc)
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goto err1;
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/* Request the slowpath IRQ */
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rc = qed_slowpath_irq_req(cdev);
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if (rc)
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goto err2;
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/* Allocate stream for unzipping */
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rc = qed_alloc_stream_mem(cdev);
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if (rc) {
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DP_NOTICE(cdev, "Failed to allocate stream memory\n");
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goto err3;
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goto err2;
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}
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/* Start the slowpath */
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