mirror of https://gitee.com/openkylin/linux.git
iommu/arm-smmu: Implement of_xlate() for SMMUv3
Now that we can properly describe the mapping between PCI RIDs and stream IDs via "iommu-map", and have it fed it to the driver automatically via of_xlate(), rework the SMMUv3 driver to benefit from that, and get rid of the current misuse of the "iommus" binding. Since having of_xlate wired up means that masters will now be given the appropriate DMA ops, we also need to make sure that default domains work properly. This necessitates dispensing with the "whole group at a time" notion for attaching to a domain, as devices which share a group get attached to the group's default domain one by one as they are initially probed. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Robin Murphy
Will Deacon
parent
dc87a98db7
commit
8f78515425
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@ -30,6 +30,7 @@
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#include <linux/msi.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_iommu.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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@ -610,12 +611,9 @@ struct arm_smmu_device {
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struct arm_smmu_strtab_cfg strtab_cfg;
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};
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/* SMMU private data for an IOMMU group */
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struct arm_smmu_group {
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/* SMMU private data for each master */
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struct arm_smmu_master_data {
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struct arm_smmu_device *smmu;
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struct arm_smmu_domain *domain;
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int num_sids;
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u32 *sids;
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struct arm_smmu_strtab_ent ste;
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};
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@ -1555,20 +1553,6 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain)
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return ret;
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}
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static struct arm_smmu_group *arm_smmu_group_get(struct device *dev)
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{
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struct iommu_group *group;
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struct arm_smmu_group *smmu_group;
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group = iommu_group_get(dev);
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if (!group)
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return NULL;
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smmu_group = iommu_group_get_iommudata(group);
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iommu_group_put(group);
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return smmu_group;
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}
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static __le64 *arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid)
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{
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__le64 *step;
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@ -1591,27 +1575,17 @@ static __le64 *arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid)
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return step;
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}
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static int arm_smmu_install_ste_for_group(struct arm_smmu_group *smmu_group)
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static int arm_smmu_install_ste_for_dev(struct iommu_fwspec *fwspec)
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{
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int i;
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struct arm_smmu_domain *smmu_domain = smmu_group->domain;
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struct arm_smmu_strtab_ent *ste = &smmu_group->ste;
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struct arm_smmu_device *smmu = smmu_group->smmu;
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struct arm_smmu_master_data *master = fwspec->iommu_priv;
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struct arm_smmu_device *smmu = master->smmu;
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if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
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ste->s1_cfg = &smmu_domain->s1_cfg;
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ste->s2_cfg = NULL;
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arm_smmu_write_ctx_desc(smmu, ste->s1_cfg);
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} else {
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ste->s1_cfg = NULL;
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ste->s2_cfg = &smmu_domain->s2_cfg;
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}
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for (i = 0; i < smmu_group->num_sids; ++i) {
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u32 sid = smmu_group->sids[i];
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for (i = 0; i < fwspec->num_ids; ++i) {
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u32 sid = fwspec->ids[i];
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__le64 *step = arm_smmu_get_step_for_sid(smmu, sid);
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arm_smmu_write_strtab_ent(smmu, sid, step, ste);
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arm_smmu_write_strtab_ent(smmu, sid, step, &master->ste);
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}
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return 0;
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@ -1619,13 +1593,11 @@ static int arm_smmu_install_ste_for_group(struct arm_smmu_group *smmu_group)
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static void arm_smmu_detach_dev(struct device *dev)
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{
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struct arm_smmu_group *smmu_group = arm_smmu_group_get(dev);
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struct arm_smmu_master_data *master = dev->iommu_fwspec->iommu_priv;
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smmu_group->ste.bypass = true;
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if (arm_smmu_install_ste_for_group(smmu_group) < 0)
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master->ste.bypass = true;
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if (arm_smmu_install_ste_for_dev(dev->iommu_fwspec) < 0)
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dev_warn(dev, "failed to install bypass STE\n");
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smmu_group->domain = NULL;
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}
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static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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@ -1633,16 +1605,20 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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int ret = 0;
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struct arm_smmu_device *smmu;
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struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
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struct arm_smmu_group *smmu_group = arm_smmu_group_get(dev);
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struct arm_smmu_master_data *master;
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struct arm_smmu_strtab_ent *ste;
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if (!smmu_group)
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if (!dev->iommu_fwspec)
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return -ENOENT;
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master = dev->iommu_fwspec->iommu_priv;
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smmu = master->smmu;
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ste = &master->ste;
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/* Already attached to a different domain? */
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if (smmu_group->domain && smmu_group->domain != smmu_domain)
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if (!ste->bypass)
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arm_smmu_detach_dev(dev);
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smmu = smmu_group->smmu;
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mutex_lock(&smmu_domain->init_mutex);
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if (!smmu_domain->smmu) {
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@ -1661,21 +1637,21 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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goto out_unlock;
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}
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/* Group already attached to this domain? */
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if (smmu_group->domain)
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goto out_unlock;
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ste->bypass = false;
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ste->valid = true;
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smmu_group->domain = smmu_domain;
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if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
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ste->s1_cfg = &smmu_domain->s1_cfg;
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ste->s2_cfg = NULL;
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arm_smmu_write_ctx_desc(smmu, ste->s1_cfg);
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} else {
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ste->s1_cfg = NULL;
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ste->s2_cfg = &smmu_domain->s2_cfg;
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}
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/*
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* FIXME: This should always be "false" once we have IOMMU-backed
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* DMA ops for all devices behind the SMMU.
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*/
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smmu_group->ste.bypass = domain->type == IOMMU_DOMAIN_DMA;
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ret = arm_smmu_install_ste_for_group(smmu_group);
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ret = arm_smmu_install_ste_for_dev(dev->iommu_fwspec);
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if (ret < 0)
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smmu_group->domain = NULL;
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ste->valid = false;
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out_unlock:
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mutex_unlock(&smmu_domain->init_mutex);
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@ -1734,40 +1710,19 @@ arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)
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return ret;
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}
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static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *sidp)
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static struct platform_driver arm_smmu_driver;
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static int arm_smmu_match_node(struct device *dev, void *data)
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{
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*(u32 *)sidp = alias;
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return 0; /* Continue walking */
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return dev->of_node == data;
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}
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static void __arm_smmu_release_pci_iommudata(void *data)
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static struct arm_smmu_device *arm_smmu_get_by_node(struct device_node *np)
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{
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kfree(data);
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}
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static struct arm_smmu_device *arm_smmu_get_for_pci_dev(struct pci_dev *pdev)
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{
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struct device_node *of_node;
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struct platform_device *smmu_pdev;
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struct arm_smmu_device *smmu = NULL;
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struct pci_bus *bus = pdev->bus;
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/* Walk up to the root bus */
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while (!pci_is_root_bus(bus))
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bus = bus->parent;
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/* Follow the "iommus" phandle from the host controller */
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of_node = of_parse_phandle(bus->bridge->parent->of_node, "iommus", 0);
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if (!of_node)
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return NULL;
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/* See if we can find an SMMU corresponding to the phandle */
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smmu_pdev = of_find_device_by_node(of_node);
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if (smmu_pdev)
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smmu = platform_get_drvdata(smmu_pdev);
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of_node_put(of_node);
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return smmu;
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struct device *dev = driver_find_device(&arm_smmu_driver.driver, NULL,
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np, arm_smmu_match_node);
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put_device(dev);
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return dev ? dev_get_drvdata(dev) : NULL;
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}
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static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)
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@ -1780,94 +1735,74 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)
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return sid < limit;
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}
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static struct iommu_ops arm_smmu_ops;
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static int arm_smmu_add_device(struct device *dev)
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{
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int i, ret;
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u32 sid, *sids;
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struct pci_dev *pdev;
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struct iommu_group *group;
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struct arm_smmu_group *smmu_group;
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struct arm_smmu_device *smmu;
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struct arm_smmu_master_data *master;
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struct iommu_fwspec *fwspec = dev->iommu_fwspec;
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struct iommu_group *group;
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/* We only support PCI, for now */
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if (!dev_is_pci(dev))
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if (!fwspec || fwspec->ops != &arm_smmu_ops)
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return -ENODEV;
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pdev = to_pci_dev(dev);
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group = iommu_group_get_for_dev(dev);
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if (IS_ERR(group))
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return PTR_ERR(group);
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smmu_group = iommu_group_get_iommudata(group);
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if (!smmu_group) {
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smmu = arm_smmu_get_for_pci_dev(pdev);
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if (!smmu) {
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ret = -ENOENT;
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goto out_remove_dev;
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}
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smmu_group = kzalloc(sizeof(*smmu_group), GFP_KERNEL);
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if (!smmu_group) {
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ret = -ENOMEM;
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goto out_remove_dev;
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}
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smmu_group->ste.valid = true;
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smmu_group->smmu = smmu;
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iommu_group_set_iommudata(group, smmu_group,
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__arm_smmu_release_pci_iommudata);
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/*
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* We _can_ actually withstand dodgy bus code re-calling add_device()
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* without an intervening remove_device()/of_xlate() sequence, but
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* we're not going to do so quietly...
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*/
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if (WARN_ON_ONCE(fwspec->iommu_priv)) {
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master = fwspec->iommu_priv;
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smmu = master->smmu;
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} else {
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smmu = smmu_group->smmu;
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smmu = arm_smmu_get_by_node(to_of_node(fwspec->iommu_fwnode));
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if (!smmu)
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return -ENODEV;
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master = kzalloc(sizeof(*master), GFP_KERNEL);
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if (!master)
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return -ENOMEM;
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master->smmu = smmu;
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fwspec->iommu_priv = master;
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}
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/* Assume SID == RID until firmware tells us otherwise */
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pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid);
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for (i = 0; i < smmu_group->num_sids; ++i) {
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/* If we already know about this SID, then we're done */
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if (smmu_group->sids[i] == sid)
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goto out_put_group;
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/* Check the SIDs are in range of the SMMU and our stream table */
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for (i = 0; i < fwspec->num_ids; i++) {
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u32 sid = fwspec->ids[i];
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if (!arm_smmu_sid_in_range(smmu, sid))
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return -ERANGE;
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/* Ensure l2 strtab is initialised */
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if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
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ret = arm_smmu_init_l2_strtab(smmu, sid);
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if (ret)
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return ret;
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}
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}
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/* Check the SID is in range of the SMMU and our stream table */
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if (!arm_smmu_sid_in_range(smmu, sid)) {
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ret = -ERANGE;
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goto out_remove_dev;
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}
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group = iommu_group_get_for_dev(dev);
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if (!IS_ERR(group))
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iommu_group_put(group);
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/* Ensure l2 strtab is initialised */
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if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
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ret = arm_smmu_init_l2_strtab(smmu, sid);
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if (ret)
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goto out_remove_dev;
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}
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/* Resize the SID array for the group */
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smmu_group->num_sids++;
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sids = krealloc(smmu_group->sids, smmu_group->num_sids * sizeof(*sids),
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GFP_KERNEL);
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if (!sids) {
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smmu_group->num_sids--;
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ret = -ENOMEM;
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goto out_remove_dev;
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}
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/* Add the new SID */
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sids[smmu_group->num_sids - 1] = sid;
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smmu_group->sids = sids;
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out_put_group:
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iommu_group_put(group);
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return 0;
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out_remove_dev:
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iommu_group_remove_device(dev);
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iommu_group_put(group);
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return ret;
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return PTR_ERR_OR_ZERO(group);
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}
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static void arm_smmu_remove_device(struct device *dev)
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{
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struct iommu_fwspec *fwspec = dev->iommu_fwspec;
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struct arm_smmu_master_data *master;
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if (!fwspec || fwspec->ops != &arm_smmu_ops)
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return;
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master = fwspec->iommu_priv;
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if (master && master->ste.valid)
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arm_smmu_detach_dev(dev);
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iommu_group_remove_device(dev);
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kfree(master);
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iommu_fwspec_free(dev);
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}
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static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
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@ -1914,6 +1849,15 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
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return ret;
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}
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static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args)
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{
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/* We only support PCI, for now */
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if (!dev_is_pci(dev))
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return -ENODEV;
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return iommu_fwspec_add_ids(dev, args->args, 1);
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}
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static struct iommu_ops arm_smmu_ops = {
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.capable = arm_smmu_capable,
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.domain_alloc = arm_smmu_domain_alloc,
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@ -1928,6 +1872,7 @@ static struct iommu_ops arm_smmu_ops = {
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.device_group = pci_device_group,
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.domain_get_attr = arm_smmu_domain_get_attr,
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.domain_set_attr = arm_smmu_domain_set_attr,
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.of_xlate = arm_smmu_of_xlate,
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.pgsize_bitmap = -1UL, /* Restricted during device attach */
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};
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@ -2662,7 +2607,14 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, smmu);
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/* Reset the device */
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return arm_smmu_device_reset(smmu, bypass);
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ret = arm_smmu_device_reset(smmu, bypass);
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if (ret)
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return ret;
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/* And we're up. Go go go! */
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of_iommu_set_ops(dev->of_node, &arm_smmu_ops);
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pci_request_acs();
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return bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
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}
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static int arm_smmu_device_remove(struct platform_device *pdev)
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@ -2690,22 +2642,14 @@ static struct platform_driver arm_smmu_driver = {
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static int __init arm_smmu_init(void)
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{
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struct device_node *np;
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int ret;
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static bool registered;
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int ret = 0;
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np = of_find_matching_node(NULL, arm_smmu_of_match);
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if (!np)
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return 0;
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of_node_put(np);
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ret = platform_driver_register(&arm_smmu_driver);
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if (ret)
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return ret;
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pci_request_acs();
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return bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
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if (!registered) {
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ret = platform_driver_register(&arm_smmu_driver);
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registered = !ret;
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}
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return ret;
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}
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static void __exit arm_smmu_exit(void)
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@ -2716,6 +2660,20 @@ static void __exit arm_smmu_exit(void)
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subsys_initcall(arm_smmu_init);
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module_exit(arm_smmu_exit);
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static int __init arm_smmu_of_init(struct device_node *np)
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{
|
||||
int ret = arm_smmu_init();
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!of_platform_device_create(np, NULL, platform_bus_type.dev_root))
|
||||
return -ENODEV;
|
||||
|
||||
return 0;
|
||||
}
|
||||
IOMMU_OF_DECLARE(arm_smmuv3, "arm,smmu-v3", arm_smmu_of_init);
|
||||
|
||||
MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");
|
||||
MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
Loading…
Reference in New Issue