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dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields 

Add support for Intel KeemBay DMA registers. These registers are required
to run data transfer between device to memory and memory to device on Intel
KeemBay SoC.

Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Link: https://lore.kernel.org/r/20210125013255.25799-12-jee.heng.sia@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Sia Jee Heng 2021-01-25 09:32:49 +08:00 committed by Vinod Koul
parent 0a35c9a017
commit 8fb1dae090
1 changed files with 14 additions and 0 deletions
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14
drivers/dma/dw-axi-dmac/dw-axi-dmac.h
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@ -63,6 +63,7 @@ struct axi_dma_chip {
struct device *dev; struct device *dev;
int irq; int irq;
void __iomem *regs; void __iomem *regs;
void __iomem *apb_regs;
struct clk *core_clk; struct clk *core_clk;
struct clk *cfgr_clk; struct clk *cfgr_clk;
struct dw_axi_dma *dw; struct dw_axi_dma *dw;
@ -169,6 +170,19 @@ static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan)
#define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */ #define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
#define CH_INTCLEAR 0x098 /* W Chan Interrupt Clear */ #define CH_INTCLEAR 0x098 /* W Chan Interrupt Clear */
/* These Apb registers are used by Intel KeemBay SoC */
#define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
#define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
#define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
#define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
#define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
#define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
#define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
#define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
#define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */
#define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
/* DMAC_CFG */ /* DMAC_CFG */
#define DMAC_EN_POS 0 #define DMAC_EN_POS 0