mirror of https://gitee.com/openkylin/linux.git
i2c: tegra: Remove i2c_dev.clk_divisor_non_hs_mode member
The "non_hs_mode" divisor value is fixed, thus there is no need to have the variable i2c_dev.clk_divisor_non_hs_mode struct member. Let's remove it and move the mode selection into tegra_i2c_init() where it can be united with the timing selection. Reviewed-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
parent
8548a75f3e
commit
8ff727316a
|
@ -250,7 +250,6 @@ struct tegra_i2c_hw_feature {
|
|||
* @msg_buf_remaining: size of unsent data in the message buffer
|
||||
* @msg_read: identifies read transfers
|
||||
* @bus_clk_rate: current I2C bus clock rate
|
||||
* @clk_divisor_non_hs_mode: clock divider for non-high-speed modes
|
||||
* @is_multimaster_mode: track if I2C controller is in multi-master mode
|
||||
* @tx_dma_chan: DMA transmit channel
|
||||
* @rx_dma_chan: DMA receive channel
|
||||
|
@ -281,7 +280,6 @@ struct tegra_i2c_dev {
|
|||
size_t msg_buf_remaining;
|
||||
int msg_read;
|
||||
u32 bus_clk_rate;
|
||||
u16 clk_divisor_non_hs_mode;
|
||||
bool is_multimaster_mode;
|
||||
struct dma_chan *tx_dma_chan;
|
||||
struct dma_chan *rx_dma_chan;
|
||||
|
@ -783,6 +781,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
|
|||
u32 val;
|
||||
int err;
|
||||
u32 clk_divisor, clk_multiplier;
|
||||
u32 non_hs_mode;
|
||||
u32 tsu_thd;
|
||||
u8 tlow, thigh;
|
||||
|
||||
|
@ -805,24 +804,33 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
|
|||
if (i2c_dev->is_vi)
|
||||
tegra_i2c_vi_init(i2c_dev);
|
||||
|
||||
/* Make sure clock divisor programmed correctly */
|
||||
clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
|
||||
i2c_dev->hw->clk_divisor_hs_mode) |
|
||||
FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE,
|
||||
i2c_dev->clk_divisor_non_hs_mode);
|
||||
i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
|
||||
|
||||
if (i2c_dev->bus_clk_rate > I2C_MAX_STANDARD_MODE_FREQ &&
|
||||
i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
|
||||
switch (i2c_dev->bus_clk_rate) {
|
||||
case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
|
||||
default:
|
||||
tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
|
||||
thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
|
||||
tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
|
||||
} else {
|
||||
|
||||
if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ)
|
||||
non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
|
||||
else
|
||||
non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
|
||||
break;
|
||||
|
||||
case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
|
||||
tlow = i2c_dev->hw->tlow_std_mode;
|
||||
thigh = i2c_dev->hw->thigh_std_mode;
|
||||
tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
|
||||
non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Make sure clock divisor programmed correctly */
|
||||
clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
|
||||
i2c_dev->hw->clk_divisor_hs_mode) |
|
||||
FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
|
||||
i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
|
||||
|
||||
if (i2c_dev->hw->has_interface_timing_reg) {
|
||||
val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
|
||||
FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
|
||||
|
@ -837,7 +845,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
|
|||
i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
|
||||
|
||||
clk_multiplier = tlow + thigh + 2;
|
||||
clk_multiplier *= i2c_dev->clk_divisor_non_hs_mode + 1;
|
||||
clk_multiplier *= non_hs_mode + 1;
|
||||
|
||||
err = clk_set_rate(i2c_dev->div_clk,
|
||||
i2c_dev->bus_clk_rate * clk_multiplier);
|
||||
|
@ -1751,18 +1759,6 @@ static int tegra_i2c_probe(struct platform_device *pdev)
|
|||
goto unprepare_fast_clk;
|
||||
}
|
||||
|
||||
if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ &&
|
||||
i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_PLUS_FREQ)
|
||||
i2c_dev->clk_divisor_non_hs_mode =
|
||||
i2c_dev->hw->clk_divisor_fast_plus_mode;
|
||||
else if (i2c_dev->bus_clk_rate > I2C_MAX_STANDARD_MODE_FREQ &&
|
||||
i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_FREQ)
|
||||
i2c_dev->clk_divisor_non_hs_mode =
|
||||
i2c_dev->hw->clk_divisor_fast_mode;
|
||||
else
|
||||
i2c_dev->clk_divisor_non_hs_mode =
|
||||
i2c_dev->hw->clk_divisor_std_mode;
|
||||
|
||||
ret = clk_prepare(i2c_dev->div_clk);
|
||||
if (ret < 0) {
|
||||
dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
|
||||
|
|
Loading…
Reference in New Issue