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arm64: dts: fvp: Fix SMMU DT node 

The SMMU name in the RevC FVP DT file was not fully binding compliant.

Adjust the node name to match the binding's list of allowed names, also
shuffle the order of the interrupts to comply with the expected order.

Link: https://lore.kernel.org/r/20200513103016.130417-15-andre.przywara@arm.com
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This commit is contained in:
Andre Przywara 2020-05-13 11:30:10 +01:00 committed by Sudeep Holla
parent 608f1b6cf3
commit 906e6dd481
1 changed files with 4 additions and 4 deletions
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8
arch/arm64/boot/dts/arm/fvp-base-revc.dts
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@ -172,14 +172,14 @@ pci: pci@40000000 {
dma-coherent; dma-coherent;
}; };
smmu: smmu@2b400000 { smmu: iommu@2b400000 {
compatible = "arm,smmu-v3"; compatible = "arm,smmu-v3";
reg = <0x0 0x2b400000 0x0 0x100000>; reg = <0x0 0x2b400000 0x0 0x100000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>; interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
dma-coherent; dma-coherent;
#iommu-cells = <1>; #iommu-cells = <1>;
msi-parent = <&its 0x10000>; msi-parent = <&its 0x10000>;