mirror of https://gitee.com/openkylin/linux.git
Merge remote-tracking branches 'spi/topic/fsl-espi', 'spi/topic/gpio', 'spi/topic/hspi', 'spi/topic/mpc512x', 'spi/topic/msiof', 'spi/topic/nuc900', 'spi/topic/oc-tiny', 'spi/topic/omap', 'spi/topic/orion' and 'spi/topic/pci' into spi-linus
This commit is contained in:
parent
36e66bf84f
714bb654e9
ba1271bb05
c6c07b4f6d
e1d0cd473b
50a7799829
7c7ccc52fc
e826a7ff69
84acfd4340
bb489841b1
9a21e4770a
commit
907e26b6f5
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@ -67,7 +67,7 @@ only 1(SINGLE), 2(DUAL) and 4(QUAD).
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Dual/Quad mode is not allowed when 3-wire mode is used.
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Dual/Quad mode is not allowed when 3-wire mode is used.
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If a gpio chipselect is used for the SPI slave the gpio number will be passed
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If a gpio chipselect is used for the SPI slave the gpio number will be passed
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via the cs_gpio
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via the SPI master node cs-gpios property.
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SPI example for an MPC5200 SPI bus:
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SPI example for an MPC5200 SPI bus:
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spi@f00 {
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spi@f00 {
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@ -307,6 +307,7 @@ config SPI_OMAP_UWIRE
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config SPI_OMAP24XX
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config SPI_OMAP24XX
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tristate "McSPI driver for OMAP"
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tristate "McSPI driver for OMAP"
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depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SH
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depends on ARCH_OMAP2PLUS || COMPILE_TEST
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depends on ARCH_OMAP2PLUS || COMPILE_TEST
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help
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help
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SPI master controller for OMAP24XX and later Multichannel SPI
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SPI master controller for OMAP24XX and later Multichannel SPI
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@ -413,7 +414,8 @@ config SPI_SC18IS602
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config SPI_SH_MSIOF
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config SPI_SH_MSIOF
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tristate "SuperH MSIOF SPI controller"
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tristate "SuperH MSIOF SPI controller"
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depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
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depends on HAVE_CLK
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depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
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select SPI_BITBANG
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select SPI_BITBANG
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help
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help
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SPI driver for SuperH and SH Mobile MSIOF blocks.
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SPI driver for SuperH and SH Mobile MSIOF blocks.
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@ -125,7 +125,7 @@ static int spi_resume(struct pci_dev *pdev)
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#define spi_resume NULL
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#define spi_resume NULL
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#endif
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#endif
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static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
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static const struct pci_device_id pci_ids[] = {
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/* Intel MID platform SPI controller 0 */
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/* Intel MID platform SPI controller 0 */
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) },
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{},
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{},
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@ -705,7 +705,7 @@ static int of_fsl_espi_probe(struct platform_device *ofdev)
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goto err;
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goto err;
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irq = irq_of_parse_and_map(np, 0);
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irq = irq_of_parse_and_map(np, 0);
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if (!ret) {
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if (!irq) {
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ret = -EINVAL;
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ret = -EINVAL;
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goto err;
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goto err;
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}
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}
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@ -727,6 +727,66 @@ static int of_fsl_espi_remove(struct platform_device *dev)
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return mpc8xxx_spi_remove(&dev->dev);
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return mpc8xxx_spi_remove(&dev->dev);
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}
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}
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#ifdef CONFIG_PM_SLEEP
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static int of_fsl_espi_suspend(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct mpc8xxx_spi *mpc8xxx_spi;
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struct fsl_espi_reg *reg_base;
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u32 regval;
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int ret;
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mpc8xxx_spi = spi_master_get_devdata(master);
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reg_base = mpc8xxx_spi->reg_base;
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ret = spi_master_suspend(master);
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if (ret) {
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dev_warn(dev, "cannot suspend master\n");
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return ret;
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}
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regval = mpc8xxx_spi_read_reg(®_base->mode);
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regval &= ~SPMODE_ENABLE;
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mpc8xxx_spi_write_reg(®_base->mode, regval);
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return 0;
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}
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static int of_fsl_espi_resume(struct device *dev)
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{
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struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
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struct spi_master *master = dev_get_drvdata(dev);
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struct mpc8xxx_spi *mpc8xxx_spi;
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struct fsl_espi_reg *reg_base;
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u32 regval;
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int i;
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mpc8xxx_spi = spi_master_get_devdata(master);
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reg_base = mpc8xxx_spi->reg_base;
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/* SPI controller initializations */
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mpc8xxx_spi_write_reg(®_base->mode, 0);
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mpc8xxx_spi_write_reg(®_base->mask, 0);
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mpc8xxx_spi_write_reg(®_base->command, 0);
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mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
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/* Init eSPI CS mode register */
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for (i = 0; i < pdata->max_chipselect; i++)
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mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
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/* Enable SPI interface */
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regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
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mpc8xxx_spi_write_reg(®_base->mode, regval);
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return spi_master_resume(master);
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}
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#endif /* CONFIG_PM_SLEEP */
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static const struct dev_pm_ops espi_pm = {
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SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
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};
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static const struct of_device_id of_fsl_espi_match[] = {
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static const struct of_device_id of_fsl_espi_match[] = {
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{ .compatible = "fsl,mpc8536-espi" },
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{ .compatible = "fsl,mpc8536-espi" },
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{}
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{}
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@ -738,6 +798,7 @@ static struct platform_driver fsl_espi_driver = {
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.name = "fsl_espi",
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.name = "fsl_espi",
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.owner = THIS_MODULE,
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.owner = THIS_MODULE,
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.of_match_table = of_fsl_espi_match,
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.of_match_table = of_fsl_espi_match,
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.pm = &espi_pm,
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},
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},
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.probe = of_fsl_espi_probe,
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.probe = of_fsl_espi_probe,
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.remove = of_fsl_espi_remove,
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.remove = of_fsl_espi_remove,
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@ -115,17 +115,17 @@ spi_to_pdata(const struct spi_device *spi)
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static inline void setsck(const struct spi_device *spi, int is_on)
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static inline void setsck(const struct spi_device *spi, int is_on)
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{
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{
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gpio_set_value(SPI_SCK_GPIO, is_on);
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gpio_set_value_cansleep(SPI_SCK_GPIO, is_on);
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}
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}
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static inline void setmosi(const struct spi_device *spi, int is_on)
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static inline void setmosi(const struct spi_device *spi, int is_on)
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{
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{
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gpio_set_value(SPI_MOSI_GPIO, is_on);
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gpio_set_value_cansleep(SPI_MOSI_GPIO, is_on);
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}
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}
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static inline int getmiso(const struct spi_device *spi)
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static inline int getmiso(const struct spi_device *spi)
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{
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{
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return !!gpio_get_value(SPI_MISO_GPIO);
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return !!gpio_get_value_cansleep(SPI_MISO_GPIO);
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}
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}
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#undef pdata
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#undef pdata
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@ -229,7 +229,7 @@ static void spi_gpio_chipselect(struct spi_device *spi, int is_active)
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if (cs != SPI_GPIO_NO_CHIPSELECT) {
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if (cs != SPI_GPIO_NO_CHIPSELECT) {
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/* SPI is normally active-low */
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/* SPI is normally active-low */
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gpio_set_value(cs, (spi->mode & SPI_CS_HIGH) ? is_active : !is_active);
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gpio_set_value_cansleep(cs, (spi->mode & SPI_CS_HIGH) ? is_active : !is_active);
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}
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}
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}
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}
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@ -504,7 +504,7 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
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master->cleanup = mpc512x_psc_spi_cleanup;
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master->cleanup = mpc512x_psc_spi_cleanup;
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master->dev.of_node = dev->of_node;
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master->dev.of_node = dev->of_node;
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tempp = ioremap(regaddr, size);
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tempp = devm_ioremap(dev, regaddr, size);
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if (!tempp) {
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if (!tempp) {
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dev_err(dev, "could not ioremap I/O port range\n");
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dev_err(dev, "could not ioremap I/O port range\n");
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ret = -EFAULT;
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ret = -EFAULT;
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@ -513,9 +513,8 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
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mps->psc = tempp;
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mps->psc = tempp;
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mps->fifo =
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mps->fifo =
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(struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
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(struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
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ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
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ret = request_irq(mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
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"mpc512x-psc-spi", mps);
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"mpc512x-psc-spi", mps);
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if (ret)
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if (ret)
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goto free_master;
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goto free_master;
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init_completion(&mps->txisrdone);
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init_completion(&mps->txisrdone);
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@ -525,11 +524,11 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
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clk = devm_clk_get(dev, clk_name);
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clk = devm_clk_get(dev, clk_name);
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if (IS_ERR(clk)) {
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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ret = PTR_ERR(clk);
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goto free_irq;
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goto free_master;
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}
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}
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ret = clk_prepare_enable(clk);
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ret = clk_prepare_enable(clk);
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if (ret)
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if (ret)
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goto free_irq;
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goto free_master;
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mps->clk_mclk = clk;
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mps->clk_mclk = clk;
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mps->mclk_rate = clk_get_rate(clk);
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mps->mclk_rate = clk_get_rate(clk);
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@ -545,11 +544,7 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
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free_clock:
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free_clock:
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clk_disable_unprepare(mps->clk_mclk);
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clk_disable_unprepare(mps->clk_mclk);
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free_irq:
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free_irq(mps->irq, mps);
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free_master:
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free_master:
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if (mps->psc)
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iounmap(mps->psc);
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spi_master_put(master);
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spi_master_put(master);
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return ret;
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return ret;
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@ -561,9 +556,6 @@ static int mpc512x_psc_spi_do_remove(struct device *dev)
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struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
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struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
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clk_disable_unprepare(mps->clk_mclk);
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clk_disable_unprepare(mps->clk_mclk);
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free_irq(mps->irq, mps);
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if (mps->psc)
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iounmap(mps->psc);
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return 0;
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return 0;
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}
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}
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@ -57,7 +57,6 @@ struct nuc900_spi {
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const unsigned char *tx;
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const unsigned char *tx;
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unsigned char *rx;
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unsigned char *rx;
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struct clk *clk;
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struct clk *clk;
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struct resource *ioarea;
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struct spi_master *master;
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struct spi_master *master;
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struct spi_device *curdev;
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struct spi_device *curdev;
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struct device *dev;
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struct device *dev;
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@ -344,8 +343,7 @@ static int nuc900_spi_probe(struct platform_device *pdev)
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master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi));
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master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi));
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if (master == NULL) {
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if (master == NULL) {
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dev_err(&pdev->dev, "No memory for spi_master\n");
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dev_err(&pdev->dev, "No memory for spi_master\n");
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err = -ENOMEM;
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return -ENOMEM;
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goto err_nomem;
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|
||||||
}
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}
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hw = spi_master_get_devdata(master);
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hw = spi_master_get_devdata(master);
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@ -370,46 +368,31 @@ static int nuc900_spi_probe(struct platform_device *pdev)
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hw->bitbang.txrx_bufs = nuc900_spi_txrx;
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hw->bitbang.txrx_bufs = nuc900_spi_txrx;
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hw->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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hw->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (hw->res == NULL) {
|
hw->regs = devm_ioremap_resource(&pdev->dev, hw->res);
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dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
|
if (IS_ERR(hw->regs)) {
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err = -ENOENT;
|
err = PTR_ERR(hw->regs);
|
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goto err_pdata;
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goto err_pdata;
|
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}
|
}
|
||||||
|
|
||||||
hw->ioarea = request_mem_region(hw->res->start,
|
|
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resource_size(hw->res), pdev->name);
|
|
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|
|
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if (hw->ioarea == NULL) {
|
|
||||||
dev_err(&pdev->dev, "Cannot reserve region\n");
|
|
||||||
err = -ENXIO;
|
|
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goto err_pdata;
|
|
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}
|
|
||||||
|
|
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hw->regs = ioremap(hw->res->start, resource_size(hw->res));
|
|
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if (hw->regs == NULL) {
|
|
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dev_err(&pdev->dev, "Cannot map IO\n");
|
|
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err = -ENXIO;
|
|
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goto err_iomap;
|
|
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}
|
|
||||||
|
|
||||||
hw->irq = platform_get_irq(pdev, 0);
|
hw->irq = platform_get_irq(pdev, 0);
|
||||||
if (hw->irq < 0) {
|
if (hw->irq < 0) {
|
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dev_err(&pdev->dev, "No IRQ specified\n");
|
dev_err(&pdev->dev, "No IRQ specified\n");
|
||||||
err = -ENOENT;
|
err = -ENOENT;
|
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goto err_irq;
|
goto err_pdata;
|
||||||
}
|
}
|
||||||
|
|
||||||
err = request_irq(hw->irq, nuc900_spi_irq, 0, pdev->name, hw);
|
err = devm_request_irq(&pdev->dev, hw->irq, nuc900_spi_irq, 0,
|
||||||
|
pdev->name, hw);
|
||||||
if (err) {
|
if (err) {
|
||||||
dev_err(&pdev->dev, "Cannot claim IRQ\n");
|
dev_err(&pdev->dev, "Cannot claim IRQ\n");
|
||||||
goto err_irq;
|
goto err_pdata;
|
||||||
}
|
}
|
||||||
|
|
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hw->clk = clk_get(&pdev->dev, "spi");
|
hw->clk = devm_clk_get(&pdev->dev, "spi");
|
||||||
if (IS_ERR(hw->clk)) {
|
if (IS_ERR(hw->clk)) {
|
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dev_err(&pdev->dev, "No clock for device\n");
|
dev_err(&pdev->dev, "No clock for device\n");
|
||||||
err = PTR_ERR(hw->clk);
|
err = PTR_ERR(hw->clk);
|
||||||
goto err_clk;
|
goto err_pdata;
|
||||||
}
|
}
|
||||||
|
|
||||||
mfp_set_groupg(&pdev->dev, NULL);
|
mfp_set_groupg(&pdev->dev, NULL);
|
||||||
|
@ -425,17 +408,8 @@ static int nuc900_spi_probe(struct platform_device *pdev)
|
||||||
|
|
||||||
err_register:
|
err_register:
|
||||||
clk_disable(hw->clk);
|
clk_disable(hw->clk);
|
||||||
clk_put(hw->clk);
|
|
||||||
err_clk:
|
|
||||||
free_irq(hw->irq, hw);
|
|
||||||
err_irq:
|
|
||||||
iounmap(hw->regs);
|
|
||||||
err_iomap:
|
|
||||||
release_mem_region(hw->res->start, resource_size(hw->res));
|
|
||||||
kfree(hw->ioarea);
|
|
||||||
err_pdata:
|
err_pdata:
|
||||||
spi_master_put(hw->master);
|
spi_master_put(hw->master);
|
||||||
err_nomem:
|
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -443,18 +417,8 @@ static int nuc900_spi_remove(struct platform_device *dev)
|
||||||
{
|
{
|
||||||
struct nuc900_spi *hw = platform_get_drvdata(dev);
|
struct nuc900_spi *hw = platform_get_drvdata(dev);
|
||||||
|
|
||||||
free_irq(hw->irq, hw);
|
|
||||||
|
|
||||||
spi_bitbang_stop(&hw->bitbang);
|
spi_bitbang_stop(&hw->bitbang);
|
||||||
|
|
||||||
clk_disable(hw->clk);
|
clk_disable(hw->clk);
|
||||||
clk_put(hw->clk);
|
|
||||||
|
|
||||||
iounmap(hw->regs);
|
|
||||||
|
|
||||||
release_mem_region(hw->res->start, resource_size(hw->res));
|
|
||||||
kfree(hw->ioarea);
|
|
||||||
|
|
||||||
spi_master_put(hw->master);
|
spi_master_put(hw->master);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -153,62 +153,22 @@ static int tiny_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
|
||||||
}
|
}
|
||||||
|
|
||||||
wait_for_completion(&hw->done);
|
wait_for_completion(&hw->done);
|
||||||
} else if (txp && rxp) {
|
|
||||||
/* we need to tighten the transfer loop */
|
|
||||||
writeb(*txp++, hw->base + TINY_SPI_TXDATA);
|
|
||||||
if (t->len > 1) {
|
|
||||||
writeb(*txp++, hw->base + TINY_SPI_TXDATA);
|
|
||||||
for (i = 2; i < t->len; i++) {
|
|
||||||
u8 rx, tx = *txp++;
|
|
||||||
tiny_spi_wait_txr(hw);
|
|
||||||
rx = readb(hw->base + TINY_SPI_TXDATA);
|
|
||||||
writeb(tx, hw->base + TINY_SPI_TXDATA);
|
|
||||||
*rxp++ = rx;
|
|
||||||
}
|
|
||||||
tiny_spi_wait_txr(hw);
|
|
||||||
*rxp++ = readb(hw->base + TINY_SPI_TXDATA);
|
|
||||||
}
|
|
||||||
tiny_spi_wait_txe(hw);
|
|
||||||
*rxp++ = readb(hw->base + TINY_SPI_RXDATA);
|
|
||||||
} else if (rxp) {
|
|
||||||
writeb(0, hw->base + TINY_SPI_TXDATA);
|
|
||||||
if (t->len > 1) {
|
|
||||||
writeb(0,
|
|
||||||
hw->base + TINY_SPI_TXDATA);
|
|
||||||
for (i = 2; i < t->len; i++) {
|
|
||||||
u8 rx;
|
|
||||||
tiny_spi_wait_txr(hw);
|
|
||||||
rx = readb(hw->base + TINY_SPI_TXDATA);
|
|
||||||
writeb(0, hw->base + TINY_SPI_TXDATA);
|
|
||||||
*rxp++ = rx;
|
|
||||||
}
|
|
||||||
tiny_spi_wait_txr(hw);
|
|
||||||
*rxp++ = readb(hw->base + TINY_SPI_TXDATA);
|
|
||||||
}
|
|
||||||
tiny_spi_wait_txe(hw);
|
|
||||||
*rxp++ = readb(hw->base + TINY_SPI_RXDATA);
|
|
||||||
} else if (txp) {
|
|
||||||
writeb(*txp++, hw->base + TINY_SPI_TXDATA);
|
|
||||||
if (t->len > 1) {
|
|
||||||
writeb(*txp++, hw->base + TINY_SPI_TXDATA);
|
|
||||||
for (i = 2; i < t->len; i++) {
|
|
||||||
u8 tx = *txp++;
|
|
||||||
tiny_spi_wait_txr(hw);
|
|
||||||
writeb(tx, hw->base + TINY_SPI_TXDATA);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
tiny_spi_wait_txe(hw);
|
|
||||||
} else {
|
} else {
|
||||||
writeb(0, hw->base + TINY_SPI_TXDATA);
|
/* we need to tighten the transfer loop */
|
||||||
if (t->len > 1) {
|
writeb(txp ? *txp++ : 0, hw->base + TINY_SPI_TXDATA);
|
||||||
writeb(0, hw->base + TINY_SPI_TXDATA);
|
for (i = 1; i < t->len; i++) {
|
||||||
for (i = 2; i < t->len; i++) {
|
writeb(txp ? *txp++ : 0, hw->base + TINY_SPI_TXDATA);
|
||||||
|
|
||||||
|
if (rxp || (i != t->len - 1))
|
||||||
tiny_spi_wait_txr(hw);
|
tiny_spi_wait_txr(hw);
|
||||||
writeb(0, hw->base + TINY_SPI_TXDATA);
|
if (rxp)
|
||||||
}
|
*rxp++ = readb(hw->base + TINY_SPI_TXDATA);
|
||||||
}
|
}
|
||||||
tiny_spi_wait_txe(hw);
|
tiny_spi_wait_txe(hw);
|
||||||
|
if (rxp)
|
||||||
|
*rxp++ = readb(hw->base + TINY_SPI_RXDATA);
|
||||||
}
|
}
|
||||||
|
|
||||||
return t->len;
|
return t->len;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -470,31 +470,12 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int omap1_spi100k_remove(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct spi_master *master;
|
|
||||||
struct omap1_spi100k *spi100k;
|
|
||||||
struct resource *r;
|
|
||||||
int status = 0;
|
|
||||||
|
|
||||||
master = platform_get_drvdata(pdev);
|
|
||||||
spi100k = spi_master_get_devdata(master);
|
|
||||||
|
|
||||||
if (status != 0)
|
|
||||||
return status;
|
|
||||||
|
|
||||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct platform_driver omap1_spi100k_driver = {
|
static struct platform_driver omap1_spi100k_driver = {
|
||||||
.driver = {
|
.driver = {
|
||||||
.name = "omap1_spi100k",
|
.name = "omap1_spi100k",
|
||||||
.owner = THIS_MODULE,
|
.owner = THIS_MODULE,
|
||||||
},
|
},
|
||||||
.probe = omap1_spi100k_probe,
|
.probe = omap1_spi100k_probe,
|
||||||
.remove = omap1_spi100k_remove,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
module_platform_driver(omap1_spi100k_driver);
|
module_platform_driver(omap1_spi100k_driver);
|
||||||
|
@ -502,4 +483,3 @@ module_platform_driver(omap1_spi100k_driver);
|
||||||
MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
|
MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
|
||||||
MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
|
MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
|
||||||
MODULE_LICENSE("GPL");
|
MODULE_LICENSE("GPL");
|
||||||
|
|
||||||
|
|
|
@ -157,14 +157,14 @@ static inline void mcspi_write_reg(struct spi_master *master,
|
||||||
{
|
{
|
||||||
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
||||||
|
|
||||||
__raw_writel(val, mcspi->base + idx);
|
writel_relaxed(val, mcspi->base + idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
|
static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
|
||||||
{
|
{
|
||||||
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
||||||
|
|
||||||
return __raw_readl(mcspi->base + idx);
|
return readl_relaxed(mcspi->base + idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void mcspi_write_cs_reg(const struct spi_device *spi,
|
static inline void mcspi_write_cs_reg(const struct spi_device *spi,
|
||||||
|
@ -172,14 +172,14 @@ static inline void mcspi_write_cs_reg(const struct spi_device *spi,
|
||||||
{
|
{
|
||||||
struct omap2_mcspi_cs *cs = spi->controller_state;
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
||||||
|
|
||||||
__raw_writel(val, cs->base + idx);
|
writel_relaxed(val, cs->base + idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
|
static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
|
||||||
{
|
{
|
||||||
struct omap2_mcspi_cs *cs = spi->controller_state;
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
||||||
|
|
||||||
return __raw_readl(cs->base + idx);
|
return readl_relaxed(cs->base + idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
|
static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
|
||||||
|
@ -338,7 +338,7 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
|
||||||
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
|
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
|
||||||
|
|
||||||
list_for_each_entry(cs, &ctx->cs, node)
|
list_for_each_entry(cs, &ctx->cs, node)
|
||||||
__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
|
writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
|
static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
|
||||||
|
@ -346,9 +346,9 @@ static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
|
||||||
unsigned long timeout;
|
unsigned long timeout;
|
||||||
|
|
||||||
timeout = jiffies + msecs_to_jiffies(1000);
|
timeout = jiffies + msecs_to_jiffies(1000);
|
||||||
while (!(__raw_readl(reg) & bit)) {
|
while (!(readl_relaxed(reg) & bit)) {
|
||||||
if (time_after(jiffies, timeout)) {
|
if (time_after(jiffies, timeout)) {
|
||||||
if (!(__raw_readl(reg) & bit))
|
if (!(readl_relaxed(reg) & bit))
|
||||||
return -ETIMEDOUT;
|
return -ETIMEDOUT;
|
||||||
else
|
else
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -675,7 +675,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
|
||||||
}
|
}
|
||||||
dev_vdbg(&spi->dev, "write-%d %02x\n",
|
dev_vdbg(&spi->dev, "write-%d %02x\n",
|
||||||
word_len, *tx);
|
word_len, *tx);
|
||||||
__raw_writel(*tx++, tx_reg);
|
writel_relaxed(*tx++, tx_reg);
|
||||||
}
|
}
|
||||||
if (rx != NULL) {
|
if (rx != NULL) {
|
||||||
if (mcspi_wait_for_reg_bit(chstat_reg,
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
||||||
|
@ -687,7 +687,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
|
||||||
if (c == 1 && tx == NULL &&
|
if (c == 1 && tx == NULL &&
|
||||||
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
|
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
|
||||||
omap2_mcspi_set_enable(spi, 0);
|
omap2_mcspi_set_enable(spi, 0);
|
||||||
*rx++ = __raw_readl(rx_reg);
|
*rx++ = readl_relaxed(rx_reg);
|
||||||
dev_vdbg(&spi->dev, "read-%d %02x\n",
|
dev_vdbg(&spi->dev, "read-%d %02x\n",
|
||||||
word_len, *(rx - 1));
|
word_len, *(rx - 1));
|
||||||
if (mcspi_wait_for_reg_bit(chstat_reg,
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
||||||
|
@ -701,7 +701,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
|
||||||
omap2_mcspi_set_enable(spi, 0);
|
omap2_mcspi_set_enable(spi, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
*rx++ = __raw_readl(rx_reg);
|
*rx++ = readl_relaxed(rx_reg);
|
||||||
dev_vdbg(&spi->dev, "read-%d %02x\n",
|
dev_vdbg(&spi->dev, "read-%d %02x\n",
|
||||||
word_len, *(rx - 1));
|
word_len, *(rx - 1));
|
||||||
}
|
}
|
||||||
|
@ -722,7 +722,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
|
||||||
}
|
}
|
||||||
dev_vdbg(&spi->dev, "write-%d %04x\n",
|
dev_vdbg(&spi->dev, "write-%d %04x\n",
|
||||||
word_len, *tx);
|
word_len, *tx);
|
||||||
__raw_writel(*tx++, tx_reg);
|
writel_relaxed(*tx++, tx_reg);
|
||||||
}
|
}
|
||||||
if (rx != NULL) {
|
if (rx != NULL) {
|
||||||
if (mcspi_wait_for_reg_bit(chstat_reg,
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
||||||
|
@ -734,7 +734,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
|
||||||
if (c == 2 && tx == NULL &&
|
if (c == 2 && tx == NULL &&
|
||||||
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
|
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
|
||||||
omap2_mcspi_set_enable(spi, 0);
|
omap2_mcspi_set_enable(spi, 0);
|
||||||
*rx++ = __raw_readl(rx_reg);
|
*rx++ = readl_relaxed(rx_reg);
|
||||||
dev_vdbg(&spi->dev, "read-%d %04x\n",
|
dev_vdbg(&spi->dev, "read-%d %04x\n",
|
||||||
word_len, *(rx - 1));
|
word_len, *(rx - 1));
|
||||||
if (mcspi_wait_for_reg_bit(chstat_reg,
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
||||||
|
@ -748,7 +748,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
|
||||||
omap2_mcspi_set_enable(spi, 0);
|
omap2_mcspi_set_enable(spi, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
*rx++ = __raw_readl(rx_reg);
|
*rx++ = readl_relaxed(rx_reg);
|
||||||
dev_vdbg(&spi->dev, "read-%d %04x\n",
|
dev_vdbg(&spi->dev, "read-%d %04x\n",
|
||||||
word_len, *(rx - 1));
|
word_len, *(rx - 1));
|
||||||
}
|
}
|
||||||
|
@ -769,7 +769,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
|
||||||
}
|
}
|
||||||
dev_vdbg(&spi->dev, "write-%d %08x\n",
|
dev_vdbg(&spi->dev, "write-%d %08x\n",
|
||||||
word_len, *tx);
|
word_len, *tx);
|
||||||
__raw_writel(*tx++, tx_reg);
|
writel_relaxed(*tx++, tx_reg);
|
||||||
}
|
}
|
||||||
if (rx != NULL) {
|
if (rx != NULL) {
|
||||||
if (mcspi_wait_for_reg_bit(chstat_reg,
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
||||||
|
@ -781,7 +781,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
|
||||||
if (c == 4 && tx == NULL &&
|
if (c == 4 && tx == NULL &&
|
||||||
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
|
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
|
||||||
omap2_mcspi_set_enable(spi, 0);
|
omap2_mcspi_set_enable(spi, 0);
|
||||||
*rx++ = __raw_readl(rx_reg);
|
*rx++ = readl_relaxed(rx_reg);
|
||||||
dev_vdbg(&spi->dev, "read-%d %08x\n",
|
dev_vdbg(&spi->dev, "read-%d %08x\n",
|
||||||
word_len, *(rx - 1));
|
word_len, *(rx - 1));
|
||||||
if (mcspi_wait_for_reg_bit(chstat_reg,
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
||||||
|
@ -795,7 +795,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
|
||||||
omap2_mcspi_set_enable(spi, 0);
|
omap2_mcspi_set_enable(spi, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
*rx++ = __raw_readl(rx_reg);
|
*rx++ = readl_relaxed(rx_reg);
|
||||||
dev_vdbg(&spi->dev, "read-%d %08x\n",
|
dev_vdbg(&spi->dev, "read-%d %08x\n",
|
||||||
word_len, *(rx - 1));
|
word_len, *(rx - 1));
|
||||||
}
|
}
|
||||||
|
@ -1107,7 +1107,7 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
|
||||||
|
|
||||||
/* RX_ONLY mode needs dummy data in TX reg */
|
/* RX_ONLY mode needs dummy data in TX reg */
|
||||||
if (t->tx_buf == NULL)
|
if (t->tx_buf == NULL)
|
||||||
__raw_writel(0, cs->base
|
writel_relaxed(0, cs->base
|
||||||
+ OMAP2_MCSPI_TX0);
|
+ OMAP2_MCSPI_TX0);
|
||||||
|
|
||||||
if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
|
if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
|
||||||
|
@ -1470,9 +1470,9 @@ static int omap2_mcspi_resume(struct device *dev)
|
||||||
* change in account.
|
* change in account.
|
||||||
*/
|
*/
|
||||||
cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
|
cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
|
||||||
__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
|
writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
|
||||||
cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
|
cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
|
||||||
__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
|
writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
pm_runtime_mark_last_busy(mcspi->dev);
|
pm_runtime_mark_last_busy(mcspi->dev);
|
||||||
|
|
|
@ -434,7 +434,7 @@ static int orion_spi_probe(struct platform_device *pdev)
|
||||||
spi = spi_master_get_devdata(master);
|
spi = spi_master_get_devdata(master);
|
||||||
spi->master = master;
|
spi->master = master;
|
||||||
|
|
||||||
spi->clk = clk_get(&pdev->dev, NULL);
|
spi->clk = devm_clk_get(&pdev->dev, NULL);
|
||||||
if (IS_ERR(spi->clk)) {
|
if (IS_ERR(spi->clk)) {
|
||||||
status = PTR_ERR(spi->clk);
|
status = PTR_ERR(spi->clk);
|
||||||
goto out;
|
goto out;
|
||||||
|
@ -465,7 +465,6 @@ static int orion_spi_probe(struct platform_device *pdev)
|
||||||
|
|
||||||
out_rel_clk:
|
out_rel_clk:
|
||||||
clk_disable_unprepare(spi->clk);
|
clk_disable_unprepare(spi->clk);
|
||||||
clk_put(spi->clk);
|
|
||||||
out:
|
out:
|
||||||
spi_master_put(master);
|
spi_master_put(master);
|
||||||
return status;
|
return status;
|
||||||
|
@ -481,7 +480,6 @@ static int orion_spi_remove(struct platform_device *pdev)
|
||||||
spi = spi_master_get_devdata(master);
|
spi = spi_master_get_devdata(master);
|
||||||
|
|
||||||
clk_disable_unprepare(spi->clk);
|
clk_disable_unprepare(spi->clk);
|
||||||
clk_put(spi->clk);
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -62,7 +62,7 @@ static void ce4100_spi_remove(struct pci_dev *dev)
|
||||||
platform_device_unregister(pdev);
|
platform_device_unregister(pdev);
|
||||||
}
|
}
|
||||||
|
|
||||||
static DEFINE_PCI_DEVICE_TABLE(ce4100_spi_devices) = {
|
static const struct pci_device_id ce4100_spi_devices[] = {
|
||||||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2e6a) },
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2e6a) },
|
||||||
{ },
|
{ },
|
||||||
};
|
};
|
||||||
|
|
|
@ -197,7 +197,7 @@ static int hspi_transfer_one_message(struct spi_master *master,
|
||||||
|
|
||||||
hspi_write(hspi, SPTBR, tx);
|
hspi_write(hspi, SPTBR, tx);
|
||||||
|
|
||||||
/* wait recive */
|
/* wait receive */
|
||||||
ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
|
ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
break;
|
break;
|
||||||
|
|
|
@ -169,7 +169,7 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
|
||||||
|
|
||||||
static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
|
static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
|
||||||
u32 cpol, u32 cpha,
|
u32 cpol, u32 cpha,
|
||||||
u32 tx_hi_z, u32 lsb_first)
|
u32 tx_hi_z, u32 lsb_first, u32 cs_high)
|
||||||
{
|
{
|
||||||
u32 tmp;
|
u32 tmp;
|
||||||
int edge;
|
int edge;
|
||||||
|
@ -182,8 +182,12 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
|
||||||
* 1 1 11 11 1 1
|
* 1 1 11 11 1 1
|
||||||
*/
|
*/
|
||||||
sh_msiof_write(p, FCTR, 0);
|
sh_msiof_write(p, FCTR, 0);
|
||||||
sh_msiof_write(p, TMDR1, 0xe2000005 | (lsb_first << 24));
|
|
||||||
sh_msiof_write(p, RMDR1, 0x22000005 | (lsb_first << 24));
|
tmp = 0;
|
||||||
|
tmp |= !cs_high << 25;
|
||||||
|
tmp |= lsb_first << 24;
|
||||||
|
sh_msiof_write(p, TMDR1, 0xe0000005 | tmp);
|
||||||
|
sh_msiof_write(p, RMDR1, 0x20000005 | tmp);
|
||||||
|
|
||||||
tmp = 0xa0000000;
|
tmp = 0xa0000000;
|
||||||
tmp |= cpol << 30; /* TSCKIZ */
|
tmp |= cpol << 30; /* TSCKIZ */
|
||||||
|
@ -417,11 +421,12 @@ static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on)
|
||||||
sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
|
sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
|
||||||
!!(spi->mode & SPI_CPHA),
|
!!(spi->mode & SPI_CPHA),
|
||||||
!!(spi->mode & SPI_3WIRE),
|
!!(spi->mode & SPI_3WIRE),
|
||||||
!!(spi->mode & SPI_LSB_FIRST));
|
!!(spi->mode & SPI_LSB_FIRST),
|
||||||
|
!!(spi->mode & SPI_CS_HIGH));
|
||||||
}
|
}
|
||||||
|
|
||||||
/* use spi->controller data for CS (same strategy as spi_gpio) */
|
/* use spi->controller data for CS (same strategy as spi_gpio) */
|
||||||
gpio_set_value((unsigned)spi->controller_data, value);
|
gpio_set_value((uintptr_t)spi->controller_data, value);
|
||||||
|
|
||||||
if (is_on == BITBANG_CS_INACTIVE) {
|
if (is_on == BITBANG_CS_INACTIVE) {
|
||||||
if (test_and_clear_bit(0, &p->flags)) {
|
if (test_and_clear_bit(0, &p->flags)) {
|
||||||
|
@ -635,8 +640,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
|
||||||
master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
|
master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
|
||||||
if (master == NULL) {
|
if (master == NULL) {
|
||||||
dev_err(&pdev->dev, "failed to allocate spi master\n");
|
dev_err(&pdev->dev, "failed to allocate spi master\n");
|
||||||
ret = -ENOMEM;
|
return -ENOMEM;
|
||||||
goto err0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
p = spi_master_get_devdata(master);
|
p = spi_master_get_devdata(master);
|
||||||
|
@ -655,32 +659,38 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
|
||||||
|
|
||||||
init_completion(&p->done);
|
init_completion(&p->done);
|
||||||
|
|
||||||
p->clk = clk_get(&pdev->dev, NULL);
|
p->clk = devm_clk_get(&pdev->dev, NULL);
|
||||||
if (IS_ERR(p->clk)) {
|
if (IS_ERR(p->clk)) {
|
||||||
dev_err(&pdev->dev, "cannot get clock\n");
|
dev_err(&pdev->dev, "cannot get clock\n");
|
||||||
ret = PTR_ERR(p->clk);
|
ret = PTR_ERR(p->clk);
|
||||||
goto err1;
|
goto err1;
|
||||||
}
|
}
|
||||||
|
|
||||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
||||||
i = platform_get_irq(pdev, 0);
|
i = platform_get_irq(pdev, 0);
|
||||||
if (!r || i < 0) {
|
if (i < 0) {
|
||||||
dev_err(&pdev->dev, "cannot get platform resources\n");
|
dev_err(&pdev->dev, "cannot get platform IRQ\n");
|
||||||
ret = -ENOENT;
|
ret = -ENOENT;
|
||||||
goto err2;
|
goto err1;
|
||||||
}
|
|
||||||
p->mapbase = ioremap_nocache(r->start, resource_size(r));
|
|
||||||
if (!p->mapbase) {
|
|
||||||
dev_err(&pdev->dev, "unable to ioremap\n");
|
|
||||||
ret = -ENXIO;
|
|
||||||
goto err2;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = request_irq(i, sh_msiof_spi_irq, 0,
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||||
dev_name(&pdev->dev), p);
|
p->mapbase = devm_ioremap_resource(&pdev->dev, r);
|
||||||
|
if (IS_ERR(p->mapbase)) {
|
||||||
|
ret = PTR_ERR(p->mapbase);
|
||||||
|
goto err1;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
|
||||||
|
dev_name(&pdev->dev), p);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
dev_err(&pdev->dev, "unable to request irq\n");
|
dev_err(&pdev->dev, "unable to request irq\n");
|
||||||
goto err3;
|
goto err1;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = clk_prepare(p->clk);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(&pdev->dev, "unable to prepare clock\n");
|
||||||
|
goto err1;
|
||||||
}
|
}
|
||||||
|
|
||||||
p->pdev = pdev;
|
p->pdev = pdev;
|
||||||
|
@ -719,13 +729,9 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
pm_runtime_disable(&pdev->dev);
|
pm_runtime_disable(&pdev->dev);
|
||||||
err3:
|
clk_unprepare(p->clk);
|
||||||
iounmap(p->mapbase);
|
|
||||||
err2:
|
|
||||||
clk_put(p->clk);
|
|
||||||
err1:
|
err1:
|
||||||
spi_master_put(master);
|
spi_master_put(master);
|
||||||
err0:
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -737,9 +743,7 @@ static int sh_msiof_spi_remove(struct platform_device *pdev)
|
||||||
ret = spi_bitbang_stop(&p->bitbang);
|
ret = spi_bitbang_stop(&p->bitbang);
|
||||||
if (!ret) {
|
if (!ret) {
|
||||||
pm_runtime_disable(&pdev->dev);
|
pm_runtime_disable(&pdev->dev);
|
||||||
free_irq(platform_get_irq(pdev, 0), p);
|
clk_unprepare(p->clk);
|
||||||
iounmap(p->mapbase);
|
|
||||||
clk_put(p->clk);
|
|
||||||
spi_master_put(p->bitbang.master);
|
spi_master_put(p->bitbang.master);
|
||||||
}
|
}
|
||||||
return ret;
|
return ret;
|
||||||
|
|
|
@ -217,7 +217,7 @@ struct pch_pd_dev_save {
|
||||||
struct pch_spi_board_data *board_dat;
|
struct pch_spi_board_data *board_dat;
|
||||||
};
|
};
|
||||||
|
|
||||||
static DEFINE_PCI_DEVICE_TABLE(pch_spi_pcidev_id) = {
|
static const struct pci_device_id pch_spi_pcidev_id[] = {
|
||||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
|
||||||
{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
|
{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
|
||||||
{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
|
{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
|
||||||
|
|
|
@ -1,6 +1,4 @@
|
||||||
/*
|
/*
|
||||||
* arch/arm/mach-w90x900/include/mach/nuc900_spi.h
|
|
||||||
*
|
|
||||||
* Copyright (c) 2009 Nuvoton technology corporation.
|
* Copyright (c) 2009 Nuvoton technology corporation.
|
||||||
*
|
*
|
||||||
* Wan ZongShun <mcuos.com@gmail.com>
|
* Wan ZongShun <mcuos.com@gmail.com>
|
||||||
|
@ -11,8 +9,8 @@
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __ASM_ARCH_SPI_H
|
#ifndef __SPI_NUC900_H
|
||||||
#define __ASM_ARCH_SPI_H
|
#define __SPI_NUC900_H
|
||||||
|
|
||||||
extern void mfp_set_groupg(struct device *dev, const char *subname);
|
extern void mfp_set_groupg(struct device *dev, const char *subname);
|
||||||
|
|
||||||
|
@ -32,4 +30,4 @@ struct nuc900_spi_chip {
|
||||||
unsigned char bits_per_word;
|
unsigned char bits_per_word;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif /* __ASM_ARCH_SPI_H */
|
#endif /* __SPI_NUC900_H */
|
||||||
|
|
Loading…
Reference in New Issue