mirror of https://gitee.com/openkylin/linux.git
i.MX drivers update for 5.7:
- Update SCU power domain driver to include PD ranges for audio, CM40 I2C and INTMUX, also enlarge PD range for mu_b. - Remove IMX_SC_RPC_SVC_ABORT from SCU API, as it was added by mistake. - Increase build test coverage for i.MX8M SoC and IMX_SCU driver. - Improve i.MX GPC power up sequencing to ensure that the reset is properly propagated through the peripheral devices in the power domain. -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl5xhKcUHHNoYXduZ3Vv QGtlcm5lbC5vcmcACgkQUFdYWoewfM4/6gf/e9lFuDNG9HiVsDad6YODwzZZxNF6 AxBqD924W4chqLZboAgahFVrWEyINourkzx9PMYK5gE6D6lxEnHhevbfVOYaw3NT Wjv4TSOCMzzlfzJIeFf+m0vzTR3gOtmE6Cto/HMd95IlF+afCzIWrKW+gAGWoRVH c1sCstForQ8SMoFixCJ+YfV8DXje1wGqgLEquMtn5jih2ZEIijo2XZ4nPs6ip4mV Pf+a3WXuN2NB13U2CKbkonk+JY2d8OFqLNQer7WsNp29wCSJqZB2ewnZP/vGSqvO e/i4BxMTtKg/2DPZFmCZNVbM3aEf0tv2E2c28bcb5qDuJfFu2jE4+olwCg== =LVyO -----END PGP SIGNATURE----- Merge tag 'imx-drivers-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers i.MX drivers update for 5.7: - Update SCU power domain driver to include PD ranges for audio, CM40 I2C and INTMUX, also enlarge PD range for mu_b. - Remove IMX_SC_RPC_SVC_ABORT from SCU API, as it was added by mistake. - Increase build test coverage for i.MX8M SoC and IMX_SCU driver. - Improve i.MX GPC power up sequencing to ensure that the reset is properly propagated through the peripheral devices in the power domain. * tag 'imx-drivers-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx: drop COMPILE_TEST for IMX_SCU_SOC firmware: imx: add COMPILE_TEST for IMX_SCU driver soc: imx: gpc: fix power up sequencing soc: imx: increase build coverage for imx8m soc driver firmware: imx: scu-pd: add power domain for I2C and INTMUX in CM40 SS firmware: imx: Remove IMX_SC_RPC_SVC_ABORT firmware: imx: scu-pd: enlarge PD range for mu_b firmware: imx: scu-pd: Add missing audio PD ranges soc: imx: gpcv2: include linux/sizes.h Link: https://lore.kernel.org/r/20200318051918.32579-1-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
90ae9ee792
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@ -12,7 +12,7 @@ config IMX_DSP
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config IMX_SCU
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bool "IMX SCU Protocol driver"
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depends on IMX_MBOX
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depends on IMX_MBOX || COMPILE_TEST
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help
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The System Controller Firmware (SCFW) is a low-level system function
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which runs on a dedicated Cortex-M core to provide power, clock, and
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@ -93,7 +93,7 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = {
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{ "kpp", IMX_SC_R_KPP, 1, false, 0 },
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{ "fspi", IMX_SC_R_FSPI_0, 2, true, 0 },
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{ "mu_a", IMX_SC_R_MU_0A, 14, true, 0 },
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{ "mu_b", IMX_SC_R_MU_13B, 1, true, 13 },
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{ "mu_b", IMX_SC_R_MU_5B, 9, true, 5 },
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/* CONN SS */
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{ "usb", IMX_SC_R_USB_0, 2, true, 0 },
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@ -109,6 +109,7 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = {
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{ "audio-pll0", IMX_SC_R_AUDIO_PLL_0, 1, false, 0 },
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{ "audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, false, 0 },
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{ "audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, false, 0 },
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{ "audio-clk-1", IMX_SC_R_AUDIO_CLK_1, 1, false, 0 },
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{ "dma0-ch", IMX_SC_R_DMA_0_CH0, 16, true, 0 },
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{ "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 },
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{ "dma2-ch", IMX_SC_R_DMA_2_CH0, 5, true, 0 },
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@ -116,7 +117,13 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = {
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{ "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 },
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{ "esai0", IMX_SC_R_ESAI_0, 1, false, 0 },
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{ "spdif0", IMX_SC_R_SPDIF_0, 1, false, 0 },
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{ "spdif1", IMX_SC_R_SPDIF_1, 1, false, 0 },
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{ "sai", IMX_SC_R_SAI_0, 3, true, 0 },
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{ "sai3", IMX_SC_R_SAI_3, 1, false, 0 },
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{ "sai4", IMX_SC_R_SAI_4, 1, false, 0 },
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{ "sai5", IMX_SC_R_SAI_5, 1, false, 0 },
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{ "sai6", IMX_SC_R_SAI_6, 1, false, 0 },
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{ "sai7", IMX_SC_R_SAI_7, 1, false, 0 },
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{ "amix", IMX_SC_R_AMIX, 1, false, 0 },
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{ "mqs0", IMX_SC_R_MQS_0, 1, false, 0 },
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{ "dsp", IMX_SC_R_DSP, 1, false, 0 },
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@ -158,6 +165,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = {
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/* DC SS */
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{ "dc0", IMX_SC_R_DC_0, 1, false, 0 },
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{ "dc0-pll", IMX_SC_R_DC_0_PLL_0, 2, true, 0 },
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/* CM40 SS */
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{ "cm40_i2c", IMX_SC_R_M4_0_I2C, 1, 0 },
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{ "cm40_intmux", IMX_SC_R_M4_0_INTMUX, 1, 0 },
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};
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static const struct imx_sc_pd_soc imx8qxp_scu_pd = {
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@ -11,7 +11,7 @@ obj-$(CONFIG_ARCH_DOVE) += dove/
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obj-$(CONFIG_MACH_DOVE) += dove/
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obj-y += fsl/
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obj-$(CONFIG_ARCH_GEMINI) += gemini/
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obj-$(CONFIG_ARCH_MXC) += imx/
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obj-y += imx/
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obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/
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obj-$(CONFIG_SOC_XWAY) += lantiq/
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obj-y += mediatek/
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@ -10,11 +10,20 @@ config IMX_GPCV2_PM_DOMAINS
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config IMX_SCU_SOC
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bool "i.MX System Controller Unit SoC info support"
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depends on IMX_SCU || COMPILE_TEST
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depends on IMX_SCU
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select SOC_BUS
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help
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If you say yes here you get support for the NXP i.MX System
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Controller Unit SoC info module, it will provide the SoC info
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like SoC family, ID and revision etc.
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config SOC_IMX8M
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bool "i.MX8M SoC family support"
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depends on ARCH_MXC || COMPILE_TEST
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default ARCH_MXC && ARM64
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help
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If you say yes here you get support for the NXP i.MX8M family
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support, it will provide the SoC info like SoC family,
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ID and revision etc.
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endmenu
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@ -1,5 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
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obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
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obj-$(CONFIG_ARCH_MXC) += soc-imx8.o
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obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
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obj-$(CONFIG_IMX_SCU_SOC) += soc-imx-scu.o
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@ -87,8 +87,8 @@ static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd)
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static int imx6_pm_domain_power_on(struct generic_pm_domain *genpd)
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{
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struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
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int i, ret, sw, sw2iso;
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u32 val;
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int i, ret;
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u32 val, req;
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if (pd->supply) {
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ret = regulator_enable(pd->supply);
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@ -107,17 +107,18 @@ static int imx6_pm_domain_power_on(struct generic_pm_domain *genpd)
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regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
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0x1, 0x1);
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/* Read ISO and ISO2SW power up delays */
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regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
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sw = val & 0x3f;
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sw2iso = (val >> 8) & 0x3f;
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/* Request GPC to power up domain */
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val = BIT(pd->cntr_pdn_bit + 1);
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regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
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req = BIT(pd->cntr_pdn_bit + 1);
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regmap_update_bits(pd->regmap, GPC_CNTR, req, req);
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/* Wait ISO + ISO2SW IPG clock cycles */
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udelay(DIV_ROUND_UP(sw + sw2iso, pd->ipg_rate_mhz));
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/* Wait for the PGC to handle the request */
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ret = regmap_read_poll_timeout(pd->regmap, GPC_CNTR, val, !(val & req),
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1, 50);
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if (ret)
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pr_err("powerup request on domain %s timed out\n", genpd->name);
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/* Wait for reset to propagate through peripherals */
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usleep_range(5, 10);
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/* Disable reset clocks for all devices in the domain */
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for (i = 0; i < pd->num_clks; i++)
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@ -343,6 +344,7 @@ static const struct regmap_config imx_gpc_regmap_config = {
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.rd_table = &access_table,
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.wr_table = &access_table,
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.max_register = 0x2ac,
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.fast_io = true,
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};
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static struct generic_pm_domain *imx_gpc_onecell_domains[] = {
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@ -14,6 +14,7 @@
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#include <linux/pm_domain.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/sizes.h>
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#include <dt-bindings/power/imx7-power.h>
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#include <dt-bindings/power/imx8mq-power.h>
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@ -25,7 +25,6 @@ enum imx_sc_rpc_svc {
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IMX_SC_RPC_SVC_PAD = 6,
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IMX_SC_RPC_SVC_MISC = 7,
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IMX_SC_RPC_SVC_IRQ = 8,
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IMX_SC_RPC_SVC_ABORT = 9
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};
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struct imx_sc_rpc_msg {
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