mirror of https://gitee.com/openkylin/linux.git
dmaengine: omap-dma: consolidate writes to DMA registers
There's no need to keep writing registers which don't change value in omap_dma_start_sg(). Move this into omap_dma_start_desc() and merge the register updates together. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -99,92 +99,17 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
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unsigned idx)
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{
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struct omap_sg *sg = d->sg + idx;
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uint32_t val;
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if (d->dir == DMA_DEV_TO_MEM) {
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if (dma_omap1()) {
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val = c->plat->dma_read(CSDP, c->dma_ch);
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val &= ~(0x1f << 9);
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val |= OMAP_DMA_PORT_EMIFF << 9;
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c->plat->dma_write(val, CSDP, c->dma_ch);
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}
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val = c->plat->dma_read(CCR, c->dma_ch);
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val &= ~(0x03 << 14);
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val |= OMAP_DMA_AMODE_POST_INC << 14;
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c->plat->dma_write(val, CCR, c->dma_ch);
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c->plat->dma_write(sg->addr, CDSA, c->dma_ch);
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c->plat->dma_write(0, CDEI, c->dma_ch);
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c->plat->dma_write(0, CDFI, c->dma_ch);
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} else {
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if (dma_omap1()) {
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val = c->plat->dma_read(CSDP, c->dma_ch);
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val &= ~(0x1f << 2);
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val |= OMAP_DMA_PORT_EMIFF << 2;
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c->plat->dma_write(val, CSDP, c->dma_ch);
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}
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val = c->plat->dma_read(CCR, c->dma_ch);
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val &= ~(0x03 << 12);
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val |= OMAP_DMA_AMODE_POST_INC << 12;
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c->plat->dma_write(val, CCR, c->dma_ch);
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c->plat->dma_write(sg->addr, CSSA, c->dma_ch);
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c->plat->dma_write(0, CSEI, c->dma_ch);
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c->plat->dma_write(0, CSFI, c->dma_ch);
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}
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val = c->plat->dma_read(CSDP, c->dma_ch);
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val &= ~0x03;
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val |= d->es;
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c->plat->dma_write(val, CSDP, c->dma_ch);
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if (dma_omap1()) {
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val = c->plat->dma_read(CCR, c->dma_ch);
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val &= ~(1 << 5);
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if (d->sync_mode == OMAP_DMA_SYNC_FRAME)
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val |= 1 << 5;
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c->plat->dma_write(val, CCR, c->dma_ch);
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val = c->plat->dma_read(CCR2, c->dma_ch);
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val &= ~(1 << 2);
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if (d->sync_mode == OMAP_DMA_SYNC_BLOCK)
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val |= 1 << 2;
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c->plat->dma_write(val, CCR2, c->dma_ch);
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} else if (c->dma_sig) {
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val = c->plat->dma_read(CCR, c->dma_ch);
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/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
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val &= ~((1 << 23) | (3 << 19) | 0x1f);
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val |= (c->dma_sig & ~0x1f) << 14;
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val |= c->dma_sig & 0x1f;
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if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
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val |= 1 << 5;
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else
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val &= ~(1 << 5);
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if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
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val |= 1 << 18;
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else
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val &= ~(1 << 18);
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switch (d->sync_type) {
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case OMAP_DMA_DST_SYNC_PREFETCH:
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val &= ~(1 << 24); /* dest synch */
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val |= 1 << 23; /* Prefetch */
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break;
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case 0:
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val &= ~(1 << 24); /* dest synch */
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break;
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default:
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val |= 1 << 24; /* source synch */
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break;
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}
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c->plat->dma_write(val, CCR, c->dma_ch);
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}
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c->plat->dma_write(sg->en, CEN, c->dma_ch);
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c->plat->dma_write(sg->fn, CFN, c->dma_ch);
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@ -210,13 +135,15 @@ static void omap_dma_start_desc(struct omap_chan *c)
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if (d->dir == DMA_DEV_TO_MEM) {
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if (dma_omap1()) {
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val = c->plat->dma_read(CSDP, c->dma_ch);
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val &= ~(0x1f << 2);
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val &= ~(0x1f << 9 | 0x1f << 2);
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val |= OMAP_DMA_PORT_EMIFF << 9;
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val |= d->periph_port << 2;
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c->plat->dma_write(val, CSDP, c->dma_ch);
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}
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val = c->plat->dma_read(CCR, c->dma_ch);
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val &= ~(0x03 << 12);
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val &= ~(0x03 << 14 | 0x03 << 12);
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val |= OMAP_DMA_AMODE_POST_INC << 14;
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val |= OMAP_DMA_AMODE_CONSTANT << 12;
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c->plat->dma_write(val, CCR, c->dma_ch);
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@ -226,14 +153,16 @@ static void omap_dma_start_desc(struct omap_chan *c)
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} else {
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if (dma_omap1()) {
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val = c->plat->dma_read(CSDP, c->dma_ch);
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val &= ~(0x1f << 9);
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val &= ~(0x1f << 9 | 0x1f << 2);
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val |= d->periph_port << 9;
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val |= OMAP_DMA_PORT_EMIFF << 2;
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c->plat->dma_write(val, CSDP, c->dma_ch);
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}
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val = c->plat->dma_read(CCR, c->dma_ch);
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val &= ~(0x03 << 14);
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val &= ~(0x03 << 12 | 0x03 << 14);
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val |= OMAP_DMA_AMODE_CONSTANT << 14;
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val |= OMAP_DMA_AMODE_POST_INC << 12;
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c->plat->dma_write(val, CCR, c->dma_ch);
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c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
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@ -241,6 +170,50 @@ static void omap_dma_start_desc(struct omap_chan *c)
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c->plat->dma_write(d->fi, CDFI, c->dma_ch);
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}
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val = c->plat->dma_read(CSDP, c->dma_ch);
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val &= ~0x03;
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val |= d->es;
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c->plat->dma_write(val, CSDP, c->dma_ch);
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if (dma_omap1()) {
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val = c->plat->dma_read(CCR, c->dma_ch);
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val &= ~(1 << 5);
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if (d->sync_mode == OMAP_DMA_SYNC_FRAME)
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val |= 1 << 5;
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c->plat->dma_write(val, CCR, c->dma_ch);
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val = c->plat->dma_read(CCR2, c->dma_ch);
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val &= ~(1 << 2);
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if (d->sync_mode == OMAP_DMA_SYNC_BLOCK)
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val |= 1 << 2;
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c->plat->dma_write(val, CCR2, c->dma_ch);
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} else if (c->dma_sig) {
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val = c->plat->dma_read(CCR, c->dma_ch);
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/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
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val &= ~(1 << 24 | 1 << 23 | 3 << 19 | 1 << 18 | 1 << 5 | 0x1f);
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val |= (c->dma_sig & ~0x1f) << 14;
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val |= c->dma_sig & 0x1f;
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if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
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val |= 1 << 5;
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if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
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val |= 1 << 18;
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switch (d->sync_type) {
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case OMAP_DMA_DST_SYNC_PREFETCH:/* dest synch */
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val |= 1 << 23; /* Prefetch */
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break;
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case 0:
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break;
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default:
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val |= 1 << 24; /* source synch */
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break;
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}
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c->plat->dma_write(val, CCR, c->dma_ch);
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}
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omap_dma_start_sg(c, d, 0);
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}
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