mirror of https://gitee.com/openkylin/linux.git
powerpc/perf: MMCR0 control for PMU registers under PMCC=00
PowerISA v3.1 introduces new control bit (PMCCEXT) for restricting access to group B PMU registers in problem state when MMCR0 PMCC=0b00. In problem state and when MMCR0 PMCC=0b00, setting the Monitor Mode Control Register bit 54 (MMCR0 PMCCEXT), will restrict read permission on Group B Performance Monitor Registers (SIER, SIAR, SDAR and MMCR1). When this bit is set to zero, group B registers will be readable. In other platforms (like power9), the older behaviour is retained where group B PMU SPRs are readable. Patch adds support for MMCR0 PMCCEXT bit in power10 by enabling this bit during boot and during the PMU event enable/disable callback functions. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1606409684-1589-8-git-send-email-atrajeev@linux.vnet.ibm.com
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9a8ee52634
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91668ab7db
arch/powerpc
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@ -864,6 +864,7 @@
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#define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */
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#define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */
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#define MMCR0_EBE 0x00100000UL /* Event based branch enable */
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#define MMCR0_EBE 0x00100000UL /* Event based branch enable */
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#define MMCR0_PMCC 0x000c0000UL /* PMC control */
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#define MMCR0_PMCC 0x000c0000UL /* PMC control */
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#define MMCR0_PMCCEXT ASM_CONST(0x00000200) /* PMCCEXT control */
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#define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
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#define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
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#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
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#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
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#define MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/
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#define MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/
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@ -123,6 +123,7 @@ static void init_PMU_ISA31(void)
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{
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{
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mtspr(SPRN_MMCR3, 0);
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mtspr(SPRN_MMCR3, 0);
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mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
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mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
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mtspr(SPRN_MMCR0, MMCR0_PMCCEXT);
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}
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}
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/*
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/*
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@ -454,6 +454,7 @@ static void init_pmu_power10(void)
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mtspr(SPRN_MMCR3, 0);
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mtspr(SPRN_MMCR3, 0);
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mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
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mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
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mtspr(SPRN_MMCR0, MMCR0_PMCCEXT);
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}
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}
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static int __init feat_enable_pmu_power10(struct dt_cpu_feature *f)
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static int __init feat_enable_pmu_power10(struct dt_cpu_feature *f)
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@ -95,6 +95,7 @@ static unsigned int freeze_events_kernel = MMCR0_FCS;
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#define SPRN_SIER3 0
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#define SPRN_SIER3 0
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#define MMCRA_SAMPLE_ENABLE 0
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#define MMCRA_SAMPLE_ENABLE 0
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#define MMCRA_BHRB_DISABLE 0
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#define MMCRA_BHRB_DISABLE 0
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#define MMCR0_PMCCEXT 0
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static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
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static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
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{
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{
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@ -1273,6 +1274,9 @@ static void power_pmu_disable(struct pmu *pmu)
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val |= MMCR0_FC;
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val |= MMCR0_FC;
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val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
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val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
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MMCR0_FC56);
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MMCR0_FC56);
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/* Set mmcr0 PMCCEXT for p10 */
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if (ppmu->flags & PPMU_ARCH_31)
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val |= MMCR0_PMCCEXT;
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/*
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/*
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* The barrier is to make sure the mtspr has been
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* The barrier is to make sure the mtspr has been
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@ -558,6 +558,14 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
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if (!(pmc_inuse & 0x60))
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if (!(pmc_inuse & 0x60))
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mmcr->mmcr0 |= MMCR0_FC56;
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mmcr->mmcr0 |= MMCR0_FC56;
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/*
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* Set mmcr0 (PMCCEXT) for p10 which
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* will restrict access to group B registers
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* when MMCR0 PMCC=0b00.
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*/
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if (cpu_has_feature(CPU_FTR_ARCH_31))
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mmcr->mmcr0 |= MMCR0_PMCCEXT;
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mmcr->mmcr1 = mmcr1;
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mmcr->mmcr1 = mmcr1;
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mmcr->mmcra = mmcra;
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mmcr->mmcra = mmcra;
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mmcr->mmcr2 = mmcr2;
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mmcr->mmcr2 = mmcr2;
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