mirror of https://gitee.com/openkylin/linux.git
[media] msi001: revise synthesizer calculation
Update synthesizer calculation to model I prefer nowadays. It is mostly just renaming some variables, but also minor functionality change how integer and fractional part are divided (using div_u64_rem()). Also, add 'schematic' of synthesizer following my current understanding. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
This commit is contained in:
Antti Palosaari
Mauro Carvalho Chehab
parent
e989a73ebd
commit
9195e5b246
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@ -91,15 +91,15 @@ static int msi001_set_gain(struct msi001 *s, int lna_gain, int mixer_gain,
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static int msi001_set_tuner(struct msi001 *s)
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{
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int ret, i;
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unsigned int n, m, thresh, frac, vco_step, tmp, f_if1;
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unsigned int uitmp, div_n, k, k_thresh, k_frac, div_lo, f_if1;
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u32 reg;
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u64 f_vco, tmp64;
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u8 mode, filter_mode, lo_div;
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u64 f_vco;
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u8 mode, filter_mode;
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static const struct {
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u32 rf;
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u8 mode;
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u8 lo_div;
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u8 div_lo;
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} band_lut[] = {
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{ 50000000, 0xe1, 16}, /* AM_MODE2, antenna 2 */
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{108000000, 0x42, 32}, /* VHF_MODE */
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@ -144,15 +144,15 @@ static int msi001_set_tuner(struct msi001 *s)
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*/
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unsigned int f_if = 0;
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#define F_REF 24000000
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#define R_REF 4
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#define F_OUT_STEP 1
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#define DIV_PRE_N 4
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#define F_VCO_STEP div_lo
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dev_dbg(&s->spi->dev, "f_rf=%d f_if=%d\n", f_rf, f_if);
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for (i = 0; i < ARRAY_SIZE(band_lut); i++) {
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if (f_rf <= band_lut[i].rf) {
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mode = band_lut[i].mode;
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lo_div = band_lut[i].lo_div;
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div_lo = band_lut[i].div_lo;
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break;
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}
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}
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@ -200,32 +200,46 @@ static int msi001_set_tuner(struct msi001 *s)
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dev_dbg(&s->spi->dev, "bandwidth selected=%d\n", bandwidth_lut[i].freq);
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f_vco = (u64) (f_rf + f_if + f_if1) * lo_div;
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tmp64 = f_vco;
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m = do_div(tmp64, F_REF * R_REF);
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n = (unsigned int) tmp64;
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/*
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* Fractional-N synthesizer
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*
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* +---------------------------------------+
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* v |
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* Fref +----+ +-------+ +----+ +------+ +---+
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* ------> | PD | --> | VCO | ------> | /4 | --> | /N.F | <-- | K |
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* +----+ +-------+ +----+ +------+ +---+
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* |
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* |
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* v
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* +-------+ Fout
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* | /Rout | ------>
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* +-------+
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*/
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vco_step = F_OUT_STEP * lo_div;
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thresh = (F_REF * R_REF) / vco_step;
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frac = 1ul * thresh * m / (F_REF * R_REF);
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/* Calculate PLL integer and fractional control word. */
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f_vco = (u64) (f_rf + f_if + f_if1) * div_lo;
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div_n = div_u64_rem(f_vco, DIV_PRE_N * F_REF, &k);
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k_thresh = (DIV_PRE_N * F_REF) / F_VCO_STEP;
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k_frac = div_u64((u64) k * k_thresh, (DIV_PRE_N * F_REF));
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/* Find out greatest common divisor and divide to smaller. */
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tmp = gcd(thresh, frac);
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thresh /= tmp;
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frac /= tmp;
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uitmp = gcd(k_thresh, k_frac);
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k_thresh /= uitmp;
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k_frac /= uitmp;
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/* Force divide to reg max. Resolution will be reduced. */
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tmp = DIV_ROUND_UP(thresh, 4095);
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thresh = DIV_ROUND_CLOSEST(thresh, tmp);
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frac = DIV_ROUND_CLOSEST(frac, tmp);
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uitmp = DIV_ROUND_UP(k_thresh, 4095);
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k_thresh = DIV_ROUND_CLOSEST(k_thresh, uitmp);
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k_frac = DIV_ROUND_CLOSEST(k_frac, uitmp);
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/* calc real RF set */
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tmp = 1ul * F_REF * R_REF * n;
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tmp += 1ul * F_REF * R_REF * frac / thresh;
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tmp /= lo_div;
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/* Calculate real RF set. */
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uitmp = (unsigned int) F_REF * DIV_PRE_N * div_n;
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uitmp += (unsigned int) F_REF * DIV_PRE_N * k_frac / k_thresh;
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uitmp /= div_lo;
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dev_dbg(&s->spi->dev, "rf=%u:%u n=%d thresh=%d frac=%d\n",
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f_rf, tmp, n, thresh, frac);
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dev_dbg(&s->spi->dev,
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"f_rf=%u:%u f_vco=%llu div_n=%u k_thresh=%u k_frac=%u div_lo=%u\n",
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f_rf, uitmp, f_vco, div_n, k_thresh, k_frac, div_lo);
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ret = msi001_wreg(s, 0x00000e);
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if (ret)
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@ -246,7 +260,7 @@ static int msi001_set_tuner(struct msi001 *s)
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goto err;
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reg = 5 << 0;
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reg |= thresh << 4;
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reg |= k_thresh << 4;
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reg |= 1 << 19;
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reg |= 1 << 21;
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ret = msi001_wreg(s, reg);
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@ -254,8 +268,8 @@ static int msi001_set_tuner(struct msi001 *s)
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goto err;
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reg = 2 << 0;
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reg |= frac << 4;
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reg |= n << 16;
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reg |= k_frac << 4;
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reg |= div_n << 16;
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ret = msi001_wreg(s, reg);
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if (ret)
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goto err;
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@ -276,7 +290,7 @@ static int msi001_set_tuner(struct msi001 *s)
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err:
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dev_dbg(&s->spi->dev, "failed %d\n", ret);
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return ret;
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};
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}
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static int msi001_s_power(struct v4l2_subdev *sd, int on)
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{
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