mirror of https://gitee.com/openkylin/linux.git
drm/i915: Change N divider minimum from 3 to 2 for gen2
Bruno Prémont has a 855 machine with a 1400x1050 LVDS screen. The VBT mode is as follows: 0:"1400x1050" 0 108000 1400 1416 1528 1688 1050 1051 1054 1066 0x8 0xa The BIOS uses the following DPLL settings: DPLL = 0x90020000 FP0 = 0x2140e FP1 = 0x21207 We can't generate that pixel clock currently as we're limiting the N divider to at least 3, whereas the BIOS uses a value of 2. Let's reduce the N minimum to 2 and see what happens. Cc: Bruno Prémont <bonbons@linux-vserver.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Bruno Prémont <bonbons@linux-vserver.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -91,7 +91,7 @@ intel_fdi_link_freq(struct drm_device *dev)
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static const intel_limit_t intel_limits_i8xx_dac = {
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.dot = { .min = 25000, .max = 350000 },
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.vco = { .min = 930000, .max = 1400000 },
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.n = { .min = 3, .max = 16 },
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.n = { .min = 2, .max = 16 },
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.m = { .min = 96, .max = 140 },
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.m1 = { .min = 18, .max = 26 },
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.m2 = { .min = 6, .max = 16 },
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@ -104,7 +104,7 @@ static const intel_limit_t intel_limits_i8xx_dac = {
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static const intel_limit_t intel_limits_i8xx_dvo = {
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.dot = { .min = 25000, .max = 350000 },
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.vco = { .min = 930000, .max = 1400000 },
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.n = { .min = 3, .max = 16 },
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.n = { .min = 2, .max = 16 },
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.m = { .min = 96, .max = 140 },
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.m1 = { .min = 18, .max = 26 },
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.m2 = { .min = 6, .max = 16 },
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@ -117,7 +117,7 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
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static const intel_limit_t intel_limits_i8xx_lvds = {
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.dot = { .min = 25000, .max = 350000 },
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.vco = { .min = 930000, .max = 1400000 },
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.n = { .min = 3, .max = 16 },
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.n = { .min = 2, .max = 16 },
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.m = { .min = 96, .max = 140 },
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.m1 = { .min = 18, .max = 26 },
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.m2 = { .min = 6, .max = 16 },
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