mirror of https://gitee.com/openkylin/linux.git
Merge branch 'omap4_and_sdrc_2.6.27' of git://git.pwsan.com/linux-2.6 into omap-for-linus
This commit is contained in:
Tony Lindgren
commit
91f6c90c8d
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -195,6 +195,42 @@
|
|||
#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
|
||||
#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
|
||||
|
||||
/* CM1.RESTORE_CM1 register offsets */
|
||||
#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
|
||||
#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)
|
||||
#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
|
||||
#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)
|
||||
#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
|
||||
#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)
|
||||
#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
|
||||
#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)
|
||||
#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
|
||||
#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)
|
||||
#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
|
||||
#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)
|
||||
#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
|
||||
#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)
|
||||
#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
|
||||
#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)
|
||||
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)
|
||||
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)
|
||||
#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)
|
||||
#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
|
||||
#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)
|
||||
#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
|
||||
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)
|
||||
#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
|
||||
#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)
|
||||
#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
|
||||
#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038)
|
||||
#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
|
||||
#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c)
|
||||
#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
|
||||
#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040)
|
||||
|
||||
/* CM2 */
|
||||
|
||||
/* CM2.OCP_SOCKET_CM2 register offsets */
|
||||
|
|
@ -252,8 +288,6 @@
|
|||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
|
||||
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
|
||||
#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET 0x0070
|
||||
#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)
|
||||
#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
|
||||
#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
|
||||
|
|
@ -296,6 +330,8 @@
|
|||
#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
|
||||
#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038
|
||||
#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
|
||||
#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040
|
||||
#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040)
|
||||
|
||||
/* CM2.CORE_CM2 register offsets */
|
||||
#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000
|
||||
|
|
@ -578,4 +614,54 @@
|
|||
#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
|
||||
#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
|
||||
#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
|
||||
|
||||
/* CM2.RESTORE_CM2 register offsets */
|
||||
#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
|
||||
#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)
|
||||
#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
|
||||
#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)
|
||||
#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
|
||||
#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)
|
||||
#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
|
||||
#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)
|
||||
#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
|
||||
#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)
|
||||
#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
|
||||
#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)
|
||||
#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
|
||||
#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)
|
||||
#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
|
||||
#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)
|
||||
#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
|
||||
#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)
|
||||
#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
|
||||
#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)
|
||||
#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
|
||||
#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)
|
||||
#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
|
||||
#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)
|
||||
#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
|
||||
#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)
|
||||
#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
|
||||
#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)
|
||||
#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
|
||||
#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)
|
||||
#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
|
||||
#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)
|
||||
#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
|
||||
#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)
|
||||
#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
|
||||
#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044)
|
||||
#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
|
||||
#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048)
|
||||
#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
|
||||
#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c)
|
||||
#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
|
||||
#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050)
|
||||
#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
|
||||
#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054)
|
||||
#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
|
||||
#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058)
|
||||
#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
|
||||
#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include "sdrc.h"
|
||||
|
||||
static void __iomem *omap2_ctrl_base;
|
||||
static void __iomem *omap4_ctrl_pad_base;
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
|
||||
struct omap3_scratchpad {
|
||||
|
|
@ -137,6 +138,7 @@ static struct omap3_control_regs control_context;
|
|||
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
|
||||
|
||||
#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
|
||||
#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg))
|
||||
|
||||
void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
|
||||
{
|
||||
|
|
@ -145,6 +147,12 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
|
|||
omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
|
||||
WARN_ON(!omap2_ctrl_base);
|
||||
}
|
||||
|
||||
/* Static mapping, never released */
|
||||
if (omap2_globals->ctrl_pad) {
|
||||
omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
|
||||
WARN_ON(!omap4_ctrl_pad_base);
|
||||
}
|
||||
}
|
||||
|
||||
void __iomem *omap_ctrl_base_get(void)
|
||||
|
|
@ -182,6 +190,23 @@ void omap_ctrl_writel(u32 val, u16 offset)
|
|||
__raw_writel(val, OMAP_CTRL_REGADDR(offset));
|
||||
}
|
||||
|
||||
/*
|
||||
* On OMAP4 control pad are not addressable from control
|
||||
* core base. So the common omap_ctrl_read/write APIs breaks
|
||||
* Hence export separate APIs to manage the omap4 pad control
|
||||
* registers. This APIs will work only for OMAP4
|
||||
*/
|
||||
|
||||
u32 omap4_ctrl_pad_readl(u16 offset)
|
||||
{
|
||||
return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
|
||||
}
|
||||
|
||||
void omap4_ctrl_pad_writel(u32 val, u16 offset)
|
||||
{
|
||||
__raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
|
||||
/*
|
||||
* Clears the scratchpad contents in case of cold boot-
|
||||
|
|
|
|||
|
|
@ -135,10 +135,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
|
|||
*
|
||||
* FIXME handle VMMC1A as needed ...
|
||||
*/
|
||||
reg = omap_ctrl_readl(control_pbias_offset);
|
||||
reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ);
|
||||
omap_ctrl_writel(reg, control_pbias_offset);
|
||||
reg = omap4_ctrl_pad_readl(control_pbias_offset);
|
||||
reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
|
||||
static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
|
||||
|
|
@ -147,30 +148,33 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
|
|||
u32 reg;
|
||||
|
||||
if (power_on) {
|
||||
reg = omap_ctrl_readl(control_pbias_offset);
|
||||
reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ;
|
||||
reg = omap4_ctrl_pad_readl(control_pbias_offset);
|
||||
reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
|
||||
if ((1 << vdd) <= MMC_VDD_165_195)
|
||||
reg &= ~OMAP4_MMC1_PBIASLITE_VMODE;
|
||||
reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
|
||||
else
|
||||
reg |= OMAP4_MMC1_PBIASLITE_VMODE;
|
||||
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ);
|
||||
omap_ctrl_writel(reg, control_pbias_offset);
|
||||
reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
|
||||
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
/* 4 microsec delay for comparator to generate an error*/
|
||||
udelay(4);
|
||||
reg = omap_ctrl_readl(control_pbias_offset);
|
||||
if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) {
|
||||
reg = omap4_ctrl_pad_readl(control_pbias_offset);
|
||||
if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
|
||||
pr_err("Pbias Voltage is not same as LDO\n");
|
||||
/* Caution : On VMODE_ERROR Power Down MMC IO */
|
||||
reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ);
|
||||
omap_ctrl_writel(reg, control_pbias_offset);
|
||||
reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
} else {
|
||||
reg = omap_ctrl_readl(control_pbias_offset);
|
||||
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ |
|
||||
OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ);
|
||||
omap_ctrl_writel(reg, control_pbias_offset);
|
||||
reg = omap4_ctrl_pad_readl(control_pbias_offset);
|
||||
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PBIASLITE_VMODE_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -218,17 +222,18 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
|
|||
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
|
||||
}
|
||||
} else {
|
||||
control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE;
|
||||
control_mmc1 = OMAP44XX_CONTROL_MMC1;
|
||||
reg = omap_ctrl_readl(control_mmc1);
|
||||
reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 |
|
||||
OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1);
|
||||
reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 |
|
||||
OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3);
|
||||
reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL |
|
||||
OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL |
|
||||
OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL);
|
||||
omap_ctrl_writel(reg, control_mmc1);
|
||||
control_pbias_offset =
|
||||
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
|
||||
control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
|
||||
reg = omap4_ctrl_pad_readl(control_mmc1);
|
||||
reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
|
||||
OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
|
||||
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
|
||||
OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
|
||||
reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
|
||||
OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
|
||||
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_mmc1);
|
||||
}
|
||||
|
||||
for (c = controllers; c->mmc; c++) {
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ int omap_type(void)
|
|||
} else if (cpu_is_omap34xx()) {
|
||||
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
|
||||
} else if (cpu_is_omap44xx()) {
|
||||
val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
|
||||
val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
|
||||
} else {
|
||||
pr_err("Cannot detect omap type!\n");
|
||||
goto out;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,391 @@
|
|||
/*
|
||||
* OMAP44xx CTRL_MODULE_CORE registers and bitfields
|
||||
*
|
||||
* Copyright (C) 2009-2010 Texas Instruments, Inc.
|
||||
*
|
||||
* Benoit Cousson (b-cousson@ti.com)
|
||||
* Santosh Shilimkar (santosh.shilimkar@ti.com)
|
||||
*
|
||||
* This file is automatically generated from the OMAP hardware databases.
|
||||
* We respectfully ask that any modifications to this file be coordinated
|
||||
* with the public linux-omap@vger.kernel.org mailing list and the
|
||||
* authors above to ensure that the autogeneration scripts are kept
|
||||
* up-to-date with the file contents.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
|
||||
|
||||
|
||||
/* Base address */
|
||||
#define OMAP4_CTRL_MODULE_CORE 0x4a002000
|
||||
|
||||
/* Registers offset */
|
||||
#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
|
||||
#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
|
||||
#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
|
||||
#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
|
||||
#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
|
||||
#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
|
||||
#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
|
||||
#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
|
||||
#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
|
||||
#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
|
||||
#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
|
||||
#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
|
||||
#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
|
||||
#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
|
||||
#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
|
||||
#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
|
||||
#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
|
||||
#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
|
||||
#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
|
||||
|
||||
/* Registers shifts and masks */
|
||||
|
||||
/* IP_REVISION */
|
||||
#define OMAP4_IP_REV_SCHEME_SHIFT 30
|
||||
#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
|
||||
#define OMAP4_IP_REV_FUNC_SHIFT 16
|
||||
#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
|
||||
#define OMAP4_IP_REV_RTL_SHIFT 11
|
||||
#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
|
||||
#define OMAP4_IP_REV_MAJOR_SHIFT 8
|
||||
#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
|
||||
#define OMAP4_IP_REV_CUSTOM_SHIFT 6
|
||||
#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
|
||||
#define OMAP4_IP_REV_MINOR_SHIFT 0
|
||||
#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
|
||||
|
||||
/* IP_HWINFO */
|
||||
#define OMAP4_IP_HWINFO_SHIFT 0
|
||||
#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
|
||||
|
||||
/* IP_SYSCONFIG */
|
||||
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
|
||||
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
|
||||
|
||||
/* STD_FUSE_DIE_ID_0 */
|
||||
#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
|
||||
|
||||
/* ID_CODE */
|
||||
#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_DIE_ID_1 */
|
||||
#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_DIE_ID_2 */
|
||||
#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_DIE_ID_3 */
|
||||
#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_PROD_ID_0 */
|
||||
#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_PROD_ID_1 */
|
||||
#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_USB_CONF */
|
||||
#define OMAP4_USB_PROD_ID_SHIFT 16
|
||||
#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
|
||||
#define OMAP4_USB_VENDOR_ID_SHIFT 0
|
||||
#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
|
||||
|
||||
/* STD_FUSE_OPP_VDD_WKUP */
|
||||
#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_OPP_BGAP */
|
||||
#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_OPP_DPLL_0 */
|
||||
#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_OPP_DPLL_1 */
|
||||
#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
|
||||
|
||||
/* STATUS */
|
||||
#define OMAP4_ATTILA_CONF_SHIFT 11
|
||||
#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
|
||||
#define OMAP4_DEVICE_TYPE_SHIFT 8
|
||||
#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
|
||||
#define OMAP4_SYS_BOOT_SHIFT 0
|
||||
#define OMAP4_SYS_BOOT_MASK (0xff << 0)
|
||||
|
||||
/* DEV_CONF */
|
||||
#define OMAP4_DEV_CONF_SHIFT 1
|
||||
#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
|
||||
#define OMAP4_USBPHY_PD_SHIFT 0
|
||||
#define OMAP4_USBPHY_PD_MASK (1 << 0)
|
||||
|
||||
/* LDOVBB_IVA_VOLTAGE_CTRL */
|
||||
#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
|
||||
#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
|
||||
#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
|
||||
#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
|
||||
#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
|
||||
#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
|
||||
#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
|
||||
#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
|
||||
#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
|
||||
#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
|
||||
#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
|
||||
#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
|
||||
|
||||
/* LDOVBB_MPU_VOLTAGE_CTRL */
|
||||
#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
|
||||
#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
|
||||
#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
|
||||
#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
|
||||
#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
|
||||
#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
|
||||
#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
|
||||
#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
|
||||
#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
|
||||
#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
|
||||
#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
|
||||
#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
|
||||
|
||||
/* LDOSRAM_IVA_VOLTAGE_CTRL */
|
||||
#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
|
||||
#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
|
||||
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
|
||||
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
|
||||
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
|
||||
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
|
||||
#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
|
||||
#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
|
||||
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
|
||||
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
|
||||
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
|
||||
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
|
||||
|
||||
/* LDOSRAM_MPU_VOLTAGE_CTRL */
|
||||
#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
|
||||
#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
|
||||
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
|
||||
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
|
||||
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
|
||||
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
|
||||
|
||||
/* LDOSRAM_CORE_VOLTAGE_CTRL */
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
|
||||
|
||||
/* TEMP_SENSOR */
|
||||
#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
|
||||
#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
|
||||
#define OMAP4_BGAP_TSHUT_SHIFT 11
|
||||
#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
|
||||
|
||||
/* DPLL_NWELL_TRIM_0 */
|
||||
#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
|
||||
#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
|
||||
#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
|
||||
#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
|
||||
#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
|
||||
#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
|
||||
#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
|
||||
#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
|
||||
#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
|
||||
#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
|
||||
#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
|
||||
#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
|
||||
#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
|
||||
#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
|
||||
#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
|
||||
#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
|
||||
#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
|
||||
#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
|
||||
#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
|
||||
#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
|
||||
|
||||
/* DPLL_NWELL_TRIM_1 */
|
||||
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
|
||||
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
|
||||
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
|
||||
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
|
||||
#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
|
||||
#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
|
||||
#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
|
||||
#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
|
||||
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
|
||||
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
|
||||
#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
|
||||
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
|
||||
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
|
||||
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
|
||||
#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
|
||||
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
|
||||
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
|
||||
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
|
||||
#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
|
||||
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
|
||||
|
||||
/* USBOTGHS_CONTROL */
|
||||
#define OMAP4_DISCHRGVBUS_SHIFT 8
|
||||
#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
|
||||
#define OMAP4_CHRGVBUS_SHIFT 7
|
||||
#define OMAP4_CHRGVBUS_MASK (1 << 7)
|
||||
#define OMAP4_DRVVBUS_SHIFT 6
|
||||
#define OMAP4_DRVVBUS_MASK (1 << 6)
|
||||
#define OMAP4_IDPULLUP_SHIFT 5
|
||||
#define OMAP4_IDPULLUP_MASK (1 << 5)
|
||||
#define OMAP4_IDDIG_SHIFT 4
|
||||
#define OMAP4_IDDIG_MASK (1 << 4)
|
||||
#define OMAP4_SESSEND_SHIFT 3
|
||||
#define OMAP4_SESSEND_MASK (1 << 3)
|
||||
#define OMAP4_VBUSVALID_SHIFT 2
|
||||
#define OMAP4_VBUSVALID_MASK (1 << 2)
|
||||
#define OMAP4_BVALID_SHIFT 1
|
||||
#define OMAP4_BVALID_MASK (1 << 1)
|
||||
#define OMAP4_AVALID_SHIFT 0
|
||||
#define OMAP4_AVALID_MASK (1 << 0)
|
||||
|
||||
/* DSS_CONTROL */
|
||||
#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
|
||||
#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
|
||||
|
||||
/* HWOBS_CONTROL */
|
||||
#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
|
||||
#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
|
||||
#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
|
||||
#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
|
||||
#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
|
||||
#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
|
||||
#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
|
||||
#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
|
||||
|
||||
/* DEBOBS_FINAL_MUX_SEL */
|
||||
#define OMAP4_SELECT_SHIFT 0
|
||||
#define OMAP4_SELECT_MASK (0xffffffff << 0)
|
||||
|
||||
/* DEBOBS_MMR_MPU */
|
||||
#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
|
||||
#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
|
||||
|
||||
/* CONF_SDMA_REQ_SEL0 */
|
||||
#define OMAP4_MULT_SHIFT 0
|
||||
#define OMAP4_MULT_MASK (0x7f << 0)
|
||||
|
||||
/* CONF_CLK_SEL0 */
|
||||
#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_CLK_SEL1 */
|
||||
#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_CLK_SEL2 */
|
||||
#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_DPLL_FREQLOCK_SEL */
|
||||
#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_DPLL_TINITZ_SEL */
|
||||
#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_DPLL_PHASELOCK_SEL */
|
||||
#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_DEBUG_SEL_TST_0 */
|
||||
#define OMAP4_MODE_SHIFT 0
|
||||
#define OMAP4_MODE_MASK (0xf << 0)
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
|
||||
*
|
||||
* Copyright (C) 2009-2010 Texas Instruments, Inc.
|
||||
*
|
||||
* Benoit Cousson (b-cousson@ti.com)
|
||||
* Santosh Shilimkar (santosh.shilimkar@ti.com)
|
||||
*
|
||||
* This file is automatically generated from the OMAP hardware databases.
|
||||
* We respectfully ask that any modifications to this file be coordinated
|
||||
* with the public linux-omap@vger.kernel.org mailing list and the
|
||||
* authors above to ensure that the autogeneration scripts are kept
|
||||
* up-to-date with the file contents.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
|
||||
|
||||
|
||||
/* Base address */
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
|
||||
|
||||
/* Registers offset */
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c
|
||||
|
||||
/* Registers shifts and masks */
|
||||
|
||||
/* IP_REVISION */
|
||||
#define OMAP4_IP_REV_SCHEME_SHIFT 30
|
||||
#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
|
||||
#define OMAP4_IP_REV_FUNC_SHIFT 16
|
||||
#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
|
||||
#define OMAP4_IP_REV_RTL_SHIFT 11
|
||||
#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
|
||||
#define OMAP4_IP_REV_MAJOR_SHIFT 8
|
||||
#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
|
||||
#define OMAP4_IP_REV_CUSTOM_SHIFT 6
|
||||
#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
|
||||
#define OMAP4_IP_REV_MINOR_SHIFT 0
|
||||
#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
|
||||
|
||||
/* IP_HWINFO */
|
||||
#define OMAP4_IP_HWINFO_SHIFT 0
|
||||
#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
|
||||
|
||||
/* IP_SYSCONFIG */
|
||||
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
|
||||
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
|
||||
|
||||
/* PADCONF_WAKEUPEVENT_0 */
|
||||
#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24
|
||||
#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
|
||||
#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23
|
||||
#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
|
||||
#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22
|
||||
#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
|
||||
#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21
|
||||
#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
|
||||
#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20
|
||||
#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
|
||||
#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19
|
||||
#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
|
||||
#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18
|
||||
#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
|
||||
#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17
|
||||
#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
|
||||
#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16
|
||||
#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
|
||||
#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15
|
||||
#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
|
||||
#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14
|
||||
#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
|
||||
#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13
|
||||
#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
|
||||
#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12
|
||||
#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
|
||||
#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11
|
||||
#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
|
||||
#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
|
||||
#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
|
||||
#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9
|
||||
#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
|
||||
#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8
|
||||
#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
|
||||
#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7
|
||||
#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
|
||||
#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6
|
||||
#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
|
||||
#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5
|
||||
#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
|
||||
#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4
|
||||
#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
|
||||
#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3
|
||||
#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
|
||||
#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2
|
||||
#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
|
||||
#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
|
||||
#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
|
||||
#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0
|
||||
#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
|
||||
|
||||
/* CONTROL_SMART1NOPMIO_PADCONF_0 */
|
||||
#define OMAP4_FREF_DR0_SC_SHIFT 30
|
||||
#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30)
|
||||
#define OMAP4_FREF_DR1_SC_SHIFT 28
|
||||
#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28)
|
||||
#define OMAP4_FREF_DR4_SC_SHIFT 26
|
||||
#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26)
|
||||
#define OMAP4_FREF_DR5_SC_SHIFT 24
|
||||
#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24)
|
||||
#define OMAP4_FREF_DR6_SC_SHIFT 22
|
||||
#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22)
|
||||
#define OMAP4_FREF_DR7_SC_SHIFT 20
|
||||
#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20)
|
||||
#define OMAP4_GPIO_DR7_SC_SHIFT 18
|
||||
#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18)
|
||||
#define OMAP4_DPM_DR0_SC_SHIFT 14
|
||||
#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14)
|
||||
#define OMAP4_SIM_DR0_SC_SHIFT 12
|
||||
#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12)
|
||||
|
||||
/* CONTROL_SMART1NOPMIO_PADCONF_1 */
|
||||
#define OMAP4_FREF_DR0_LB_SHIFT 30
|
||||
#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30)
|
||||
#define OMAP4_FREF_DR1_LB_SHIFT 28
|
||||
#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28)
|
||||
#define OMAP4_FREF_DR4_LB_SHIFT 26
|
||||
#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26)
|
||||
#define OMAP4_FREF_DR5_LB_SHIFT 24
|
||||
#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24)
|
||||
#define OMAP4_FREF_DR6_LB_SHIFT 22
|
||||
#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22)
|
||||
#define OMAP4_FREF_DR7_LB_SHIFT 20
|
||||
#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20)
|
||||
#define OMAP4_GPIO_DR7_LB_SHIFT 18
|
||||
#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18)
|
||||
#define OMAP4_DPM_DR0_LB_SHIFT 14
|
||||
#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14)
|
||||
#define OMAP4_SIM_DR0_LB_SHIFT 12
|
||||
#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12)
|
||||
|
||||
/* CONTROL_PADCONF_MODE */
|
||||
#define OMAP4_VDDS_DV_FREF_SHIFT 31
|
||||
#define OMAP4_VDDS_DV_FREF_MASK (1 << 31)
|
||||
#define OMAP4_VDDS_DV_BANK2_SHIFT 30
|
||||
#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30)
|
||||
|
||||
/* CONTROL_XTAL_OSCILLATOR */
|
||||
#define OMAP4_OSCILLATOR_BOOST_SHIFT 31
|
||||
#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31)
|
||||
#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30
|
||||
#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30)
|
||||
|
||||
/* CONTROL_USIMIO */
|
||||
#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31
|
||||
#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31)
|
||||
#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29
|
||||
#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29)
|
||||
#define OMAP4_USIM_PWRDNZ_SHIFT 28
|
||||
#define OMAP4_USIM_PWRDNZ_MASK (1 << 28)
|
||||
|
||||
/* CONTROL_I2C_2 */
|
||||
#define OMAP4_SR_SDA_GLFENB_SHIFT 31
|
||||
#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31)
|
||||
#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29
|
||||
#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29)
|
||||
#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28
|
||||
#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28)
|
||||
#define OMAP4_SR_SCL_GLFENB_SHIFT 27
|
||||
#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27)
|
||||
#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25
|
||||
#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25)
|
||||
#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24
|
||||
#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24)
|
||||
|
||||
/* CONTROL_JTAG */
|
||||
#define OMAP4_JTAG_NTRST_EN_SHIFT 31
|
||||
#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31)
|
||||
#define OMAP4_JTAG_TCK_EN_SHIFT 30
|
||||
#define OMAP4_JTAG_TCK_EN_MASK (1 << 30)
|
||||
#define OMAP4_JTAG_RTCK_EN_SHIFT 29
|
||||
#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29)
|
||||
#define OMAP4_JTAG_TDI_EN_SHIFT 28
|
||||
#define OMAP4_JTAG_TDI_EN_MASK (1 << 28)
|
||||
#define OMAP4_JTAG_TDO_EN_SHIFT 27
|
||||
#define OMAP4_JTAG_TDO_EN_MASK (1 << 27)
|
||||
|
||||
/* CONTROL_SYS */
|
||||
#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31
|
||||
#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31)
|
||||
|
||||
/* WKUP_CONTROL_SPARE_RW */
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
|
||||
|
||||
/* WKUP_CONTROL_SPARE_R */
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0)
|
||||
|
||||
/* WKUP_CONTROL_SPARE_R_C0 */
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* OMAP44xx CTRL_MODULE_WKUP registers and bitfields
|
||||
*
|
||||
* Copyright (C) 2009-2010 Texas Instruments, Inc.
|
||||
*
|
||||
* Benoit Cousson (b-cousson@ti.com)
|
||||
* Santosh Shilimkar (santosh.shilimkar@ti.com)
|
||||
*
|
||||
* This file is automatically generated from the OMAP hardware databases.
|
||||
* We respectfully ask that any modifications to this file be coordinated
|
||||
* with the public linux-omap@vger.kernel.org mailing list and the
|
||||
* authors above to ensure that the autogeneration scripts are kept
|
||||
* up-to-date with the file contents.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
|
||||
|
||||
|
||||
/* Base address */
|
||||
#define OMAP4_CTRL_MODULE_WKUP 0x4a30c000
|
||||
|
||||
/* Registers offset */
|
||||
#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000
|
||||
#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004
|
||||
#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8
|
||||
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc
|
||||
|
||||
/* Registers shifts and masks */
|
||||
|
||||
/* IP_REVISION */
|
||||
#define OMAP4_IP_REV_SCHEME_SHIFT 30
|
||||
#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
|
||||
#define OMAP4_IP_REV_FUNC_SHIFT 16
|
||||
#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
|
||||
#define OMAP4_IP_REV_RTL_SHIFT 11
|
||||
#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
|
||||
#define OMAP4_IP_REV_MAJOR_SHIFT 8
|
||||
#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
|
||||
#define OMAP4_IP_REV_CUSTOM_SHIFT 6
|
||||
#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
|
||||
#define OMAP4_IP_REV_MINOR_SHIFT 0
|
||||
#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
|
||||
|
||||
/* IP_HWINFO */
|
||||
#define OMAP4_IP_HWINFO_SHIFT 0
|
||||
#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
|
||||
|
||||
/* IP_SYSCONFIG */
|
||||
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
|
||||
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
|
||||
|
||||
/* CONF_DEBUG_SEL_TST_0 */
|
||||
#define OMAP4_WKUP_MODE_SHIFT 0
|
||||
#define OMAP4_WKUP_MODE_MASK (1 << 0)
|
||||
|
||||
#endif
|
||||
|
|
@ -98,7 +98,7 @@ static struct powerdomain dss_44xx_pwrdm = {
|
|||
.prcm_offs = OMAP4430_PRM_DSS_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRDM_POWER_OFF, /* dss_mem */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -44,14 +44,12 @@
|
|||
#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
|
||||
#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038
|
||||
#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
|
||||
#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
|
||||
#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
|
||||
#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
|
||||
#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
|
||||
|
||||
/* PRM.CKGEN_PRM register offsets */
|
||||
#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000
|
||||
#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
|
||||
#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET 0x0004
|
||||
#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004)
|
||||
#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008
|
||||
#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
|
||||
#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c
|
||||
|
|
@ -686,8 +684,8 @@
|
|||
#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
|
||||
#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc
|
||||
#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
|
||||
#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET 0x00e0
|
||||
#define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
|
||||
#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0
|
||||
#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
|
||||
#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4
|
||||
#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
|
||||
#define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8
|
||||
|
|
@ -698,6 +696,8 @@
|
|||
#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
|
||||
#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
|
||||
#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
|
||||
#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
|
||||
#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8)
|
||||
|
||||
/*
|
||||
* PRCM_MPU
|
||||
|
|
@ -715,6 +715,8 @@
|
|||
/* PRCM_MPU.DEVICE_PRM register offsets */
|
||||
#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
|
||||
#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
|
||||
#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
|
||||
#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004)
|
||||
|
||||
/* PRCM_MPU.CPU0 register offsets */
|
||||
#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
|
||||
|
|
|
|||
|
|
@ -129,8 +129,11 @@ ENTRY(omap3_sram_configure_core_dpll)
|
|||
ldr r4, [sp, #80]
|
||||
str r4, omap_sdrc_mr_1_val
|
||||
skip_cs1_params:
|
||||
mrc p15, 0, r8, c1, c0, 0 @ read ctrl register
|
||||
bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction
|
||||
mcr p15, 0, r10, c1, c0, 0 @ write ctrl register
|
||||
dsb @ flush buffered writes to interconnect
|
||||
|
||||
isb @ prevent speculative exec past here
|
||||
cmp r3, #1 @ if increasing SDRC clk rate,
|
||||
bleq configure_sdrc @ program the SDRC regs early (for RFR)
|
||||
cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
|
||||
|
|
@ -148,6 +151,7 @@ skip_cs1_params:
|
|||
beq return_to_sdram @ return to SDRAM code, otherwise,
|
||||
bl configure_sdrc @ reprogram SDRC regs now
|
||||
return_to_sdram:
|
||||
mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register
|
||||
isb @ prevent speculative exec past here
|
||||
mov r0, #0 @ return value
|
||||
ldmfd sp!, {r1-r12, pc} @ restore regs and return
|
||||
|
|
|
|||
|
|
@ -336,7 +336,8 @@ void __init omap3_map_io(void)
|
|||
static struct omap_globals omap4_globals = {
|
||||
.class = OMAP443X_CLASS,
|
||||
.tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
|
||||
.ctrl = OMAP443X_CTRL_BASE,
|
||||
.ctrl = OMAP443X_SCM_BASE,
|
||||
.ctrl_pad = OMAP443X_CTRL_BASE,
|
||||
.prm = OMAP4430_PRM_BASE,
|
||||
.cm = OMAP4430_CM_BASE,
|
||||
.cm2 = OMAP4430_CM2_BASE,
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ struct omap_globals {
|
|||
unsigned long sdrc; /* SDRAM Controller */
|
||||
unsigned long sms; /* SDRAM Memory Scheduler */
|
||||
unsigned long ctrl; /* System Control Module */
|
||||
unsigned long ctrl_pad; /* PAD Control Module */
|
||||
unsigned long prm; /* Power and Reset Management */
|
||||
unsigned long cm; /* Clock Management */
|
||||
unsigned long cm2;
|
||||
|
|
|
|||
|
|
@ -17,6 +17,10 @@
|
|||
#define __ASM_ARCH_CONTROL_H
|
||||
|
||||
#include <mach/io.h>
|
||||
#include <mach/ctrl_module_core_44xx.h>
|
||||
#include <mach/ctrl_module_wkup_44xx.h>
|
||||
#include <mach/ctrl_module_pad_core_44xx.h>
|
||||
#include <mach/ctrl_module_pad_wkup_44xx.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define OMAP242X_CTRL_REGADDR(reg) \
|
||||
|
|
@ -204,12 +208,6 @@
|
|||
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
|
||||
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
|
||||
|
||||
/* 44xx control status register offset */
|
||||
#define OMAP44XX_CONTROL_STATUS 0x2c4
|
||||
|
||||
/* 44xx-only CONTROL_GENERAL register offsets */
|
||||
#define OMAP44XX_CONTROL_MMC1 0x628
|
||||
#define OMAP44XX_CONTROL_PBIAS_LITE 0x600
|
||||
/*
|
||||
* REVISIT: This list of registers is not comprehensive - there are more
|
||||
* that should be added.
|
||||
|
|
@ -255,23 +253,6 @@
|
|||
#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
|
||||
#define OMAP2_PBIASLITEVMODE0 (1 << 0)
|
||||
|
||||
/* CONTROL_PBIAS_LITE bits for OMAP4 */
|
||||
#define OMAP4_MMC1_PWRDNZ (1 << 26)
|
||||
#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25)
|
||||
#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24)
|
||||
#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23)
|
||||
#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22)
|
||||
#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21)
|
||||
#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20)
|
||||
|
||||
#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31)
|
||||
#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30)
|
||||
#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29)
|
||||
#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28)
|
||||
#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27)
|
||||
#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26)
|
||||
#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25)
|
||||
|
||||
/* CONTROL_PROG_IO1 bits */
|
||||
#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
|
||||
|
||||
|
|
@ -354,9 +335,11 @@ extern void __iomem *omap_ctrl_base_get(void);
|
|||
extern u8 omap_ctrl_readb(u16 offset);
|
||||
extern u16 omap_ctrl_readw(u16 offset);
|
||||
extern u32 omap_ctrl_readl(u16 offset);
|
||||
extern u32 omap4_ctrl_pad_readl(u16 offset);
|
||||
extern void omap_ctrl_writeb(u8 val, u16 offset);
|
||||
extern void omap_ctrl_writew(u16 val, u16 offset);
|
||||
extern void omap_ctrl_writel(u32 val, u16 offset);
|
||||
extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
|
||||
|
||||
extern void omap3_save_scratchpad_contents(void);
|
||||
extern void omap3_clear_scratchpad_contents(void);
|
||||
|
|
@ -371,9 +354,11 @@ extern void omap3_control_restore_context(void);
|
|||
#define omap_ctrl_readb(x) 0
|
||||
#define omap_ctrl_readw(x) 0
|
||||
#define omap_ctrl_readl(x) 0
|
||||
#define omap4_ctrl_pad_readl(x) 0
|
||||
#define omap_ctrl_writeb(x, y) WARN_ON(1)
|
||||
#define omap_ctrl_writew(x, y) WARN_ON(1)
|
||||
#define omap_ctrl_writel(x, y) WARN_ON(1)
|
||||
#define omap4_ctrl_pad_writel(x, y) WARN_ON(1)
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
|
||||
/* Powerdomain allowable state bitfields */
|
||||
#define PWRSTS_ON (1 << PWRDM_POWER_ON)
|
||||
#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
|
||||
#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
|
||||
(1 << PWRDM_POWER_ON))
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue