mirror of https://gitee.com/openkylin/linux.git
dmaengine: dw: keep copy of custom slave config in dwc
It seems we need to extend custom slave configuration by one more member to support Intel Quart UART. It becomes a burden to manage all members of struct dw_dma_slave one-by-one. Replace the set of fields by embedding struct dw_dma_slave into struct dw_dma_chan. Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -46,9 +46,9 @@
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u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
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DW_DMA_MSIZE_16; \
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u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ? \
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_dwc->p_master : _dwc->m_master; \
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_dwc->dws.p_master : _dwc->dws.m_master; \
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u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ? \
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_dwc->p_master : _dwc->m_master; \
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_dwc->dws.p_master : _dwc->dws.m_master; \
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\
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(DWC_CTLL_DST_MSIZE(_dmsize) \
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| DWC_CTLL_SRC_MSIZE(_smsize) \
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@ -147,8 +147,8 @@ static void dwc_initialize(struct dw_dma_chan *dwc)
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if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags))
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return;
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cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
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cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
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cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
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cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
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channel_writel(dwc, CFG_LO, cfglo);
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channel_writel(dwc, CFG_HI, cfghi);
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@ -209,7 +209,7 @@ static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
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static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
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{
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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u8 lms = DWC_LLP_LMS(dwc->m_master);
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u8 lms = DWC_LLP_LMS(dwc->dws.m_master);
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unsigned long was_soft_llp;
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/* ASSERT: channel is idle */
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@ -662,7 +662,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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struct dw_desc *prev;
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size_t xfer_count;
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size_t offset;
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u8 m_master = dwc->m_master;
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u8 m_master = dwc->dws.m_master;
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unsigned int src_width;
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unsigned int dst_width;
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unsigned int data_width = dw->pdata->data_width[m_master];
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@ -740,7 +740,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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struct dw_desc *prev;
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struct dw_desc *first;
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u32 ctllo;
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u8 m_master = dwc->m_master;
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u8 m_master = dwc->dws.m_master;
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u8 lms = DWC_LLP_LMS(m_master);
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dma_addr_t reg;
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unsigned int reg_width;
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@ -895,12 +895,7 @@ bool dw_dma_filter(struct dma_chan *chan, void *param)
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return false;
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/* We have to copy data since dws can be temporary storage */
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dwc->src_id = dws->src_id;
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dwc->dst_id = dws->dst_id;
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dwc->m_master = dws->m_master;
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dwc->p_master = dws->p_master;
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memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave));
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return true;
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}
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@ -1167,11 +1162,7 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
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spin_lock_irqsave(&dwc->lock, flags);
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/* Clear custom channel configuration */
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dwc->src_id = 0;
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dwc->dst_id = 0;
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dwc->m_master = 0;
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dwc->p_master = 0;
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memset(&dwc->dws, 0, sizeof(struct dw_dma_slave));
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clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags);
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@ -1264,7 +1255,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
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struct dw_cyclic_desc *retval = NULL;
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struct dw_desc *desc;
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struct dw_desc *last = NULL;
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u8 lms = DWC_LLP_LMS(dwc->m_master);
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u8 lms = DWC_LLP_LMS(dwc->dws.m_master);
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unsigned long was_cyclic;
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unsigned int reg_width;
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unsigned int periods;
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@ -245,10 +245,7 @@ struct dw_dma_chan {
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bool nollp;
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/* custom slave configuration */
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u8 src_id;
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u8 dst_id;
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u8 m_master;
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u8 p_master;
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struct dw_dma_slave dws;
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/* configuration passed via .device_config */
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struct dma_slave_config dma_sconfig;
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