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drm/i915: Make state dumpers take a const state 

Constify a bunch of the arguments of various state dumping
functions. Makes it clear they don't mutate the states.
And fix up some indent fails while at it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190517193132.8140-13-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
This commit is contained in:
Ville Syrjälä 2019-05-17 22:31:31 +03:00
parent 2833920d0e
commit 926878fba5
3 changed files with 20 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/i915/intel_display.c
View File

@ -11710,12 +11710,14 @@ static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
mode->crtc_hdisplay, mode->crtc_hsync_start, mode->crtc_hdisplay, mode->crtc_hsync_start,
mode->crtc_hsync_end, mode->crtc_htotal, mode->crtc_hsync_end, mode->crtc_htotal,
mode->crtc_vdisplay, mode->crtc_vsync_start, mode->crtc_vdisplay, mode->crtc_vsync_start,
mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); mode->crtc_vsync_end, mode->crtc_vtotal,
mode->type, mode->flags);
} }
static inline void static inline void
intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
unsigned int lane_count, struct intel_link_m_n *m_n) const char *id, unsigned int lane_count,
const struct intel_link_m_n *m_n)
{ {
DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
id, lane_count, id, lane_count,
@ -11793,7 +11795,7 @@ static const char *output_formats(enum intel_output_format format)
return output_format_str[format]; return output_format_str[format];
} }
static void intel_dump_pipe_config(struct intel_crtc_state *pipe_config, static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
const char *context) const char *context)
{ {
struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);

16
drivers/gpu/drm/i915/intel_dpll_mgr.c
View File

@ -454,7 +454,7 @@ ibx_get_dpll(struct intel_crtc_state *crtc_state,
} }
static void ibx_dump_hw_state(struct drm_i915_private *dev_priv, static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state) const struct intel_dpll_hw_state *hw_state)
{ {
DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
"fp0: 0x%x, fp1: 0x%x\n", "fp0: 0x%x, fp1: 0x%x\n",
@ -856,7 +856,7 @@ hsw_get_dpll(struct intel_crtc_state *crtc_state,
} }
static void hsw_dump_hw_state(struct drm_i915_private *dev_priv, static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state) const struct intel_dpll_hw_state *hw_state)
{ {
DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
hw_state->wrpll, hw_state->spll); hw_state->wrpll, hw_state->spll);
@ -1425,7 +1425,7 @@ skl_get_dpll(struct intel_crtc_state *crtc_state,
} }
static void skl_dump_hw_state(struct drm_i915_private *dev_priv, static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state) const struct intel_dpll_hw_state *hw_state)
{ {
DRM_DEBUG_KMS("dpll_hw_state: " DRM_DEBUG_KMS("dpll_hw_state: "
"ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
@ -1857,7 +1857,7 @@ bxt_get_dpll(struct intel_crtc_state *crtc_state,
} }
static void bxt_dump_hw_state(struct drm_i915_private *dev_priv, static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state) const struct intel_dpll_hw_state *hw_state)
{ {
DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
"pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
@ -1888,7 +1888,7 @@ struct intel_dpll_mgr {
struct intel_encoder *encoder); struct intel_encoder *encoder);
void (*dump_hw_state)(struct drm_i915_private *dev_priv, void (*dump_hw_state)(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state); const struct intel_dpll_hw_state *hw_state);
}; };
static const struct dpll_info pch_plls[] = { static const struct dpll_info pch_plls[] = {
@ -2371,7 +2371,7 @@ cnl_get_dpll(struct intel_crtc_state *crtc_state,
} }
static void cnl_dump_hw_state(struct drm_i915_private *dev_priv, static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state) const struct intel_dpll_hw_state *hw_state)
{ {
DRM_DEBUG_KMS("dpll_hw_state: " DRM_DEBUG_KMS("dpll_hw_state: "
"cfgcr0: 0x%x, cfgcr1: 0x%x\n", "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
@ -3171,7 +3171,7 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv,
} }
static void icl_dump_hw_state(struct drm_i915_private *dev_priv, static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state) const struct intel_dpll_hw_state *hw_state)
{ {
DRM_DEBUG_KMS("dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, " DRM_DEBUG_KMS("dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
"mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "
@ -3341,7 +3341,7 @@ void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
* Write the relevant values in @hw_state to dmesg using DRM_DEBUG_KMS. * Write the relevant values in @hw_state to dmesg using DRM_DEBUG_KMS.
*/ */
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state) const struct intel_dpll_hw_state *hw_state)
{ {
if (dev_priv->dpll_mgr) { if (dev_priv->dpll_mgr) {
dev_priv->dpll_mgr->dump_hw_state(dev_priv, hw_state); dev_priv->dpll_mgr->dump_hw_state(dev_priv, hw_state);

2
drivers/gpu/drm/i915/intel_dpll_mgr.h
View File

@ -343,7 +343,7 @@ void intel_shared_dpll_swap_state(struct drm_atomic_state *state);
void intel_shared_dpll_init(struct drm_device *dev); void intel_shared_dpll_init(struct drm_device *dev);
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state); const struct intel_dpll_hw_state *hw_state);
int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv); int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
bool intel_dpll_is_combophy(enum intel_dpll_id id); bool intel_dpll_is_combophy(enum intel_dpll_id id);