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wireless-drivers-next patches for 5.4 

First set of patches for 5.4.
 
 Major changes:
 
 brcmfmac
 
 * enable 160 MHz channel support
 
 rt2x00
 
 * add support for PLANEX GW-USMicroN USB device
 
 rtw88
 
 * add Bluetooth coexistance support
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Merge tag 'wireless-drivers-next-for-davem-2019-08-19' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next

Kalle Valo says:

====================
wireless-drivers-next patches for 5.4

First set of patches for 5.4.

Major changes:

brcmfmac

* enable 160 MHz channel support

rt2x00

* add support for PLANEX GW-USMicroN USB device

rtw88

* add Bluetooth coexistance support
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2019-08-19 18:32:30 -07:00
parent 5483ecefe9 6004cf298a
commit 932630fa90
70 changed files with 8550 additions and 2851 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/bcma/host_pci.c
View File

@ -260,8 +260,7 @@ static void bcma_host_pci_remove(struct pci_dev *dev)
#ifdef CONFIG_PM_SLEEP
static int bcma_host_pci_suspend(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct bcma_bus *bus = pci_get_drvdata(pdev);
struct bcma_bus *bus = dev_get_drvdata(dev);
bus->mapped_core = NULL;
@ -270,8 +269,7 @@ static int bcma_host_pci_suspend(struct device *dev)
static int bcma_host_pci_resume(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct bcma_bus *bus = pci_get_drvdata(pdev);
struct bcma_bus *bus = dev_get_drvdata(dev);
return bcma_bus_resume(bus);
}

21
drivers/net/wireless/broadcom/b43legacy/phy.c
View File

@ -69,17 +69,6 @@ static const s8 b43legacy_tssi2dbm_g_table[] = {
static void b43legacy_phy_initg(struct b43legacy_wldev *dev);
static inline
void b43legacy_voluntary_preempt(void)
{
B43legacy_BUG_ON(!(!in_atomic() && !in_irq() &&
!in_interrupt() && !irqs_disabled()));
#ifndef CONFIG_PREEMPT
cond_resched();
#endif /* CONFIG_PREEMPT */
}
/* Lock the PHY registers against concurrent access from the microcode.
* This lock is nonrecursive. */
void b43legacy_phy_lock(struct b43legacy_wldev *dev)
@ -1124,7 +1113,7 @@ static u16 b43legacy_phy_lo_b_r15_loop(struct b43legacy_wldev *dev)
ret += b43legacy_phy_read(dev, 0x002C);
}
local_irq_restore(flags);
b43legacy_voluntary_preempt();
cond_resched();
return ret;
}
@ -1253,7 +1242,7 @@ u16 b43legacy_phy_lo_g_deviation_subval(struct b43legacy_wldev *dev,
}
ret = b43legacy_phy_read(dev, 0x002D);
local_irq_restore(flags);
b43legacy_voluntary_preempt();
cond_resched();
return ret;
}
@ -1591,7 +1580,7 @@ void b43legacy_phy_lo_g_measure(struct b43legacy_wldev *dev)
b43legacy_radio_write16(dev, 0x43, i);
b43legacy_radio_write16(dev, 0x52, phy->txctl2);
udelay(10);
b43legacy_voluntary_preempt();
cond_resched();
b43legacy_phy_set_baseband_attenuation(dev, j * 2);
@ -1642,7 +1631,7 @@ void b43legacy_phy_lo_g_measure(struct b43legacy_wldev *dev)
phy->txctl2
| (3/*txctl1*/ << 4));
udelay(10);
b43legacy_voluntary_preempt();
cond_resched();
b43legacy_phy_set_baseband_attenuation(dev, j * 2);
@ -1665,7 +1654,7 @@ void b43legacy_phy_lo_g_measure(struct b43legacy_wldev *dev)
b43legacy_phy_write(dev, 0x0812, (r27 << 8) | 0xA2);
udelay(2);
b43legacy_phy_write(dev, 0x0812, (r27 << 8) | 0xA3);
b43legacy_voluntary_preempt();
cond_resched();
} else
b43legacy_phy_write(dev, 0x0015, r27 | 0xEFA0);
b43legacy_phy_lo_adjust(dev, is_initializing);

11
drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcdc.c
View File

@ -479,18 +479,11 @@ int brcmf_proto_bcdc_attach(struct brcmf_pub *drvr)
return -ENOMEM;
}
void brcmf_proto_bcdc_detach_pre_delif(struct brcmf_pub *drvr)
{
struct brcmf_bcdc *bcdc = drvr->proto->pd;
brcmf_fws_detach_pre_delif(bcdc->fws);
}
void brcmf_proto_bcdc_detach_post_delif(struct brcmf_pub *drvr)
void brcmf_proto_bcdc_detach(struct brcmf_pub *drvr)
{
struct brcmf_bcdc *bcdc = drvr->proto->pd;
drvr->proto->pd = NULL;
brcmf_fws_detach_post_delif(bcdc->fws);
brcmf_fws_detach(bcdc->fws);
kfree(bcdc);
}

6
drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcdc.h
View File

@ -7,16 +7,14 @@
#ifdef CONFIG_BRCMFMAC_PROTO_BCDC
int brcmf_proto_bcdc_attach(struct brcmf_pub *drvr);
void brcmf_proto_bcdc_detach_pre_delif(struct brcmf_pub *drvr);
void brcmf_proto_bcdc_detach_post_delif(struct brcmf_pub *drvr);
void brcmf_proto_bcdc_detach(struct brcmf_pub *drvr);
void brcmf_proto_bcdc_txflowblock(struct device *dev, bool state);
void brcmf_proto_bcdc_txcomplete(struct device *dev, struct sk_buff *txp,
bool success);
struct brcmf_fws_info *drvr_to_fws(struct brcmf_pub *drvr);
#else
static inline int brcmf_proto_bcdc_attach(struct brcmf_pub *drvr) { return 0; }
static void brcmf_proto_bcdc_detach_pre_delif(struct brcmf_pub *drvr) {};
static inline void brcmf_proto_bcdc_detach_post_delif(struct brcmf_pub *drvr) {}
static inline void brcmf_proto_bcdc_detach(struct brcmf_pub *drvr) {}
#endif
#endif /* BRCMFMAC_BCDC_H */

61
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
View File

@ -189,9 +189,9 @@ static const struct ieee80211_regdomain brcmf_regdom = {
*/
REG_RULE(2484-10, 2484+10, 20, 6, 20, 0),
/* IEEE 802.11a, channel 36..64 */
REG_RULE(5150-10, 5350+10, 80, 6, 20, 0),
REG_RULE(5150-10, 5350+10, 160, 6, 20, 0),
/* IEEE 802.11a, channel 100..165 */
REG_RULE(5470-10, 5850+10, 80, 6, 20, 0), }
REG_RULE(5470-10, 5850+10, 160, 6, 20, 0), }
};
/* Note: brcmf_cipher_suites is an array of int defining which cipher suites
@ -276,8 +276,26 @@ static u16 chandef_to_chanspec(struct brcmu_d11inf *d11inf,
else
ch_inf.sb = BRCMU_CHAN_SB_UU;
break;
case NL80211_CHAN_WIDTH_80P80:
case NL80211_CHAN_WIDTH_160:
ch_inf.bw = BRCMU_CHAN_BW_160;
if (primary_offset == -70)
ch_inf.sb = BRCMU_CHAN_SB_LLL;
else if (primary_offset == -50)
ch_inf.sb = BRCMU_CHAN_SB_LLU;
else if (primary_offset == -30)
ch_inf.sb = BRCMU_CHAN_SB_LUL;
else if (primary_offset == -10)
ch_inf.sb = BRCMU_CHAN_SB_LUU;
else if (primary_offset == 10)
ch_inf.sb = BRCMU_CHAN_SB_ULL;
else if (primary_offset == 30)
ch_inf.sb = BRCMU_CHAN_SB_ULU;
else if (primary_offset == 50)
ch_inf.sb = BRCMU_CHAN_SB_UUL;
else
ch_inf.sb = BRCMU_CHAN_SB_UUU;
break;
case NL80211_CHAN_WIDTH_80P80:
case NL80211_CHAN_WIDTH_5:
case NL80211_CHAN_WIDTH_10:
default:
@ -296,6 +314,7 @@ static u16 chandef_to_chanspec(struct brcmu_d11inf *d11inf,
}
d11inf->encchspec(&ch_inf);
brcmf_dbg(TRACE, "chanspec: 0x%x\n", ch_inf.chspec);
return ch_inf.chspec;
}
@ -1267,17 +1286,21 @@ static void brcmf_link_down(struct brcmf_cfg80211_vif *vif, u16 reason)
{
struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(vif->wdev.wiphy);
struct brcmf_pub *drvr = cfg->pub;
bool bus_up = drvr->bus_if->state == BRCMF_BUS_UP;
s32 err = 0;
brcmf_dbg(TRACE, "Enter\n");
if (test_and_clear_bit(BRCMF_VIF_STATUS_CONNECTED, &vif->sme_state)) {
brcmf_dbg(INFO, "Call WLC_DISASSOC to stop excess roaming\n");
err = brcmf_fil_cmd_data_set(vif->ifp,
BRCMF_C_DISASSOC, NULL, 0);
if (err) {
bphy_err(drvr, "WLC_DISASSOC failed (%d)\n", err);
if (bus_up) {
brcmf_dbg(INFO, "Call WLC_DISASSOC to stop excess roaming\n");
err = brcmf_fil_cmd_data_set(vif->ifp,
BRCMF_C_DISASSOC, NULL, 0);
if (err)
bphy_err(drvr, "WLC_DISASSOC failed (%d)\n",
err);
}
if ((vif->wdev.iftype == NL80211_IFTYPE_STATION) ||
(vif->wdev.iftype == NL80211_IFTYPE_P2P_CLIENT))
cfg80211_disconnected(vif->wdev.netdev, reason, NULL, 0,
@ -1287,7 +1310,8 @@ static void brcmf_link_down(struct brcmf_cfg80211_vif *vif, u16 reason)
clear_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status);
brcmf_btcoex_set_mode(vif, BRCMF_BTCOEX_ENABLED, 0);
if (vif->profile.use_fwsup != BRCMF_PROFILE_FWSUP_NONE) {
brcmf_set_pmk(vif->ifp, NULL, 0);
if (bus_up)
brcmf_set_pmk(vif->ifp, NULL, 0);
vif->profile.use_fwsup = BRCMF_PROFILE_FWSUP_NONE;
}
brcmf_dbg(TRACE, "Exit\n");
@ -2958,8 +2982,6 @@ static s32 brcmf_update_bss_info(struct brcmf_cfg80211_info *cfg,
struct brcmf_pub *drvr = cfg->pub;
struct brcmf_bss_info_le *bi;
const struct brcmf_tlv *tim;
u16 beacon_interval;
u8 dtim_period;
size_t ie_len;
u8 *ie;
s32 err = 0;
@ -2983,12 +3005,9 @@ static s32 brcmf_update_bss_info(struct brcmf_cfg80211_info *cfg,
ie = ((u8 *)bi) + le16_to_cpu(bi->ie_offset);
ie_len = le32_to_cpu(bi->ie_length);
beacon_interval = le16_to_cpu(bi->beacon_period);
tim = brcmf_parse_tlvs(ie, ie_len, WLAN_EID_TIM);
if (tim)
dtim_period = tim->data[1];
else {
if (!tim) {
/*
* active scan was done so we could not get dtim
* information out of probe response.
@ -3000,7 +3019,6 @@ static s32 brcmf_update_bss_info(struct brcmf_cfg80211_info *cfg,
bphy_err(drvr, "wl dtim_assoc failed (%d)\n", err);
goto update_bss_info_out;
}
dtim_period = (u8)var;
}
update_bss_info_out:
@ -4985,18 +5003,16 @@ static int brcmf_cfg80211_get_channel(struct wiphy *wiphy,
struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
struct net_device *ndev = wdev->netdev;
struct brcmf_pub *drvr = cfg->pub;
struct brcmf_if *ifp;
struct brcmu_chan ch;
enum nl80211_band band = 0;
enum nl80211_chan_width width = 0;
u32 chanspec;
int freq, err;
if (!ndev)
if (!ndev || drvr->bus_if->state != BRCMF_BUS_UP)
return -ENODEV;
ifp = netdev_priv(ndev);
err = brcmf_fil_iovar_int_get(ifp, "chanspec", &chanspec);
err = brcmf_fil_iovar_int_get(netdev_priv(ndev), "chanspec", &chanspec);
if (err) {
bphy_err(drvr, "chanspec failed (%d)\n", err);
return err;
@ -6714,6 +6730,11 @@ static int brcmf_setup_wiphy(struct wiphy *wiphy, struct brcmf_if *ifp)
}
}
if (wiphy->bands[NL80211_BAND_5GHZ] &&
brcmf_feat_is_enabled(ifp, BRCMF_FEAT_DOT11H))
wiphy_ext_feature_set(wiphy,
NL80211_EXT_FEATURE_DFS_OFFLOAD);
wiphy_read_of_freq_limits(wiphy);
return 0;

1
drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c
View File

@ -258,7 +258,6 @@ int brcmf_c_preinit_dcmds(struct brcmf_if *ifp)
/* query for 'ver' to get version info from firmware */
memset(buf, 0, sizeof(buf));
strlcpy(buf, "ver", sizeof(buf));
err = brcmf_fil_iovar_data_get(ifp, "ver", buf, sizeof(buf));
if (err < 0) {
bphy_err(drvr, "Retrieving version information failed, %d\n",

34
drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c
View File

@ -579,7 +579,8 @@ static int brcmf_netdev_stop(struct net_device *ndev)
brcmf_cfg80211_down(ndev);
brcmf_fil_iovar_data_set(ifp, "arp_hostip_clear", NULL, 0);
if (ifp->drvr->bus_if->state == BRCMF_BUS_UP)
brcmf_fil_iovar_data_set(ifp, "arp_hostip_clear", NULL, 0);
brcmf_net_setcarrier(ifp, false);
@ -1307,27 +1308,26 @@ void brcmf_detach(struct device *dev)
unregister_inet6addr_notifier(&drvr->inet6addr_notifier);
#endif
/* stop firmware event handling */
brcmf_fweh_detach(drvr);
if (drvr->config)
brcmf_p2p_detach(&drvr->config->p2p);
brcmf_bus_change_state(bus_if, BRCMF_BUS_DOWN);
brcmf_proto_detach_pre_delif(drvr);
/* make sure primary interface removed last */
for (i = BRCMF_MAX_IFS-1; i > -1; i--)
brcmf_remove_interface(drvr->iflist[i], false);
brcmf_cfg80211_detach(drvr->config);
drvr->config = NULL;
brcmf_bus_stop(drvr->bus_if);
brcmf_proto_detach_post_delif(drvr);
brcmf_fweh_detach(drvr);
brcmf_proto_detach(drvr);
/* make sure primary interface removed last */
for (i = BRCMF_MAX_IFS - 1; i > -1; i--) {
if (drvr->iflist[i])
brcmf_del_if(drvr, drvr->iflist[i]->bsscfgidx, false);
}
if (drvr->config) {
brcmf_p2p_detach(&drvr->config->p2p);
brcmf_cfg80211_detach(drvr->config);
drvr->config = NULL;
}
bus_if->drvr = NULL;
wiphy_free(drvr->wiphy);
}

1
drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.c
View File

@ -39,6 +39,7 @@ static const struct brcmf_feat_fwcap brcmf_fwcap_map[] = {
{ BRCMF_FEAT_P2P, "p2p" },
{ BRCMF_FEAT_MONITOR, "monitor" },
{ BRCMF_FEAT_MONITOR_FMT_RADIOTAP, "rtap" },
{ BRCMF_FEAT_DOT11H, "802.11h" }
};
#ifdef DEBUG

4
drivers/net/wireless/broadcom/brcm80211/brcmfmac/feature.h
View File

@ -25,6 +25,7 @@
* MONITOR: firmware can pass monitor packets to host.
* MONITOR_FMT_RADIOTAP: firmware provides monitor packets with radiotap header
* MONITOR_FMT_HW_RX_HDR: firmware provides monitor packets with hw/ucode header
* DOT11H: firmware supports 802.11h
*/
#define BRCMF_FEAT_LIST \
BRCMF_FEAT_DEF(MBSS) \
@ -43,7 +44,8 @@
BRCMF_FEAT_DEF(FWSUP) \
BRCMF_FEAT_DEF(MONITOR) \
BRCMF_FEAT_DEF(MONITOR_FMT_RADIOTAP) \
BRCMF_FEAT_DEF(MONITOR_FMT_HW_RX_HDR)
BRCMF_FEAT_DEF(MONITOR_FMT_HW_RX_HDR) \
BRCMF_FEAT_DEF(DOT11H)
/*
* Quirks:

9
drivers/net/wireless/broadcom/brcm80211/brcmfmac/fweh.c
View File

@ -303,16 +303,7 @@ void brcmf_fweh_attach(struct brcmf_pub *drvr)
void brcmf_fweh_detach(struct brcmf_pub *drvr)
{
struct brcmf_fweh_info *fweh = &drvr->fweh;
struct brcmf_if *ifp = brcmf_get_ifp(drvr, 0);
s8 eventmask[BRCMF_EVENTING_MASK_LEN];
if (ifp) {
/* clear all events */
memset(eventmask, 0, BRCMF_EVENTING_MASK_LEN);
(void)brcmf_fil_iovar_data_set(ifp, "event_msgs",
eventmask,
BRCMF_EVENTING_MASK_LEN);
}
/* cancel the worker */
cancel_work_sync(&fweh->event_work);
WARN_ON(!list_empty(&fweh->event_q));

16
drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c
View File

@ -2432,25 +2432,17 @@ struct brcmf_fws_info *brcmf_fws_attach(struct brcmf_pub *drvr)
return fws;
fail:
brcmf_fws_detach_pre_delif(fws);
brcmf_fws_detach_post_delif(fws);
brcmf_fws_detach(fws);
return ERR_PTR(rc);
}
void brcmf_fws_detach_pre_delif(struct brcmf_fws_info *fws)
void brcmf_fws_detach(struct brcmf_fws_info *fws)
{
if (!fws)
return;
if (fws->fws_wq) {
destroy_workqueue(fws->fws_wq);
fws->fws_wq = NULL;
}
}
void brcmf_fws_detach_post_delif(struct brcmf_fws_info *fws)
{
if (!fws)
return;
if (fws->fws_wq)
destroy_workqueue(fws->fws_wq);
/* cleanup */
brcmf_fws_lock(fws);

3
drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.h
View File

@ -7,8 +7,7 @@
#define FWSIGNAL_H_
struct brcmf_fws_info *brcmf_fws_attach(struct brcmf_pub *drvr);
void brcmf_fws_detach_pre_delif(struct brcmf_fws_info *fws);
void brcmf_fws_detach_post_delif(struct brcmf_fws_info *fws);
void brcmf_fws_detach(struct brcmf_fws_info *fws);
void brcmf_fws_debugfs_create(struct brcmf_pub *drvr);
bool brcmf_fws_queue_skbs(struct brcmf_fws_info *fws);
bool brcmf_fws_fc_active(struct brcmf_fws_info *fws);

7
drivers/net/wireless/broadcom/brcm80211/brcmfmac/msgbuf.c
View File

@ -1398,6 +1398,13 @@ void brcmf_msgbuf_delete_flowring(struct brcmf_pub *drvr, u16 flowid)
u8 ifidx;
int err;
/* no need to submit if firmware can not be reached */
if (drvr->bus_if->state != BRCMF_BUS_UP) {
brcmf_dbg(MSGBUF, "bus down, flowring will be removed\n");
brcmf_msgbuf_remove_flowring(msgbuf, flowid);
return;
}
commonring = msgbuf->commonrings[BRCMF_H2D_MSGRING_CONTROL_SUBMIT];
brcmf_commonring_lock(commonring);
ret_ptr = brcmf_commonring_reserve_for_write(commonring);

3
drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
View File

@ -794,7 +794,8 @@ static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo,
if (ch == '\n') {
console->log_str[console->log_idx] = 0;
if (error)
brcmf_err(bus, "CONSOLE: %s", console->log_str);
__brcmf_err(bus, __func__, "CONSOLE: %s",
console->log_str);
else
pr_debug("CONSOLE: %s", console->log_str);
console->log_idx = 0;

10
drivers/net/wireless/broadcom/brcm80211/brcmfmac/proto.c
View File

@ -56,22 +56,16 @@ int brcmf_proto_attach(struct brcmf_pub *drvr)
return -ENOMEM;
}
void brcmf_proto_detach_post_delif(struct brcmf_pub *drvr)
void brcmf_proto_detach(struct brcmf_pub *drvr)
{
brcmf_dbg(TRACE, "Enter\n");
if (drvr->proto) {
if (drvr->bus_if->proto_type == BRCMF_PROTO_BCDC)
brcmf_proto_bcdc_detach_post_delif(drvr);
brcmf_proto_bcdc_detach(drvr);
else if (drvr->bus_if->proto_type == BRCMF_PROTO_MSGBUF)
brcmf_proto_msgbuf_detach(drvr);
kfree(drvr->proto);
drvr->proto = NULL;
}
}
void brcmf_proto_detach_pre_delif(struct brcmf_pub *drvr)
{
if (drvr->proto && drvr->bus_if->proto_type == BRCMF_PROTO_BCDC)
brcmf_proto_bcdc_detach_pre_delif(drvr);
}

3
drivers/net/wireless/broadcom/brcm80211/brcmfmac/proto.h
View File

@ -43,8 +43,7 @@ struct brcmf_proto {
int brcmf_proto_attach(struct brcmf_pub *drvr);
void brcmf_proto_detach_pre_delif(struct brcmf_pub *drvr);
void brcmf_proto_detach_post_delif(struct brcmf_pub *drvr);
void brcmf_proto_detach(struct brcmf_pub *drvr);
static inline int brcmf_proto_hdrpull(struct brcmf_pub *drvr, bool do_fws,
struct sk_buff *skb,

13
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
View File

@ -5248,15 +5248,7 @@ int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
/* Default to 54g Auto */
/* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
s8 shortslot = BRCMS_SHORTSLOT_AUTO;
bool shortslot_restrict = false; /* Restrict association to stations
* that support shortslot
*/
bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
/* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
int preamble = BRCMS_PLCP_LONG;
bool preamble_restrict = false; /* Restrict association to stations
* that support short preambles
*/
struct brcms_band *band;
/* if N-support is enabled, allow Gmode set as long as requested
@ -5297,16 +5289,11 @@ int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
case GMODE_ONLY:
ofdm_basic = true;
preamble = BRCMS_PLCP_SHORT;
preamble_restrict = true;
break;
case GMODE_PERFORMANCE:
shortslot = BRCMS_SHORTSLOT_ON;
shortslot_restrict = true;
ofdm_basic = true;
preamble = BRCMS_PLCP_SHORT;
preamble_restrict = true;
break;
default:

2
drivers/net/wireless/intel/ipw2x00/ipw2100.c
View File

@ -4413,7 +4413,7 @@ static void ipw2100_kill_works(struct ipw2100_priv *priv)
static int ipw2100_tx_allocate(struct ipw2100_priv *priv)
{
int i, j, err = -EINVAL;
int i, j, err;
void *v;
dma_addr_t p;

3
drivers/net/wireless/intel/iwlegacy/common.c
View File

@ -4942,8 +4942,7 @@ EXPORT_SYMBOL(il_add_beacon_time);
static int
il_pci_suspend(struct device *device)
{
struct pci_dev *pdev = to_pci_dev(device);
struct il_priv *il = pci_get_drvdata(pdev);
struct il_priv *il = dev_get_drvdata(device);
/*
* This function is called when system goes into suspend state

14
drivers/net/wireless/marvell/libertas/if_spi.c
View File

@ -766,19 +766,15 @@ static int if_spi_c2h_data(struct if_spi_card *card)
/* Read the data from the WLAN module into our skb... */
err = spu_read(card, IF_SPI_DATA_RDWRPORT_REG, data, ALIGN(len, 4));
if (err)
goto free_skb;
if (err) {
dev_kfree_skb(skb);
goto out;
}
/* pass the SKB to libertas */
err = lbs_process_rxed_packet(card->priv, skb);
if (err)
goto free_skb;
/* lbs_process_rxed_packet() consumes the skb */
/* success */
goto out;
free_skb:
dev_kfree_skb(skb);
out:
if (err)
netdev_err(priv->dev, "%s: err=%d\n", __func__, err);

3
drivers/net/wireless/marvell/libertas/if_usb.c
View File

@ -50,7 +50,8 @@ static const struct lbs_fw_table fw_table[] = {
{ MODEL_8388, "libertas/usb8388_v5.bin", NULL },
{ MODEL_8388, "libertas/usb8388.bin", NULL },
{ MODEL_8388, "usb8388.bin", NULL },
{ MODEL_8682, "libertas/usb8682.bin", NULL }
{ MODEL_8682, "libertas/usb8682.bin", NULL },
{ 0, NULL, NULL }
};
static const struct usb_device_id if_usb_table[] = {

2
drivers/net/wireless/marvell/libertas/main.c
View File

@ -1046,7 +1046,7 @@ int lbs_rtap_supported(struct lbs_private *priv)
int lbs_start_card(struct lbs_private *priv)
{
struct net_device *dev = priv->dev;
int ret = -1;
int ret;
/* poke the firmware */
ret = lbs_setup_firmware(priv);

2
drivers/net/wireless/marvell/libertas_tf/cmd.c
View File

@ -65,7 +65,7 @@ static void lbtf_geo_init(struct lbtf_private *priv)
break;
}
for (ch = priv->range.start; ch < priv->range.end; ch++)
for (ch = range->start; ch < range->end; ch++)
priv->channels[CHAN_TO_IDX(ch)].flags = 0;
}

2
drivers/net/wireless/marvell/mwifiex/init.c
View File

@ -59,7 +59,7 @@ static void wakeup_timer_fn(struct timer_list *t)
adapter->hw_status = MWIFIEX_HW_STATUS_RESET;
mwifiex_cancel_all_pending_cmd(adapter);
if (adapter->if_ops.card_reset && !adapter->hs_activated)
if (adapter->if_ops.card_reset)
adapter->if_ops.card_reset(adapter);
}

8
drivers/net/wireless/marvell/mwifiex/pcie.c
View File

@ -150,10 +150,8 @@ static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter)
static int mwifiex_pcie_suspend(struct device *dev)
{
struct mwifiex_adapter *adapter;
struct pcie_service_card *card;
struct pci_dev *pdev = to_pci_dev(dev);
struct pcie_service_card *card = dev_get_drvdata(dev);
card = pci_get_drvdata(pdev);
/* Might still be loading firmware */
wait_for_completion(&card->fw_done);
@ -195,10 +193,8 @@ static int mwifiex_pcie_suspend(struct device *dev)
static int mwifiex_pcie_resume(struct device *dev)
{
struct mwifiex_adapter *adapter;
struct pcie_service_card *card;
struct pci_dev *pdev = to_pci_dev(dev);
struct pcie_service_card *card = dev_get_drvdata(dev);
card = pci_get_drvdata(pdev);
if (!card->adapter) {
dev_err(dev, "adapter structure is not valid\n");

2
drivers/net/wireless/marvell/mwifiex/scan.c
View File

@ -1244,7 +1244,7 @@ int mwifiex_update_bss_desc_with_ie(struct mwifiex_adapter *adapter,
mwifiex_dbg(adapter, ERROR,
"err: InterpretIE: in processing\t"
"IE, bytes left < IE length\n");
return -1;
return -EINVAL;
}
switch (element_id) {
case WLAN_EID_SSID:

3
drivers/net/wireless/marvell/mwifiex/tdls.c
View File

@ -731,7 +731,6 @@ mwifiex_construct_tdls_action_frame(struct mwifiex_private *priv,
u16 status_code, struct sk_buff *skb)
{
struct ieee80211_mgmt *mgmt;
u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
int ret;
u16 capab;
struct ieee80211_ht_cap *ht_cap;
@ -765,7 +764,7 @@ mwifiex_construct_tdls_action_frame(struct mwifiex_private *priv,
memmove(pos + ETH_ALEN, &mgmt->u.action.category,
sizeof(mgmt->u.action.u.tdls_discover_resp));
/* init address 4 */
memcpy(pos, bc_addr, ETH_ALEN);
eth_broadcast_addr(pos);
ret = mwifiex_tdls_append_rates_ie(priv, skb);
if (ret) {

3
drivers/net/wireless/mediatek/mt7601u/init.c
View File

@ -557,6 +557,9 @@ mt76_init_sband_2g(struct mt7601u_dev *dev)
{
dev->sband_2g = devm_kzalloc(dev->dev, sizeof(*dev->sband_2g),
GFP_KERNEL);
if (!dev->sband_2g)
return -ENOMEM;
dev->hw->wiphy->bands[NL80211_BAND_2GHZ] = dev->sband_2g;
WARN_ON(dev->ee->reg.start - 1 + dev->ee->reg.num >

4
drivers/net/wireless/mediatek/mt7601u/main.c
View File

@ -351,7 +351,7 @@ mt76_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta = params->sta;
enum ieee80211_ampdu_mlme_action action = params->action;
u16 tid = params->tid;
u16 *ssn = &params->ssn;
u16 ssn = params->ssn;
struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv;
WARN_ON(msta->wcid.idx > GROUP_WCID(0));
@ -371,7 +371,7 @@ mt76_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
break;
case IEEE80211_AMPDU_TX_START:
msta->agg_ssn[tid] = *ssn << 4;
msta->agg_ssn[tid] = ssn << 4;
ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
break;
case IEEE80211_AMPDU_TX_STOP_CONT:

4
drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c
View File

@ -430,7 +430,7 @@ static int qtnf_pcie_suspend(struct device *dev)
struct qtnf_pcie_bus_priv *priv;
struct qtnf_bus *bus;
bus = pci_get_drvdata(to_pci_dev(dev));
bus = dev_get_drvdata(dev);
if (!bus)
return -EFAULT;
@ -443,7 +443,7 @@ static int qtnf_pcie_resume(struct device *dev)
struct qtnf_pcie_bus_priv *priv;
struct qtnf_bus *bus;
bus = pci_get_drvdata(to_pci_dev(dev));
bus = dev_get_drvdata(dev);
if (!bus)
return -EFAULT;

1
drivers/net/wireless/ralink/rt2x00/rt2800usb.c
View File

@ -1086,6 +1086,7 @@ static const struct usb_device_id rt2800usb_device_table[] = {
{ USB_DEVICE(0x0846, 0x9013) },
{ USB_DEVICE(0x0846, 0x9019) },
/* Planex */
{ USB_DEVICE(0x2019, 0xed14) },
{ USB_DEVICE(0x2019, 0xed19) },
/* Ralink */
{ USB_DEVICE(0x148f, 0x3573) },

136
drivers/net/wireless/ralink/rt2x00/rt2x00debug.c
View File

@ -65,26 +65,6 @@ struct rt2x00debug_intf {
* - crypto stats file
*/
struct dentry *driver_folder;
struct dentry *driver_entry;
struct dentry *chipset_entry;
struct dentry *dev_flags;
struct dentry *cap_flags;
struct dentry *restart_hw;
struct dentry *register_folder;
struct dentry *csr_off_entry;
struct dentry *csr_val_entry;
struct dentry *eeprom_off_entry;
struct dentry *eeprom_val_entry;
struct dentry *bbp_off_entry;
struct dentry *bbp_val_entry;
struct dentry *rf_off_entry;
struct dentry *rf_val_entry;
struct dentry *rfcsr_off_entry;
struct dentry *rfcsr_val_entry;
struct dentry *queue_folder;
struct dentry *queue_frame_dump_entry;
struct dentry *queue_stats_entry;
struct dentry *crypto_stats_entry;
/*
* The frame dump file only allows a single reader,
@ -596,39 +576,34 @@ static const struct file_operations rt2x00debug_restart_hw = {
.llseek = generic_file_llseek,
};
static struct dentry *rt2x00debug_create_file_driver(const char *name,
struct rt2x00debug_intf
*intf,
struct debugfs_blob_wrapper
*blob)
static void rt2x00debug_create_file_driver(const char *name,
struct rt2x00debug_intf *intf,
struct debugfs_blob_wrapper *blob)
{
char *data;
data = kzalloc(3 * MAX_LINE_LENGTH, GFP_KERNEL);
if (!data)
return NULL;
return;
blob->data = data;
data += sprintf(data, "driver:\t%s\n", intf->rt2x00dev->ops->name);
data += sprintf(data, "version:\t%s\n", DRV_VERSION);
blob->size = strlen(blob->data);
return debugfs_create_blob(name, 0400, intf->driver_folder, blob);
debugfs_create_blob(name, 0400, intf->driver_folder, blob);
}
static struct dentry *rt2x00debug_create_file_chipset(const char *name,
struct rt2x00debug_intf
*intf,
struct
debugfs_blob_wrapper
*blob)
static void rt2x00debug_create_file_chipset(const char *name,
struct rt2x00debug_intf *intf,
struct debugfs_blob_wrapper *blob)
{
const struct rt2x00debug *debug = intf->debug;
char *data;
data = kzalloc(9 * MAX_LINE_LENGTH, GFP_KERNEL);
if (!data)
return NULL;
return;
blob->data = data;
data += sprintf(data, "rt chip:\t%04x\n", intf->rt2x00dev->chip.rt);
@ -654,13 +629,15 @@ static struct dentry *rt2x00debug_create_file_chipset(const char *name,
blob->size = strlen(blob->data);
return debugfs_create_blob(name, 0400, intf->driver_folder, blob);
debugfs_create_blob(name, 0400, intf->driver_folder, blob);
}
void rt2x00debug_register(struct rt2x00_dev *rt2x00dev)
{
const struct rt2x00debug *debug = rt2x00dev->ops->debugfs;
struct rt2x00debug_intf *intf;
struct dentry *queue_folder;
struct dentry *register_folder;
intf = kzalloc(sizeof(struct rt2x00debug_intf), GFP_KERNEL);
if (!intf) {
@ -676,43 +653,27 @@ void rt2x00debug_register(struct rt2x00_dev *rt2x00dev)
debugfs_create_dir(intf->rt2x00dev->ops->name,
rt2x00dev->hw->wiphy->debugfsdir);
intf->driver_entry =
rt2x00debug_create_file_driver("driver", intf, &intf->driver_blob);
rt2x00debug_create_file_driver("driver", intf, &intf->driver_blob);
rt2x00debug_create_file_chipset("chipset", intf, &intf->chipset_blob);
debugfs_create_file("dev_flags", 0400, intf->driver_folder, intf,
&rt2x00debug_fop_dev_flags);
debugfs_create_file("cap_flags", 0400, intf->driver_folder, intf,
&rt2x00debug_fop_cap_flags);
debugfs_create_file("restart_hw", 0200, intf->driver_folder, intf,
&rt2x00debug_restart_hw);
intf->chipset_entry =
rt2x00debug_create_file_chipset("chipset",
intf, &intf->chipset_blob);
intf->dev_flags = debugfs_create_file("dev_flags", 0400,
intf->driver_folder, intf,
&rt2x00debug_fop_dev_flags);
intf->cap_flags = debugfs_create_file("cap_flags", 0400,
intf->driver_folder, intf,
&rt2x00debug_fop_cap_flags);
intf->restart_hw = debugfs_create_file("restart_hw", 0200,
intf->driver_folder, intf,
&rt2x00debug_restart_hw);
intf->register_folder =
debugfs_create_dir("register", intf->driver_folder);
register_folder = debugfs_create_dir("register", intf->driver_folder);
#define RT2X00DEBUGFS_CREATE_REGISTER_ENTRY(__intf, __name) \
({ \
if (debug->__name.read) { \
(__intf)->__name##_off_entry = \
debugfs_create_u32(__stringify(__name) "_offset", \
0600, \
(__intf)->register_folder, \
&(__intf)->offset_##__name); \
debugfs_create_u32(__stringify(__name) "_offset", 0600, \
register_folder, \
&(__intf)->offset_##__name); \
\
(__intf)->__name##_val_entry = \
debugfs_create_file(__stringify(__name) "_value", \
0600, \
(__intf)->register_folder, \
(__intf), \
&rt2x00debug_fop_##__name); \
debugfs_create_file(__stringify(__name) "_value", 0600, \
register_folder, (__intf), \
&rt2x00debug_fop_##__name); \
} \
})
@ -724,26 +685,21 @@ void rt2x00debug_register(struct rt2x00_dev *rt2x00dev)
#undef RT2X00DEBUGFS_CREATE_REGISTER_ENTRY
intf->queue_folder =
debugfs_create_dir("queue", intf->driver_folder);
queue_folder = debugfs_create_dir("queue", intf->driver_folder);
intf->queue_frame_dump_entry =
debugfs_create_file("dump", 0400, intf->queue_folder,
intf, &rt2x00debug_fop_queue_dump);
debugfs_create_file("dump", 0400, queue_folder, intf,
&rt2x00debug_fop_queue_dump);
skb_queue_head_init(&intf->frame_dump_skbqueue);
init_waitqueue_head(&intf->frame_dump_waitqueue);
intf->queue_stats_entry =
debugfs_create_file("queue", 0400, intf->queue_folder,
intf, &rt2x00debug_fop_queue_stats);
debugfs_create_file("queue", 0400, queue_folder, intf,
&rt2x00debug_fop_queue_stats);
#ifdef CONFIG_RT2X00_LIB_CRYPTO
if (rt2x00_has_cap_hw_crypto(rt2x00dev))
intf->crypto_stats_entry =
debugfs_create_file("crypto", 0444, intf->queue_folder,
intf,
&rt2x00debug_fop_crypto_stats);
debugfs_create_file("crypto", 0444, queue_folder, intf,
&rt2x00debug_fop_crypto_stats);
#endif
return;
@ -758,29 +714,7 @@ void rt2x00debug_deregister(struct rt2x00_dev *rt2x00dev)
skb_queue_purge(&intf->frame_dump_skbqueue);
#ifdef CONFIG_RT2X00_LIB_CRYPTO
debugfs_remove(intf->crypto_stats_entry);
#endif
debugfs_remove(intf->queue_stats_entry);
debugfs_remove(intf->queue_frame_dump_entry);
debugfs_remove(intf->queue_folder);
debugfs_remove(intf->rfcsr_val_entry);
debugfs_remove(intf->rfcsr_off_entry);
debugfs_remove(intf->rf_val_entry);
debugfs_remove(intf->rf_off_entry);
debugfs_remove(intf->bbp_val_entry);
debugfs_remove(intf->bbp_off_entry);
debugfs_remove(intf->eeprom_val_entry);
debugfs_remove(intf->eeprom_off_entry);
debugfs_remove(intf->csr_val_entry);
debugfs_remove(intf->csr_off_entry);
debugfs_remove(intf->register_folder);
debugfs_remove(intf->dev_flags);
debugfs_remove(intf->restart_hw);
debugfs_remove(intf->cap_flags);
debugfs_remove(intf->chipset_entry);
debugfs_remove(intf->driver_entry);
debugfs_remove(intf->driver_folder);
debugfs_remove_recursive(intf->driver_folder);
kfree(intf->chipset_blob.data);
kfree(intf->driver_blob.data);
kfree(intf);

9
drivers/net/wireless/ralink/rt2x00/rt2x00usb.c
View File

@ -349,8 +349,7 @@ static void rt2x00usb_work_rxdone(struct work_struct *work)
while (!rt2x00queue_empty(rt2x00dev->rx)) {
entry = rt2x00queue_get_entry(rt2x00dev->rx, Q_INDEX_DONE);
if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
break;
/*
@ -389,8 +388,7 @@ static void rt2x00usb_interrupt_rxdone(struct urb *urb)
rt2x00lib_dmadone(entry);
/*
* Schedule the delayed work for reading the RX status
* from the device.
* Schedule the delayed work for processing RX data
*/
queue_work(rt2x00dev->workqueue, &rt2x00dev->rxdone_work);
}
@ -402,8 +400,7 @@ static bool rt2x00usb_kick_rx_entry(struct queue_entry *entry, void *data)
struct queue_entry_priv_usb *entry_priv = entry->priv_data;
int status;
if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
return false;
rt2x00lib_dmastart(entry);

11
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c
View File

@ -1525,7 +1525,7 @@ static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
/*
* WLAN action by PTA
*/
rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c);
/*
* BT select S0/S1 controlled by WiFi
@ -1568,9 +1568,14 @@ static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
/*
* 0x280, 0x00, 0x200, 0x80 - not clear
* Different settings per different antenna position.
* Antenna Position: | Normal Inverse
* --------------------------------------------------
* Antenna switch to BT: | 0x280, 0x00
* Antenna switch to WiFi: | 0x0, 0x280
* Antenna switch to PTA: | 0x200, 0x80
*/
rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80);
/*
* Software control, antenna at WiFi side

3
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
View File

@ -3891,12 +3891,13 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
/* Check if MAC is already powered on */
val8 = rtl8xxxu_read8(priv, REG_CR);
val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
/*
* Fix 92DU-VC S3 hang with the reason is that secondary mac is not
* initialized. First MAC returns 0xea, second MAC returns 0x00
*/
if (val8 == 0xea)
if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE))
macpower = false;
else
macpower = true;

8
drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.c
View File

@ -509,13 +509,7 @@ static u32 halbtc_get_wifi_link_status(struct btc_coexist *btcoexist)
static s32 halbtc_get_wifi_rssi(struct rtl_priv *rtlpriv)
{
int undec_sm_pwdb = 0;
if (rtlpriv->mac80211.link_state >= MAC80211_LINKED)
undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
else /* associated entry pwdb */
undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
return undec_sm_pwdb;
return rtlpriv->dm.undec_sm_pwdb;
}
static bool halbtc_get(void *void_btcoexist, u8 get_type, void *out_buf)

6
drivers/net/wireless/realtek/rtlwifi/pci.c
View File

@ -2409,8 +2409,7 @@ EXPORT_SYMBOL(rtl_pci_disconnect);
****************************************/
int rtl_pci_suspend(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct ieee80211_hw *hw = pci_get_drvdata(pdev);
struct ieee80211_hw *hw = dev_get_drvdata(dev);
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtlpriv->cfg->ops->hw_suspend(hw);
@ -2422,8 +2421,7 @@ EXPORT_SYMBOL(rtl_pci_suspend);
int rtl_pci_resume(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct ieee80211_hw *hw = pci_get_drvdata(pdev);
struct ieee80211_hw *hw = dev_get_drvdata(dev);
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtlpriv->cfg->ops->hw_resume(hw);

18
drivers/net/wireless/realtek/rtlwifi/regd.c
View File

@ -276,22 +276,6 @@ static void _rtl_reg_apply_world_flags(struct wiphy *wiphy,
return;
}
static void _rtl_dump_channel_map(struct wiphy *wiphy)
{
enum nl80211_band band;
struct ieee80211_supported_band *sband;
struct ieee80211_channel *ch;
unsigned int i;
for (band = 0; band < NUM_NL80211_BANDS; band++) {
if (!wiphy->bands[band])
continue;
sband = wiphy->bands[band];
for (i = 0; i < sband->n_channels; i++)
ch = &sband->channels[i];
}
}
static int _rtl_reg_notifier_apply(struct wiphy *wiphy,
struct regulatory_request *request,
struct rtl_regulatory *reg)
@ -309,8 +293,6 @@ static int _rtl_reg_notifier_apply(struct wiphy *wiphy,
break;
}
_rtl_dump_channel_map(wiphy);
return 0;
}

7
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c
View File

@ -1411,12 +1411,13 @@ void rtl88e_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
struct fast_ant_training *pfat_table = &rtldm->fat_table;
__le32 *pdesc32 = (__le32 *)pdesc;
if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
(rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV)) {
SET_TX_DESC_ANTSEL_A(pdesc, pfat_table->antsel_a[mac_id]);
SET_TX_DESC_ANTSEL_B(pdesc, pfat_table->antsel_b[mac_id]);
SET_TX_DESC_ANTSEL_C(pdesc, pfat_table->antsel_c[mac_id]);
set_tx_desc_antsel_a(pdesc32, pfat_table->antsel_a[mac_id]);
set_tx_desc_antsel_b(pdesc32, pfat_table->antsel_b[mac_id]);
set_tx_desc_antsel_c(pdesc32, pfat_table->antsel_c[mac_id]);
}
}

4
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c
View File

@ -115,10 +115,6 @@ int rtl88e_init_sw_vars(struct ieee80211_hw *hw)
rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
rtlpriv->cfg->mod_params->sw_crypto =
rtlpriv->cfg->mod_params->sw_crypto;
rtlpriv->cfg->mod_params->disable_watchdog =
rtlpriv->cfg->mod_params->disable_watchdog;
if (rtlpriv->cfg->mod_params->disable_watchdog)
pr_info("watchdog disabled\n");
if (!rtlpriv->psc.inactiveps)

255
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c
View File

@ -25,7 +25,7 @@ static u8 _rtl88ee_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
}
static void _rtl88ee_query_rxphystatus(struct ieee80211_hw *hw,
struct rtl_stats *pstatus, u8 *pdesc,
struct rtl_stats *pstatus, __le32 *pdesc,
struct rx_fwinfo_88e *p_drvinfo,
bool bpacket_match_bssid,
bool bpacket_toself, bool packet_beacon)
@ -271,7 +271,7 @@ static void _rtl88ee_smart_antenna(struct ieee80211_hw *hw,
static void _rtl88ee_translate_rx_signal_stuff(struct ieee80211_hw *hw,
struct sk_buff *skb,
struct rtl_stats *pstatus,
u8 *pdesc,
__le32 *pdesc,
struct rx_fwinfo_88e *p_drvinfo)
{
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
@ -313,13 +313,13 @@ static void _rtl88ee_translate_rx_signal_stuff(struct ieee80211_hw *hw,
rtl_process_phyinfo(hw, tmp_buf, pstatus);
}
static void _rtl88ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
u8 *virtualaddress)
static void rtl88ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
__le32 *virtualaddress)
{
u32 dwtmp = 0;
memset(virtualaddress, 0, 8);
SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
set_earlymode_pktnum(virtualaddress, ptcb_desc->empkt_num);
if (ptcb_desc->empkt_num == 1) {
dwtmp = ptcb_desc->empkt_len[0];
} else {
@ -327,7 +327,7 @@ static void _rtl88ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
dwtmp += ((dwtmp%4) ? (4-dwtmp%4) : 0)+4;
dwtmp += ptcb_desc->empkt_len[1];
}
SET_EARLYMODE_LEN0(virtualaddress, dwtmp);
set_earlymode_len0(virtualaddress, dwtmp);
if (ptcb_desc->empkt_num <= 3) {
dwtmp = ptcb_desc->empkt_len[2];
@ -336,7 +336,7 @@ static void _rtl88ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
dwtmp += ((dwtmp%4) ? (4-dwtmp%4) : 0)+4;
dwtmp += ptcb_desc->empkt_len[3];
}
SET_EARLYMODE_LEN1(virtualaddress, dwtmp);
set_earlymode_len1(virtualaddress, dwtmp);
if (ptcb_desc->empkt_num <= 5) {
dwtmp = ptcb_desc->empkt_len[4];
} else {
@ -344,8 +344,8 @@ static void _rtl88ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
dwtmp += ((dwtmp%4) ? (4-dwtmp%4) : 0)+4;
dwtmp += ptcb_desc->empkt_len[5];
}
SET_EARLYMODE_LEN2_1(virtualaddress, dwtmp & 0xF);
SET_EARLYMODE_LEN2_2(virtualaddress, dwtmp >> 4);
set_earlymode_len2_1(virtualaddress, dwtmp & 0xF);
set_earlymode_len2_2(virtualaddress, dwtmp >> 4);
if (ptcb_desc->empkt_num <= 7) {
dwtmp = ptcb_desc->empkt_len[6];
} else {
@ -353,7 +353,7 @@ static void _rtl88ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
dwtmp += ((dwtmp%4) ? (4-dwtmp%4) : 0)+4;
dwtmp += ptcb_desc->empkt_len[7];
}
SET_EARLYMODE_LEN3(virtualaddress, dwtmp);
set_earlymode_len3(virtualaddress, dwtmp);
if (ptcb_desc->empkt_num <= 9) {
dwtmp = ptcb_desc->empkt_len[8];
} else {
@ -361,50 +361,51 @@ static void _rtl88ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
dwtmp += ((dwtmp%4) ? (4-dwtmp%4) : 0)+4;
dwtmp += ptcb_desc->empkt_len[9];
}
SET_EARLYMODE_LEN4(virtualaddress, dwtmp);
set_earlymode_len4(virtualaddress, dwtmp);
}
bool rtl88ee_rx_query_desc(struct ieee80211_hw *hw,
struct rtl_stats *status,
struct ieee80211_rx_status *rx_status,
u8 *pdesc, struct sk_buff *skb)
u8 *pdesc8, struct sk_buff *skb)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rx_fwinfo_88e *p_drvinfo;
struct ieee80211_hdr *hdr;
u8 wake_match;
u32 phystatus = GET_RX_DESC_PHYST(pdesc);
__le32 *pdesc = (__le32 *)pdesc8;
u32 phystatus = get_rx_desc_physt(pdesc);
status->packet_report_type = (u8)GET_RX_STATUS_DESC_RPT_SEL(pdesc);
status->packet_report_type = (u8)get_rx_status_desc_rpt_sel(pdesc);
if (status->packet_report_type == TX_REPORT2)
status->length = (u16)GET_RX_RPT2_DESC_PKT_LEN(pdesc);
status->length = (u16)get_rx_rpt2_desc_pkt_len(pdesc);
else
status->length = (u16)GET_RX_DESC_PKT_LEN(pdesc);
status->rx_drvinfo_size = (u8)GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
status->length = (u16)get_rx_desc_pkt_len(pdesc);
status->rx_drvinfo_size = (u8)get_rx_desc_drv_info_size(pdesc) *
RX_DRV_INFO_SIZE_UNIT;
status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03);
status->icv = (u16)GET_RX_DESC_ICV(pdesc);
status->crc = (u16)GET_RX_DESC_CRC32(pdesc);
status->rx_bufshift = (u8)(get_rx_desc_shift(pdesc) & 0x03);
status->icv = (u16)get_rx_desc_icv(pdesc);
status->crc = (u16)get_rx_desc_crc32(pdesc);
status->hwerror = (status->crc | status->icv);
status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
status->rate = (u8)GET_RX_DESC_RXMCS(pdesc);
status->shortpreamble = (u16)GET_RX_DESC_SPLCP(pdesc);
status->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
status->isfirst_ampdu = (bool)((GET_RX_DESC_PAGGR(pdesc) == 1) &&
(GET_RX_DESC_FAGGR(pdesc) == 1));
status->decrypted = !get_rx_desc_swdec(pdesc);
status->rate = (u8)get_rx_desc_rxmcs(pdesc);
status->shortpreamble = (u16)get_rx_desc_splcp(pdesc);
status->isampdu = (bool) (get_rx_desc_paggr(pdesc) == 1);
status->isfirst_ampdu = (bool)((get_rx_desc_paggr(pdesc) == 1) &&
(get_rx_desc_faggr(pdesc) == 1));
if (status->packet_report_type == NORMAL_RX)
status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
status->rx_is40mhzpacket = (bool)GET_RX_DESC_BW(pdesc);
status->is_ht = (bool)GET_RX_DESC_RXHT(pdesc);
status->timestamp_low = get_rx_desc_tsfl(pdesc);
status->rx_is40mhzpacket = (bool)get_rx_desc_bw(pdesc);
status->is_ht = (bool)get_rx_desc_rxht(pdesc);
status->is_cck = RTL8188_RX_HAL_IS_CCK_RATE(status->rate);
status->macid = GET_RX_DESC_MACID(pdesc);
if (GET_RX_STATUS_DESC_PATTERN_MATCH(pdesc))
status->macid = get_rx_desc_macid(pdesc);
if (get_rx_status_desc_pattern_match(pdesc))
wake_match = BIT(2);
else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
else if (get_rx_status_desc_magic_match(pdesc))
wake_match = BIT(1);
else if (GET_RX_STATUS_DESC_UNICAST_MATCH(pdesc))
else if (get_rx_status_desc_unicast_match(pdesc))
wake_match = BIT(0);
else
wake_match = 0;
@ -465,15 +466,15 @@ bool rtl88ee_rx_query_desc(struct ieee80211_hw *hw,
rx_status->signal = status->recvsignalpower + 10;
if (status->packet_report_type == TX_REPORT2) {
status->macid_valid_entry[0] =
GET_RX_RPT2_DESC_MACID_VALID_1(pdesc);
get_rx_rpt2_desc_macid_valid_1(pdesc);
status->macid_valid_entry[1] =
GET_RX_RPT2_DESC_MACID_VALID_2(pdesc);
get_rx_rpt2_desc_macid_valid_2(pdesc);
}
return true;
}
void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
struct ieee80211_hdr *hdr, u8 *pdesc_tx,
struct ieee80211_hdr *hdr, u8 *pdesc8,
u8 *txbd, struct ieee80211_tx_info *info,
struct ieee80211_sta *sta,
struct sk_buff *skb,
@ -484,7 +485,6 @@ void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
u8 *pdesc = (u8 *)pdesc_tx;
u16 seq_number;
__le16 fc = hdr->frame_control;
unsigned int buf_len = 0;
@ -497,6 +497,7 @@ void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
dma_addr_t mapping;
u8 bw_40 = 0;
u8 short_gi = 0;
__le32 *pdesc = (u32 *)pdesc8;
if (mac->opmode == NL80211_IFTYPE_STATION) {
bw_40 = mac->bw_40;
@ -521,77 +522,77 @@ void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
"DMA mapping error\n");
return;
}
CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_88e));
clear_pci_tx_desc_content(pdesc, sizeof(struct tx_desc_88e));
if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
firstseg = true;
lastseg = true;
}
if (firstseg) {
if (rtlhal->earlymode_enable) {
SET_TX_DESC_PKT_OFFSET(pdesc, 1);
SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN +
set_tx_desc_pkt_offset(pdesc, 1);
set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN +
EM_HDR_LEN);
if (ptcb_desc->empkt_num) {
RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
"Insert 8 byte.pTcb->EMPktNum:%d\n",
ptcb_desc->empkt_num);
_rtl88ee_insert_emcontent(ptcb_desc,
(u8 *)(skb->data));
rtl88ee_insert_emcontent(ptcb_desc,
(__le32 *)(skb->data));
}
} else {
SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN);
}
ptcb_desc->use_driver_rate = true;
SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
set_tx_desc_tx_rate(pdesc, ptcb_desc->hw_rate);
if (ptcb_desc->hw_rate > DESC92C_RATEMCS0)
short_gi = (ptcb_desc->use_shortgi) ? 1 : 0;
else
short_gi = (ptcb_desc->use_shortpreamble) ? 1 : 0;
SET_TX_DESC_DATA_SHORTGI(pdesc, short_gi);
set_tx_desc_data_shortgi(pdesc, short_gi);
if (info->flags & IEEE80211_TX_CTL_AMPDU) {
SET_TX_DESC_AGG_ENABLE(pdesc, 1);
SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
set_tx_desc_agg_enable(pdesc, 1);
set_tx_desc_max_agg_num(pdesc, 0x14);
}
SET_TX_DESC_SEQ(pdesc, seq_number);
SET_TX_DESC_RTS_ENABLE(pdesc, ((ptcb_desc->rts_enable &&
set_tx_desc_seq(pdesc, seq_number);
set_tx_desc_rts_enable(pdesc, ((ptcb_desc->rts_enable &&
!ptcb_desc->cts_enable) ? 1 : 0));
SET_TX_DESC_HW_RTS_ENABLE(pdesc, 0);
SET_TX_DESC_CTS2SELF(pdesc, ((ptcb_desc->cts_enable) ? 1 : 0));
SET_TX_DESC_RTS_STBC(pdesc, ((ptcb_desc->rts_stbc) ? 1 : 0));
set_tx_desc_hw_rts_enable(pdesc, 0);
set_tx_desc_cts2self(pdesc, ((ptcb_desc->cts_enable) ? 1 : 0));
set_tx_desc_rts_stbc(pdesc, ((ptcb_desc->rts_stbc) ? 1 : 0));
SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
SET_TX_DESC_RTS_BW(pdesc, 0);
SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
SET_TX_DESC_RTS_SHORT(pdesc,
set_tx_desc_rts_rate(pdesc, ptcb_desc->rts_rate);
set_tx_desc_rts_bw(pdesc, 0);
set_tx_desc_rts_sc(pdesc, ptcb_desc->rts_sc);
set_tx_desc_rts_short(pdesc,
((ptcb_desc->rts_rate <= DESC92C_RATE54M) ?
(ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
(ptcb_desc->rts_use_shortgi ? 1 : 0)));
if (ptcb_desc->tx_enable_sw_calc_duration)
SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
set_tx_desc_nav_use_hdr(pdesc, 1);
if (bw_40) {
if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
SET_TX_DESC_DATA_BW(pdesc, 1);
SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
set_tx_desc_data_bw(pdesc, 1);
set_tx_desc_tx_sub_carrier(pdesc, 3);
} else {
SET_TX_DESC_DATA_BW(pdesc, 0);
SET_TX_DESC_TX_SUB_CARRIER(pdesc,
set_tx_desc_data_bw(pdesc, 0);
set_tx_desc_tx_sub_carrier(pdesc,
mac->cur_40_prime_sc);
}
} else {
SET_TX_DESC_DATA_BW(pdesc, 0);
SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
set_tx_desc_data_bw(pdesc, 0);
set_tx_desc_tx_sub_carrier(pdesc, 0);
}
SET_TX_DESC_LINIP(pdesc, 0);
SET_TX_DESC_PKT_SIZE(pdesc, (u16)skb_len);
set_tx_desc_linip(pdesc, 0);
set_tx_desc_pkt_size(pdesc, (u16)skb_len);
if (sta) {
u8 ampdu_density = sta->ht_cap.ampdu_density;
SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
set_tx_desc_ampdu_density(pdesc, ampdu_density);
}
if (info->control.hw_key) {
struct ieee80211_key_conf *keyconf;
@ -601,76 +602,77 @@ void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
case WLAN_CIPHER_SUITE_WEP40:
case WLAN_CIPHER_SUITE_WEP104:
case WLAN_CIPHER_SUITE_TKIP:
SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
set_tx_desc_sec_type(pdesc, 0x1);
break;
case WLAN_CIPHER_SUITE_CCMP:
SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
set_tx_desc_sec_type(pdesc, 0x3);
break;
default:
SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
set_tx_desc_sec_type(pdesc, 0x0);
break;
}
}
SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
SET_TX_DESC_DISABLE_FB(pdesc, ptcb_desc->disable_ratefallback ?
set_tx_desc_queue_sel(pdesc, fw_qsel);
set_tx_desc_data_rate_fb_limit(pdesc, 0x1F);
set_tx_desc_rts_rate_fb_limit(pdesc, 0xF);
set_tx_desc_disable_fb(pdesc, ptcb_desc->disable_ratefallback ?
1 : 0);
SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
set_tx_desc_use_rate(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
/*SET_TX_DESC_PWR_STATUS(pdesc, pwr_status);*/
/*set_tx_desc_pwr_status(pdesc, pwr_status);*/
/* Set TxRate and RTSRate in TxDesc */
/* This prevent Tx initial rate of new-coming packets */
/* from being overwritten by retried packet rate.*/
if (!ptcb_desc->use_driver_rate) {
/*SET_TX_DESC_RTS_RATE(pdesc, 0x08); */
/* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
/*set_tx_desc_rts_rate(pdesc, 0x08); */
/* set_tx_desc_tx_rate(pdesc, 0x0b); */
}
if (ieee80211_is_data_qos(fc)) {
if (mac->rdg_en) {
RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
"Enable RDG function.\n");
SET_TX_DESC_RDG_ENABLE(pdesc, 1);
SET_TX_DESC_HTC(pdesc, 1);
set_tx_desc_rdg_enable(pdesc, 1);
set_tx_desc_htc(pdesc, 1);
}
}
}
SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)buf_len);
SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
set_tx_desc_first_seg(pdesc, (firstseg ? 1 : 0));
set_tx_desc_last_seg(pdesc, (lastseg ? 1 : 0));
set_tx_desc_tx_buffer_size(pdesc, (u16)buf_len);
set_tx_desc_tx_buffer_address(pdesc, mapping);
if (rtlpriv->dm.useramask) {
SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
set_tx_desc_rate_id(pdesc, ptcb_desc->ratr_index);
set_tx_desc_macid(pdesc, ptcb_desc->mac_id);
} else {
SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
set_tx_desc_rate_id(pdesc, 0xC + ptcb_desc->ratr_index);
set_tx_desc_macid(pdesc, ptcb_desc->ratr_index);
}
if (ieee80211_is_data_qos(fc))
SET_TX_DESC_QOS(pdesc, 1);
set_tx_desc_qos(pdesc, 1);
if (!ieee80211_is_data_qos(fc))
SET_TX_DESC_HWSEQ_EN(pdesc, 1);
SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
set_tx_desc_hwseq_en(pdesc, 1);
set_tx_desc_more_frag(pdesc, (lastseg ? 0 : 1));
if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
SET_TX_DESC_BMC(pdesc, 1);
set_tx_desc_bmc(pdesc, 1);
}
rtl88e_dm_set_tx_ant_by_tx_info(hw, pdesc, ptcb_desc->mac_id);
rtl88e_dm_set_tx_ant_by_tx_info(hw, pdesc8, ptcb_desc->mac_id);
RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
}
void rtl88ee_tx_fill_cmddesc(struct ieee80211_hw *hw,
u8 *pdesc, bool firstseg,
u8 *pdesc8, bool firstseg,
bool lastseg, struct sk_buff *skb)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
u8 fw_queue = QSLT_BEACON;
__le32 *pdesc = (__le32 *)pdesc8;
dma_addr_t mapping = pci_map_single(rtlpci->pdev,
skb->data, skb->len,
@ -684,58 +686,60 @@ void rtl88ee_tx_fill_cmddesc(struct ieee80211_hw *hw,
"DMA mapping error\n");
return;
}
CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE);
clear_pci_tx_desc_content(pdesc, TX_DESC_SIZE);
if (firstseg)
SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN);
SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M);
set_tx_desc_tx_rate(pdesc, DESC92C_RATE1M);
SET_TX_DESC_SEQ(pdesc, 0);
set_tx_desc_seq(pdesc, 0);
SET_TX_DESC_LINIP(pdesc, 0);
set_tx_desc_linip(pdesc, 0);
SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
set_tx_desc_queue_sel(pdesc, fw_queue);
SET_TX_DESC_FIRST_SEG(pdesc, 1);
SET_TX_DESC_LAST_SEG(pdesc, 1);
set_tx_desc_first_seg(pdesc, 1);
set_tx_desc_last_seg(pdesc, 1);
SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
set_tx_desc_tx_buffer_size(pdesc, (u16)(skb->len));
SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
set_tx_desc_tx_buffer_address(pdesc, mapping);
SET_TX_DESC_RATE_ID(pdesc, 7);
SET_TX_DESC_MACID(pdesc, 0);
set_tx_desc_rate_id(pdesc, 7);
set_tx_desc_macid(pdesc, 0);
SET_TX_DESC_OWN(pdesc, 1);
set_tx_desc_own(pdesc, 1);
SET_TX_DESC_PKT_SIZE(pdesc, (u16)(skb->len));
set_tx_desc_pkt_size(pdesc, (u16)(skb->len));
SET_TX_DESC_FIRST_SEG(pdesc, 1);
SET_TX_DESC_LAST_SEG(pdesc, 1);
set_tx_desc_first_seg(pdesc, 1);
set_tx_desc_last_seg(pdesc, 1);
SET_TX_DESC_OFFSET(pdesc, 0x20);
set_tx_desc_offset(pdesc, 0x20);
SET_TX_DESC_USE_RATE(pdesc, 1);
set_tx_desc_use_rate(pdesc, 1);
if (!ieee80211_is_data_qos(fc))
SET_TX_DESC_HWSEQ_EN(pdesc, 1);
set_tx_desc_hwseq_en(pdesc, 1);
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
"H2C Tx Cmd Content\n",
pdesc, TX_DESC_SIZE);
}
void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc8,
bool istx, u8 desc_name, u8 *val)
{
__le32 *pdesc = (__le32 *)pdesc8;
if (istx == true) {
switch (desc_name) {
case HW_DESC_OWN:
SET_TX_DESC_OWN(pdesc, 1);
set_tx_desc_own(pdesc, 1);
break;
case HW_DESC_TX_NEXTDESC_ADDR:
SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val);
set_tx_desc_next_desc_address(pdesc, *(u32 *)val);
break;
default:
WARN_ONCE(true, "rtl8188ee: ERR txdesc :%d not processed\n",
@ -745,16 +749,16 @@ void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
} else {
switch (desc_name) {
case HW_DESC_RXOWN:
SET_RX_DESC_OWN(pdesc, 1);
set_rx_desc_own(pdesc, 1);
break;
case HW_DESC_RXBUFF_ADDR:
SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *)val);
set_rx_desc_buff_addr(pdesc, *(u32 *)val);
break;
case HW_DESC_RXPKT_LEN:
SET_RX_DESC_PKT_LEN(pdesc, *(u32 *)val);
set_rx_desc_pkt_len(pdesc, *(u32 *)val);
break;
case HW_DESC_RXERO:
SET_RX_DESC_EOR(pdesc, 1);
set_rx_desc_eor(pdesc, 1);
break;
default:
WARN_ONCE(true, "rtl8188ee: ERR rxdesc :%d not processed\n",
@ -765,17 +769,18 @@ void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
}
u64 rtl88ee_get_desc(struct ieee80211_hw *hw,
u8 *pdesc, bool istx, u8 desc_name)
u8 *pdesc8, bool istx, u8 desc_name)
{
u32 ret = 0;
__le32 *pdesc = (__le32 *)pdesc8;
if (istx == true) {
switch (desc_name) {
case HW_DESC_OWN:
ret = GET_TX_DESC_OWN(pdesc);
ret = get_tx_desc_own(pdesc);
break;
case HW_DESC_TXBUFF_ADDR:
ret = GET_TX_DESC_TX_BUFFER_ADDRESS(pdesc);
ret = get_tx_desc_tx_buffer_address(pdesc);
break;
default:
WARN_ONCE(true, "rtl8188ee: ERR txdesc :%d not processed\n",
@ -785,13 +790,13 @@ u64 rtl88ee_get_desc(struct ieee80211_hw *hw,
} else {
switch (desc_name) {
case HW_DESC_OWN:
ret = GET_RX_DESC_OWN(pdesc);
ret = get_rx_desc_own(pdesc);
break;
case HW_DESC_RXPKT_LEN:
ret = GET_RX_DESC_PKT_LEN(pdesc);
ret = get_rx_desc_pkt_len(pdesc);
break;
case HW_DESC_RXBUFF_ADDR:
ret = GET_RX_DESC_BUFF_ADDR(pdesc);
ret = get_rx_desc_buff_addr(pdesc);
break;
default:
WARN_ONCE(true, "rtl8188ee: ERR rxdesc :%d not processed\n",

988
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h
View File

File diff suppressed because it is too large Load Diff

2
drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c
View File

@ -113,8 +113,6 @@ int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
rtlpriv->cfg->mod_params->sw_crypto =
rtlpriv->cfg->mod_params->sw_crypto;
if (!rtlpriv->psc.inactiveps)
pr_info("rtl8192ce: Power Save off (module option)\n");
if (!rtlpriv->psc.fwctrl_lps)

215
drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c
View File

@ -251,8 +251,8 @@ static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
*/
if (i == 0)
pstats->signalquality =
(u8) (evm & 0xff);
pstats->rx_mimo_sig_qual[i] = (u8) (evm & 0xff);
(u8)(evm & 0xff);
pstats->rx_mimo_sig_qual[i] = (u8)(evm & 0xff);
}
}
}
@ -262,10 +262,10 @@ static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
*/
if (is_cck_rate)
pstats->signalstrength =
(u8) (_rtl92ce_signal_scale_mapping(hw, pwdb_all));
(u8)(_rtl92ce_signal_scale_mapping(hw, pwdb_all));
else if (rf_rx_num != 0)
pstats->signalstrength =
(u8) (_rtl92ce_signal_scale_mapping
(u8)(_rtl92ce_signal_scale_mapping
(hw, total_rssi /= rf_rx_num));
}
@ -317,29 +317,30 @@ static void _rtl92ce_translate_rx_signal_stuff(struct ieee80211_hw *hw,
bool rtl92ce_rx_query_desc(struct ieee80211_hw *hw,
struct rtl_stats *stats,
struct ieee80211_rx_status *rx_status,
u8 *p_desc, struct sk_buff *skb)
u8 *p_desc8, struct sk_buff *skb)
{
struct rx_fwinfo_92c *p_drvinfo;
struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc;
struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc8;
struct ieee80211_hdr *hdr;
u32 phystatus = GET_RX_DESC_PHYST(pdesc);
__le32 *p_desc = (__le32 *)p_desc8;
u32 phystatus = get_rx_desc_physt(p_desc);
stats->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
stats->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
stats->length = (u16)get_rx_desc_pkt_len(p_desc);
stats->rx_drvinfo_size = (u8)get_rx_desc_drv_info_size(p_desc) *
RX_DRV_INFO_SIZE_UNIT;
stats->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03);
stats->icv = (u16) GET_RX_DESC_ICV(pdesc);
stats->crc = (u16) GET_RX_DESC_CRC32(pdesc);
stats->rx_bufshift = (u8)(get_rx_desc_shift(p_desc) & 0x03);
stats->icv = (u16)get_rx_desc_icv(p_desc);
stats->crc = (u16)get_rx_desc_crc32(p_desc);
stats->hwerror = (stats->crc | stats->icv);
stats->decrypted = !GET_RX_DESC_SWDEC(pdesc);
stats->rate = (u8) GET_RX_DESC_RXMCS(pdesc);
stats->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc);
stats->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
stats->isfirst_ampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1)
&& (GET_RX_DESC_FAGGR(pdesc) == 1));
stats->timestamp_low = GET_RX_DESC_TSFL(pdesc);
stats->rx_is40mhzpacket = (bool)GET_RX_DESC_BW(pdesc);
stats->is_ht = (bool)GET_RX_DESC_RXHT(pdesc);
stats->decrypted = !get_rx_desc_swdec(p_desc);
stats->rate = (u8)get_rx_desc_rxmcs(p_desc);
stats->shortpreamble = (u16)get_rx_desc_splcp(p_desc);
stats->isampdu = (bool)(get_rx_desc_paggr(p_desc) == 1);
stats->isfirst_ampdu = (bool)((get_rx_desc_paggr(p_desc) == 1) &&
(get_rx_desc_faggr(p_desc) == 1));
stats->timestamp_low = get_rx_desc_tsfl(p_desc);
stats->rx_is40mhzpacket = (bool)get_rx_desc_bw(p_desc);
stats->is_ht = (bool)get_rx_desc_rxht(p_desc);
stats->is_cck = RX_HAL_IS_CCK_RATE(pdesc->rxmcs);
@ -400,7 +401,7 @@ bool rtl92ce_rx_query_desc(struct ieee80211_hw *hw,
}
void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
struct ieee80211_hdr *hdr, u8 *pdesc_tx,
struct ieee80211_hdr *hdr, u8 *pdesc8,
u8 *pbd_desc_tx, struct ieee80211_tx_info *info,
struct ieee80211_sta *sta,
struct sk_buff *skb,
@ -411,7 +412,7 @@ void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
bool defaultadapter = true;
u8 *pdesc = pdesc_tx;
__le32 *pdesc = (__le32 *)pdesc8;
u16 seq_number;
__le16 fc = hdr->frame_control;
u8 fw_qsel = _rtl92ce_map_hwqueue_to_fwqueue(skb, hw_queue);
@ -447,64 +448,64 @@ void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
rtl_get_tcb_desc(hw, info, sta, skb, tcb_desc);
CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_92c));
clear_pci_tx_desc_content(pdesc, sizeof(struct tx_desc_92c));
if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
firstseg = true;
lastseg = true;
}
if (firstseg) {
SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN);
SET_TX_DESC_TX_RATE(pdesc, tcb_desc->hw_rate);
set_tx_desc_tx_rate(pdesc, tcb_desc->hw_rate);
if (tcb_desc->use_shortgi || tcb_desc->use_shortpreamble)
SET_TX_DESC_DATA_SHORTGI(pdesc, 1);
set_tx_desc_data_shortgi(pdesc, 1);
if (info->flags & IEEE80211_TX_CTL_AMPDU) {
SET_TX_DESC_AGG_BREAK(pdesc, 1);
SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
set_tx_desc_agg_break(pdesc, 1);
set_tx_desc_max_agg_num(pdesc, 0x14);
}
SET_TX_DESC_SEQ(pdesc, seq_number);
set_tx_desc_seq(pdesc, seq_number);
SET_TX_DESC_RTS_ENABLE(pdesc, ((tcb_desc->rts_enable &&
set_tx_desc_rts_enable(pdesc, ((tcb_desc->rts_enable &&
!tcb_desc->
cts_enable) ? 1 : 0));
SET_TX_DESC_HW_RTS_ENABLE(pdesc,
set_tx_desc_hw_rts_enable(pdesc,
((tcb_desc->rts_enable
|| tcb_desc->cts_enable) ? 1 : 0));
SET_TX_DESC_CTS2SELF(pdesc, ((tcb_desc->cts_enable) ? 1 : 0));
SET_TX_DESC_RTS_STBC(pdesc, ((tcb_desc->rts_stbc) ? 1 : 0));
set_tx_desc_cts2self(pdesc, ((tcb_desc->cts_enable) ? 1 : 0));
set_tx_desc_rts_stbc(pdesc, ((tcb_desc->rts_stbc) ? 1 : 0));
SET_TX_DESC_RTS_RATE(pdesc, tcb_desc->rts_rate);
SET_TX_DESC_RTS_BW(pdesc, 0);
SET_TX_DESC_RTS_SC(pdesc, tcb_desc->rts_sc);
SET_TX_DESC_RTS_SHORT(pdesc,
set_tx_desc_rts_rate(pdesc, tcb_desc->rts_rate);
set_tx_desc_rts_bw(pdesc, 0);
set_tx_desc_rts_sc(pdesc, tcb_desc->rts_sc);
set_tx_desc_rts_short(pdesc,
((tcb_desc->rts_rate <= DESC_RATE54M) ?
(tcb_desc->rts_use_shortpreamble ? 1 : 0)
: (tcb_desc->rts_use_shortgi ? 1 : 0)));
if (bw_40) {
if (tcb_desc->packet_bw) {
SET_TX_DESC_DATA_BW(pdesc, 1);
SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
set_tx_desc_data_bw(pdesc, 1);
set_tx_desc_tx_sub_carrier(pdesc, 3);
} else {
SET_TX_DESC_DATA_BW(pdesc, 0);
SET_TX_DESC_TX_SUB_CARRIER(pdesc,
set_tx_desc_data_bw(pdesc, 0);
set_tx_desc_tx_sub_carrier(pdesc,
mac->cur_40_prime_sc);
}
} else {
SET_TX_DESC_DATA_BW(pdesc, 0);
SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
set_tx_desc_data_bw(pdesc, 0);
set_tx_desc_tx_sub_carrier(pdesc, 0);
}
SET_TX_DESC_LINIP(pdesc, 0);
SET_TX_DESC_PKT_SIZE(pdesc, (u16) skb->len);
set_tx_desc_linip(pdesc, 0);
set_tx_desc_pkt_size(pdesc, (u16)skb->len);
if (sta) {
u8 ampdu_density = sta->ht_cap.ampdu_density;
SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
set_tx_desc_ampdu_density(pdesc, ampdu_density);
}
if (info->control.hw_key) {
@ -515,77 +516,78 @@ void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
case WLAN_CIPHER_SUITE_WEP40:
case WLAN_CIPHER_SUITE_WEP104:
case WLAN_CIPHER_SUITE_TKIP:
SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
set_tx_desc_sec_type(pdesc, 0x1);
break;
case WLAN_CIPHER_SUITE_CCMP:
SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
set_tx_desc_sec_type(pdesc, 0x3);
break;
default:
SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
set_tx_desc_sec_type(pdesc, 0x0);
break;
}
}
SET_TX_DESC_PKT_ID(pdesc, 0);
SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
set_tx_desc_pkt_id(pdesc, 0);
set_tx_desc_queue_sel(pdesc, fw_qsel);
SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
SET_TX_DESC_DISABLE_FB(pdesc, 0);
SET_TX_DESC_USE_RATE(pdesc, tcb_desc->use_driver_rate ? 1 : 0);
set_tx_desc_data_rate_fb_limit(pdesc, 0x1F);
set_tx_desc_rts_rate_fb_limit(pdesc, 0xF);
set_tx_desc_disable_fb(pdesc, 0);
set_tx_desc_use_rate(pdesc, tcb_desc->use_driver_rate ? 1 : 0);
if (ieee80211_is_data_qos(fc)) {
if (mac->rdg_en) {
RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
"Enable RDG function\n");
SET_TX_DESC_RDG_ENABLE(pdesc, 1);
SET_TX_DESC_HTC(pdesc, 1);
set_tx_desc_rdg_enable(pdesc, 1);
set_tx_desc_htc(pdesc, 1);
}
}
}
rcu_read_unlock();
SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
set_tx_desc_first_seg(pdesc, (firstseg ? 1 : 0));
set_tx_desc_last_seg(pdesc, (lastseg ? 1 : 0));
SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) skb->len);
set_tx_desc_tx_buffer_size(pdesc, (u16)skb->len);
SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
set_tx_desc_tx_buffer_address(pdesc, mapping);
if (rtlpriv->dm.useramask) {
SET_TX_DESC_RATE_ID(pdesc, tcb_desc->ratr_index);
SET_TX_DESC_MACID(pdesc, tcb_desc->mac_id);
set_tx_desc_rate_id(pdesc, tcb_desc->ratr_index);
set_tx_desc_macid(pdesc, tcb_desc->mac_id);
} else {
SET_TX_DESC_RATE_ID(pdesc, 0xC + tcb_desc->ratr_index);
SET_TX_DESC_MACID(pdesc, tcb_desc->ratr_index);
set_tx_desc_rate_id(pdesc, 0xC + tcb_desc->ratr_index);
set_tx_desc_macid(pdesc, tcb_desc->ratr_index);
}
if ((!ieee80211_is_data_qos(fc)) && ppsc->fwctrl_lps) {
SET_TX_DESC_HWSEQ_EN(pdesc, 1);
SET_TX_DESC_PKT_ID(pdesc, 8);
set_tx_desc_hwseq_en(pdesc, 1);
set_tx_desc_pkt_id(pdesc, 8);
if (!defaultadapter)
SET_TX_DESC_QOS(pdesc, 1);
set_tx_desc_qos(pdesc, 1);
}
SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
set_tx_desc_more_frag(pdesc, (lastseg ? 0 : 1));
if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
SET_TX_DESC_BMC(pdesc, 1);
set_tx_desc_bmc(pdesc, 1);
}
RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
}
void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw,
u8 *pdesc, bool firstseg,
u8 *pdesc8, bool firstseg,
bool lastseg, struct sk_buff *skb)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
u8 fw_queue = QSLT_BEACON;
__le32 *pdesc = (__le32 *)pdesc8;
dma_addr_t mapping = pci_map_single(rtlpci->pdev,
skb->data, skb->len,
@ -599,60 +601,62 @@ void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw,
"DMA mapping error\n");
return;
}
CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE);
clear_pci_tx_desc_content(pdesc, TX_DESC_SIZE);
if (firstseg)
SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN);
SET_TX_DESC_TX_RATE(pdesc, DESC_RATE1M);
set_tx_desc_tx_rate(pdesc, DESC_RATE1M);
SET_TX_DESC_SEQ(pdesc, 0);
set_tx_desc_seq(pdesc, 0);
SET_TX_DESC_LINIP(pdesc, 0);
set_tx_desc_linip(pdesc, 0);
SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
set_tx_desc_queue_sel(pdesc, fw_queue);
SET_TX_DESC_FIRST_SEG(pdesc, 1);
SET_TX_DESC_LAST_SEG(pdesc, 1);
set_tx_desc_first_seg(pdesc, 1);
set_tx_desc_last_seg(pdesc, 1);
SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) (skb->len));
set_tx_desc_tx_buffer_size(pdesc, (u16)(skb->len));
SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
set_tx_desc_tx_buffer_address(pdesc, mapping);
SET_TX_DESC_RATE_ID(pdesc, 7);
SET_TX_DESC_MACID(pdesc, 0);
set_tx_desc_rate_id(pdesc, 7);
set_tx_desc_macid(pdesc, 0);
SET_TX_DESC_OWN(pdesc, 1);
set_tx_desc_own(pdesc, 1);
SET_TX_DESC_PKT_SIZE(pdesc, (u16) (skb->len));
set_tx_desc_pkt_size(pdesc, (u16)(skb->len));
SET_TX_DESC_FIRST_SEG(pdesc, 1);
SET_TX_DESC_LAST_SEG(pdesc, 1);
set_tx_desc_first_seg(pdesc, 1);
set_tx_desc_last_seg(pdesc, 1);
SET_TX_DESC_OFFSET(pdesc, 0x20);
set_tx_desc_offset(pdesc, 0x20);
SET_TX_DESC_USE_RATE(pdesc, 1);
set_tx_desc_use_rate(pdesc, 1);
if (!ieee80211_is_data_qos(fc)) {
SET_TX_DESC_HWSEQ_EN(pdesc, 1);
SET_TX_DESC_PKT_ID(pdesc, 8);
set_tx_desc_hwseq_en(pdesc, 1);
set_tx_desc_pkt_id(pdesc, 8);
}
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
"H2C Tx Cmd Content", pdesc, TX_DESC_SIZE);
}
void rtl92ce_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
void rtl92ce_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx,
u8 desc_name, u8 *val)
{
__le32 *pdesc = (__le32 *)pdesc8;
if (istx) {
switch (desc_name) {
case HW_DESC_OWN:
wmb();
SET_TX_DESC_OWN(pdesc, 1);
set_tx_desc_own(pdesc, 1);
break;
case HW_DESC_TX_NEXTDESC_ADDR:
SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *) val);
set_tx_desc_next_desc_address(pdesc, *(u32 *)val);
break;
default:
WARN_ONCE(true, "rtl8192ce: ERR txdesc :%d not processed\n",
@ -663,16 +667,16 @@ void rtl92ce_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
switch (desc_name) {
case HW_DESC_RXOWN:
wmb();
SET_RX_DESC_OWN(pdesc, 1);
set_rx_desc_own(pdesc, 1);
break;
case HW_DESC_RXBUFF_ADDR:
SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *) val);
set_rx_desc_buff_addr(pdesc, *(u32 *)val);
break;
case HW_DESC_RXPKT_LEN:
SET_RX_DESC_PKT_LEN(pdesc, *(u32 *) val);
set_rx_desc_pkt_len(pdesc, *(u32 *)val);
break;
case HW_DESC_RXERO:
SET_RX_DESC_EOR(pdesc, 1);
set_rx_desc_eor(pdesc, 1);
break;
default:
WARN_ONCE(true, "rtl8192ce: ERR rxdesc :%d not processed\n",
@ -682,18 +686,19 @@ void rtl92ce_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
}
}
u64 rtl92ce_get_desc(struct ieee80211_hw *hw, u8 *p_desc,
u64 rtl92ce_get_desc(struct ieee80211_hw *hw, u8 *p_desc8,
bool istx, u8 desc_name)
{
u32 ret = 0;
__le32 *p_desc = (__le32 *)p_desc8;
if (istx) {
switch (desc_name) {
case HW_DESC_OWN:
ret = GET_TX_DESC_OWN(p_desc);
ret = get_tx_desc_own(p_desc);
break;
case HW_DESC_TXBUFF_ADDR:
ret = GET_TX_DESC_TX_BUFFER_ADDRESS(p_desc);
ret = get_tx_desc_tx_buffer_address(p_desc);
break;
default:
WARN_ONCE(true, "rtl8192ce: ERR txdesc :%d not processed\n",
@ -703,13 +708,13 @@ u64 rtl92ce_get_desc(struct ieee80211_hw *hw, u8 *p_desc,
} else {
switch (desc_name) {
case HW_DESC_OWN:
ret = GET_RX_DESC_OWN(p_desc);
ret = get_rx_desc_own(p_desc);
break;
case HW_DESC_RXPKT_LEN:
ret = GET_RX_DESC_PKT_LEN(p_desc);
ret = get_rx_desc_pkt_len(p_desc);
break;
case HW_DESC_RXBUFF_ADDR:
ret = GET_RX_DESC_BUFF_ADDR(p_desc);
ret = get_rx_desc_buff_addr(p_desc);
break;
default:
WARN_ONCE(true, "rtl8192ce: ERR rxdesc :%d not processed\n",

749
drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h
View File

@ -14,497 +14,322 @@
#define USB_HWDESC_HEADER_LEN 32
#define CRCLENGTH 4
/* Define a macro that takes a le32 word, converts it to host ordering,
* right shifts by a specified count, creates a mask of the specified
* bit count, and extracts that number of bits.
*/
#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
BIT_LEN_MASK_32(__mask))
/* Define a macro that clears a bit field in an le32 word and
* sets the specified value into that bit field. The resulting
* value remains in le32 ordering; however, it is properly converted
* to host ordering for the clear and set operations before conversion
* back to le32.
*/
#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
(*(__le32 *)(__pdesc) = \
(cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
(~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
(((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
/* macros to read/write various fields in RX or TX descriptors */
#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
#define SET_TX_DESC_OFFSET(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
#define SET_TX_DESC_BMC(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val)
#define SET_TX_DESC_HTC(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val)
#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
#define SET_TX_DESC_LINIP(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
#define SET_TX_DESC_GF(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
#define SET_TX_DESC_OWN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));
}
#define GET_TX_DESC_PKT_SIZE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 0, 16)
#define GET_TX_DESC_OFFSET(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 16, 8)
#define GET_TX_DESC_BMC(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 24, 1)
#define GET_TX_DESC_HTC(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 25, 1)
#define GET_TX_DESC_LAST_SEG(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 26, 1)
#define GET_TX_DESC_FIRST_SEG(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 27, 1)
#define GET_TX_DESC_LINIP(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 28, 1)
#define GET_TX_DESC_NO_ACM(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 29, 1)
#define GET_TX_DESC_GF(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 30, 1)
#define GET_TX_DESC_OWN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 31, 1)
static inline void set_tx_desc_offset(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));
}
#define SET_TX_DESC_MACID(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
#define SET_TX_DESC_BK(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+4, 6, 1, __val)
#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val)
#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+4, 13, 1, __val)
#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+4, 14, 1, __val)
#define SET_TX_DESC_PIFS(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+4, 15, 1, __val)
#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val)
#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+4, 20, 1, __val)
#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+4, 21, 1, __val)
#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+4, 24, 8, __val)
static inline void set_tx_desc_bmc(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits(__pdesc, __val, BIT(24));
}
#define GET_TX_DESC_MACID(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 5, 1)
#define GET_TX_DESC_AGG_BREAK(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 6, 1)
#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 7, 1)
#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 8, 5)
#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 13, 1)
#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
#define GET_TX_DESC_PIFS(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
#define GET_TX_DESC_RATE_ID(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 20, 1)
#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 21, 1)
#define GET_TX_DESC_SEC_TYPE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 22, 2)
#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 24, 8)
static inline void set_tx_desc_htc(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits(__pdesc, __val, BIT(25));
}
#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+8, 0, 6, __val)
#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+8, 6, 6, __val)
#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+8, 14, 2, __val)
#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val)
#define SET_TX_DESC_RAW(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+8, 18, 1, __val)
#define SET_TX_DESC_CCX(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+8, 19, 1, __val)
#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val)
#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+8, 24, 1, __val)
#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+8, 25, 1, __val)
#define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+8, 26, 2, __val)
#define SET_TX_DESC_TX_ANTL(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+8, 28, 2, __val)
#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+8, 30, 2, __val)
static inline void set_tx_desc_last_seg(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits(__pdesc, __val, BIT(26));
}
#define GET_TX_DESC_RTS_RC(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 0, 6)
#define GET_TX_DESC_DATA_RC(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 6, 6)
#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 14, 2)
#define GET_TX_DESC_MORE_FRAG(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 17, 1)
#define GET_TX_DESC_RAW(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 18, 1)
#define GET_TX_DESC_CCX(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 19, 1)
#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 20, 3)
#define GET_TX_DESC_ANTSEL_A(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 24, 1)
#define GET_TX_DESC_ANTSEL_B(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 25, 1)
#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 26, 2)
#define GET_TX_DESC_TX_ANTL(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 28, 2)
#define GET_TX_DESC_TX_ANT_HT(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 30, 2)
static inline void set_tx_desc_first_seg(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits(__pdesc, __val, BIT(27));
}
#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+12, 0, 8, __val)
#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+12, 8, 8, __val)
#define SET_TX_DESC_SEQ(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
#define SET_TX_DESC_PKT_ID(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
static inline void set_tx_desc_linip(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits(__pdesc, __val, BIT(28));
}
#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+12, 0, 8)
#define GET_TX_DESC_TAIL_PAGE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+12, 8, 8)
#define GET_TX_DESC_SEQ(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+12, 16, 12)
#define GET_TX_DESC_PKT_ID(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+12, 28, 4)
static inline void set_tx_desc_own(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits(__pdesc, __val, BIT(31));
}
#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val)
#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 5, 1, __val)
#define SET_TX_DESC_QOS(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val)
#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val)
#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val)
#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 9, 1, __val)
#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val)
#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val)
#define SET_TX_DESC_PORT_ID(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 14, 1, __val)
#define SET_TX_DESC_WAIT_DCTS(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val)
#define SET_TX_DESC_CTS2AP_EN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 19, 1, __val)
#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val)
#define SET_TX_DESC_TX_STBC(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 22, 2, __val)
#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val)
#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val)
#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val)
#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val)
static inline int get_tx_desc_own(__le32 *__pdesc)
{
return le32_get_bits(*(__pdesc), BIT(31));
}
#define GET_TX_DESC_RTS_RATE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 0, 5)
#define GET_TX_DESC_AP_DCFE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 5, 1)
#define GET_TX_DESC_QOS(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 6, 1)
#define GET_TX_DESC_HWSEQ_EN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 7, 1)
#define GET_TX_DESC_USE_RATE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 8, 1)
#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 9, 1)
#define GET_TX_DESC_DISABLE_FB(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 10, 1)
#define GET_TX_DESC_CTS2SELF(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 11, 1)
#define GET_TX_DESC_RTS_ENABLE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 12, 1)
#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 13, 1)
#define GET_TX_DESC_PORT_ID(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 14, 1)
#define GET_TX_DESC_WAIT_DCTS(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 18, 1)
#define GET_TX_DESC_CTS2AP_EN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 19, 1)
#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 20, 2)
#define GET_TX_DESC_TX_STBC(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 22, 2)
#define GET_TX_DESC_DATA_SHORT(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 24, 1)
#define GET_TX_DESC_DATA_BW(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 25, 1)
#define GET_TX_DESC_RTS_SHORT(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 26, 1)
#define GET_TX_DESC_RTS_BW(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 27, 1)
#define GET_TX_DESC_RTS_SC(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 28, 2)
#define GET_TX_DESC_RTS_STBC(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 30, 2)
static inline void set_tx_desc_macid(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0));
}
#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val)
#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val)
#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+20, 17, 1, __val)
#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+20, 18, 6, __val)
#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+20, 24, 8, __val)
static inline void set_tx_desc_agg_break(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 1), __val, BIT(5));
}
#define GET_TX_DESC_TX_RATE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+20, 0, 6)
#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+20, 6, 1)
#define GET_TX_DESC_CCX_TAG(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+20, 7, 1)
#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+20, 8, 5)
#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+20, 13, 4)
#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+20, 17, 1)
#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+20, 18, 6)
#define GET_TX_DESC_USB_TXAGG_NUM(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+20, 24, 8)
static inline void set_tx_desc_rdg_enable(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 1), __val, BIT(7));
}
#define SET_TX_DESC_TXAGC_A(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+24, 0, 5, __val)
#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+24, 5, 5, __val)
#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+24, 10, 1, __val)
#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val)
#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+24, 16, 4, __val)
#define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+24, 20, 4, __val)
#define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+24, 24, 4, __val)
#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+24, 28, 4, __val)
static inline void set_tx_desc_queue_sel(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));
}
#define GET_TX_DESC_TXAGC_A(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+24, 0, 5)
#define GET_TX_DESC_TXAGC_B(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+24, 5, 5)
#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+24, 10, 1)
#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+24, 11, 5)
#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+24, 16, 4)
#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+24, 20, 4)
#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+24, 24, 4)
#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+24, 28, 4)
static inline void set_tx_desc_rate_id(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 1), __val, GENMASK(19, 16));
}
#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
#define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+28, 16, 4, __val)
#define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+28, 20, 4, __val)
#define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+28, 24, 4, __val)
#define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+28, 28, 4, __val)
static inline void set_tx_desc_sec_type(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));
}
#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+28, 0, 16)
#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+28, 16, 4)
#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+28, 20, 4)
#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+28, 24, 4)
#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+28, 28, 4)
static inline void set_tx_desc_more_frag(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 2), __val, BIT(17));
}
#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val)
static inline void set_tx_desc_ampdu_density(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20));
}
#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+36, 0, 32)
static inline void set_tx_desc_seq(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16));
}
#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val)
#define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+44, 0, 32, __val)
static inline void set_tx_desc_pkt_id(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 3), __val, GENMASK(31, 28));
}
#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+40, 0, 32)
#define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+44, 0, 32)
static inline void set_tx_desc_rts_rate(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, GENMASK(4, 0));
}
#define GET_RX_DESC_PKT_LEN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 0, 14)
#define GET_RX_DESC_CRC32(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 14, 1)
#define GET_RX_DESC_ICV(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 15, 1)
#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 16, 4)
#define GET_RX_DESC_SECURITY(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 20, 3)
#define GET_RX_DESC_QOS(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 23, 1)
#define GET_RX_DESC_SHIFT(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 24, 2)
#define GET_RX_DESC_PHYST(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 26, 1)
#define GET_RX_DESC_SWDEC(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 27, 1)
#define GET_RX_DESC_LS(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 28, 1)
#define GET_RX_DESC_FS(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 29, 1)
#define GET_RX_DESC_EOR(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 30, 1)
#define GET_RX_DESC_OWN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc, 31, 1)
static inline void set_tx_desc_qos(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, BIT(6));
}
#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
#define SET_RX_DESC_EOR(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
#define SET_RX_DESC_OWN(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
static inline void set_tx_desc_hwseq_en(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, BIT(7));
}
#define GET_RX_DESC_MACID(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
#define GET_RX_DESC_TID(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 5, 4)
#define GET_RX_DESC_HWRSVD(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 9, 5)
#define GET_RX_DESC_PAGGR(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
#define GET_RX_DESC_FAGGR(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
#define GET_RX_DESC_A1_FIT(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
#define GET_RX_DESC_A2_FIT(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 20, 4)
#define GET_RX_DESC_PAM(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 24, 1)
#define GET_RX_DESC_PWR(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 25, 1)
#define GET_RX_DESC_MD(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 26, 1)
#define GET_RX_DESC_MF(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 27, 1)
#define GET_RX_DESC_TYPE(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 28, 2)
#define GET_RX_DESC_MC(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 30, 1)
#define GET_RX_DESC_BC(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+4, 31, 1)
#define GET_RX_DESC_SEQ(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 0, 12)
#define GET_RX_DESC_FRAG(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 12, 4)
#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 16, 14)
#define GET_RX_DESC_NEXT_IND(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 30, 1)
#define GET_RX_DESC_RSVD(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+8, 31, 1)
static inline void set_tx_desc_use_rate(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, BIT(8));
}
#define GET_RX_DESC_RXMCS(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
#define GET_RX_DESC_RXHT(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
#define GET_RX_DESC_SPLCP(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
#define GET_RX_DESC_BW(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
#define GET_RX_DESC_HTC(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+12, 10, 1)
#define GET_RX_DESC_HWPC_ERR(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+12, 14, 1)
#define GET_RX_DESC_HWPC_IND(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+12, 15, 1)
#define GET_RX_DESC_IV0(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+12, 16, 16)
static inline void set_tx_desc_disable_fb(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, BIT(10));
}
#define GET_RX_DESC_IV1(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+16, 0, 32)
#define GET_RX_DESC_TSFL(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
static inline void set_tx_desc_cts2self(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, BIT(11));
}
#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+24, 0, 32)
#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
SHIFT_AND_MASK_LE(__pdesc+28, 0, 32)
static inline void set_tx_desc_rts_enable(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, BIT(12));
}
#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val)
static inline void set_tx_desc_hw_rts_enable(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, BIT(13));
}
#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET))
static inline void set_tx_desc_tx_sub_carrier(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, GENMASK(21, 20));
}
static inline void set_tx_desc_data_bw(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, BIT(25));
}
static inline void set_tx_desc_rts_short(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, BIT(26));
}
static inline void set_tx_desc_rts_bw(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, BIT(27));
}
static inline void set_tx_desc_rts_sc(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, GENMASK(29, 28));
}
static inline void set_tx_desc_rts_stbc(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 4), __val, GENMASK(31, 30));
}
static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0));
}
static inline void set_tx_desc_data_shortgi(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 5), __val, BIT(6));
}
static inline void set_tx_desc_data_rate_fb_limit(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 5), __val, GENMASK(12, 8));
}
static inline void set_tx_desc_rts_rate_fb_limit(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13));
}
static inline void set_tx_desc_max_agg_num(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 6), __val, GENMASK(15, 11));
}
static inline void set_tx_desc_tx_buffer_size(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));
}
static inline void set_tx_desc_tx_buffer_address(__le32 *__pdesc, u32 __val)
{
*(__pdesc + 8) = cpu_to_le32(__val);
}
static inline int get_tx_desc_tx_buffer_address(__le32 *__pdesc)
{
return le32_to_cpu(*((__pdesc + 8)));
}
static inline void set_tx_desc_next_desc_address(__le32 *__pdesc, u32 __val)
{
*(__pdesc + 10) = cpu_to_le32(__val);
}
static inline int get_rx_desc_pkt_len(__le32 *__pdesc)
{
return le32_get_bits(*(__pdesc), GENMASK(13, 0));
}
static inline int get_rx_desc_crc32(__le32 *__pdesc)
{
return le32_get_bits(*(__pdesc), BIT(14));
}
static inline int get_rx_desc_icv(__le32 *__pdesc)
{
return le32_get_bits(*(__pdesc), BIT(15));
}
static inline int get_rx_desc_drv_info_size(__le32 *__pdesc)
{
return le32_get_bits(*(__pdesc), GENMASK(19, 16));
}
static inline int get_rx_desc_shift(__le32 *__pdesc)
{
return le32_get_bits(*(__pdesc), GENMASK(25, 24));
}
static inline int get_rx_desc_physt(__le32 *__pdesc)
{
return le32_get_bits(*(__pdesc), BIT(26));
}
static inline int get_rx_desc_swdec(__le32 *__pdesc)
{
return le32_get_bits(*(__pdesc), BIT(27));
}
static inline int get_rx_desc_own(__le32 *__pdesc)
{
return le32_get_bits(*(__pdesc), BIT(31));
}
static inline void set_rx_desc_pkt_len(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));
}
static inline void set_rx_desc_eor(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits(__pdesc, __val, BIT(30));
}
static inline void set_rx_desc_own(__le32 *__pdesc, u32 __val)
{
le32p_replace_bits(__pdesc, __val, BIT(31));
}
static inline int get_rx_desc_paggr(__le32 *__pdesc)
{
return le32_get_bits(*((__pdesc + 1)), BIT(14));
}
static inline int get_rx_desc_faggr(__le32 *__pdesc)
{
return le32_get_bits(*((__pdesc + 1)), BIT(15));
}
static inline int get_rx_desc_rxmcs(__le32 *__pdesc)
{
return le32_get_bits(*((__pdesc + 3)), GENMASK(5, 0));
}
static inline int get_rx_desc_rxht(__le32 *__pdesc)
{
return le32_get_bits(*((__pdesc + 3)), BIT(6));
}
static inline int get_rx_desc_splcp(__le32 *__pdesc)
{
return le32_get_bits(*((__pdesc + 3)), BIT(8));
}
static inline int get_rx_desc_bw(__le32 *__pdesc)
{
return le32_get_bits(*((__pdesc + 3)), BIT(9));
}
static inline int get_rx_desc_tsfl(__le32 *__pdesc)
{
return le32_to_cpu(*((__pdesc + 5)));
}
static inline int get_rx_desc_buff_addr(__le32 *__pdesc)
{
return le32_to_cpu(*((__pdesc + 6)));
}
static inline void set_rx_desc_buff_addr(__le32 *__pdesc, u32 __val)
{
*(__pdesc + 6) = cpu_to_le32(__val);
}
static inline void clear_pci_tx_desc_content(__le32 *__pdesc, int _size)
{
memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET));
}
struct rx_fwinfo_92c {
u8 gain_trsw[4];

2
drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c
View File

@ -39,8 +39,6 @@ static int rtl92cu_init_sw_vars(struct ieee80211_hw *hw)
rtlpriv->dm.dm_flag = 0;
rtlpriv->dm.disable_framebursting = false;
rtlpriv->dm.thermalvalue = 0;
rtlpriv->cfg->mod_params->sw_crypto =
rtlpriv->cfg->mod_params->sw_crypto;
/* for firmware buf */
rtlpriv->rtlhal.pfirmware = vzalloc(0x4000);

2
drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c
View File

@ -161,8 +161,6 @@ static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
rtlpriv->cfg->mod_params->sw_crypto =
rtlpriv->cfg->mod_params->sw_crypto;
if (!rtlpriv->psc.inactiveps)
pr_info("Power Save off (module option)\n");
if (!rtlpriv->psc.fwctrl_lps)

4
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c
View File

@ -129,10 +129,6 @@ int rtl8723e_init_sw_vars(struct ieee80211_hw *hw)
rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
rtlpriv->cfg->mod_params->sw_crypto =
rtlpriv->cfg->mod_params->sw_crypto;
rtlpriv->cfg->mod_params->disable_watchdog =
rtlpriv->cfg->mod_params->disable_watchdog;
if (rtlpriv->cfg->mod_params->disable_watchdog)
pr_info("watchdog disabled\n");
rtlpriv->psc.reg_fwctrl_lps = 3;

4
drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c
View File

@ -128,10 +128,6 @@ int rtl8723be_init_sw_vars(struct ieee80211_hw *hw)
rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
rtlpriv->cfg->mod_params->sw_crypto =
rtlpriv->cfg->mod_params->sw_crypto;
rtlpriv->cfg->mod_params->disable_watchdog =
rtlpriv->cfg->mod_params->disable_watchdog;
if (rtlpriv->cfg->mod_params->disable_watchdog)
pr_info("watchdog disabled\n");
rtlpriv->psc.reg_fwctrl_lps = 2;

4
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c
View File

@ -145,10 +145,6 @@ int rtl8821ae_init_sw_vars(struct ieee80211_hw *hw)
rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
rtlpci->int_clear = rtlpriv->cfg->mod_params->int_clear;
rtlpriv->cfg->mod_params->sw_crypto =
rtlpriv->cfg->mod_params->sw_crypto;
rtlpriv->cfg->mod_params->disable_watchdog =
rtlpriv->cfg->mod_params->disable_watchdog;
if (rtlpriv->cfg->mod_params->disable_watchdog)
pr_info("watchdog disabled\n");
rtlpriv->psc.reg_fwctrl_lps = 2;

1
drivers/net/wireless/realtek/rtw88/Makefile
View File

@ -9,6 +9,7 @@ rtw88-y += main.o \
rx.o \
mac.o \
phy.o \
coex.o \
efuse.o \
fw.o \
ps.o \

2507
drivers/net/wireless/realtek/rtw88/coex.c Normal file
View File

File diff suppressed because it is too large Load Diff

369
drivers/net/wireless/realtek/rtw88/coex.h Normal file
View File

@ -0,0 +1,369 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2018-2019 Realtek Corporation
*/
#ifndef __RTW_COEX_H__
#define __RTW_COEX_H__
/* BT profile map bit definition */
#define BPM_HFP BIT(0)
#define BPM_HID BIT(1)
#define BPM_A2DP BIT(2)
#define BPM_PAN BIT(3)
#define COEX_RESP_ACK_BY_WL_FW 0x1
#define COEX_REQUEST_TIMEOUT msecs_to_jiffies(10)
#define COEX_MIN_DELAY 10 /* delay unit in ms */
#define COEX_RFK_TIMEOUT 600 /* RFK timeout in ms */
#define COEX_RF_OFF 0x0
#define COEX_RF_ON 0x1
#define COEX_H2C69_WL_LEAKAP 0xc
#define PARA1_H2C69_DIS_5MS 0x1
#define PARA1_H2C69_EN_5MS 0x0
#define COEX_H2C69_TDMA_SLOT 0xb
#define PARA1_H2C69_TDMA_4SLOT 0xc1
#define PARA1_H2C69_TDMA_2SLOT 0x1
#define TDMA_4SLOT BIT(8)
#define COEX_RSSI_STEP 4
#define COEX_RSSI_HIGH(rssi) \
({ typeof(rssi) __rssi__ = rssi; \
(__rssi__ == COEX_RSSI_STATE_HIGH || \
__rssi__ == COEX_RSSI_STATE_STAY_HIGH ? true : false); })
#define COEX_RSSI_MEDIUM(rssi) \
({ typeof(rssi) __rssi__ = rssi; \
(__rssi__ == COEX_RSSI_STATE_MEDIUM || \
__rssi__ == COEX_RSSI_STATE_STAY_MEDIUM ? true : false); })
#define COEX_RSSI_LOW(rssi) \
({ typeof(rssi) __rssi__ = rssi; \
(__rssi__ == COEX_RSSI_STATE_LOW || \
__rssi__ == COEX_RSSI_STATE_STAY_LOW ? true : false); })
#define GET_COEX_RESP_BT_SCAN_TYPE(payload) \
le64_get_bits(*((__le64 *)(payload)), GENMASK(31, 24))
enum coex_mp_info_op {
BT_MP_INFO_OP_PATCH_VER = 0x00,
BT_MP_INFO_OP_READ_REG = 0x11,
BT_MP_INFO_OP_SUPP_FEAT = 0x2a,
BT_MP_INFO_OP_SUPP_VER = 0x2b,
BT_MP_INFO_OP_SCAN_TYPE = 0x2d,
BT_MP_INFO_OP_LNA_CONSTRAINT = 0x32,
};
enum coex_set_ant_phase {
COEX_SET_ANT_INIT,
COEX_SET_ANT_WONLY,
COEX_SET_ANT_WOFF,
COEX_SET_ANT_2G,
COEX_SET_ANT_5G,
COEX_SET_ANT_POWERON,
COEX_SET_ANT_2G_WLBT,
COEX_SET_ANT_2G_FREERUN,
COEX_SET_ANT_MAX
};
enum coex_runreason {
COEX_RSN_2GSCANSTART = 0,
COEX_RSN_5GSCANSTART = 1,
COEX_RSN_SCANFINISH = 2,
COEX_RSN_2GSWITCHBAND = 3,
COEX_RSN_5GSWITCHBAND = 4,
COEX_RSN_2GCONSTART = 5,
COEX_RSN_5GCONSTART = 6,
COEX_RSN_2GCONFINISH = 7,
COEX_RSN_5GCONFINISH = 8,
COEX_RSN_2GMEDIA = 9,
COEX_RSN_5GMEDIA = 10,
COEX_RSN_MEDIADISCON = 11,
COEX_RSN_BTINFO = 12,
COEX_RSN_LPS = 13,
COEX_RSN_WLSTATUS = 14,
COEX_RSN_MAX
};
enum coex_lte_coex_table_type {
COEX_CTT_WL_VS_LTE,
COEX_CTT_BT_VS_LTE,
};
enum coex_gnt_setup_state {
COEX_GNT_SET_HW_PTA = 0x0,
COEX_GNT_SET_SW_LOW = 0x1,
COEX_GNT_SET_SW_HIGH = 0x3,
};
enum coex_ext_ant_switch_pos_type {
COEX_SWITCH_TO_BT,
COEX_SWITCH_TO_WLG,
COEX_SWITCH_TO_WLA,
COEX_SWITCH_TO_NOCARE,
COEX_SWITCH_TO_WLG_BT,
COEX_SWITCH_TO_MAX
};
enum coex_ext_ant_switch_ctrl_type {
COEX_SWITCH_CTRL_BY_BBSW,
COEX_SWITCH_CTRL_BY_PTA,
COEX_SWITCH_CTRL_BY_ANTDIV,
COEX_SWITCH_CTRL_BY_MAC,
COEX_SWITCH_CTRL_BY_BT,
COEX_SWITCH_CTRL_BY_FW,
COEX_SWITCH_CTRL_MAX
};
enum coex_algorithm {
COEX_ALGO_NOPROFILE = 0,
COEX_ALGO_HFP = 1,
COEX_ALGO_HID = 2,
COEX_ALGO_A2DP = 3,
COEX_ALGO_PAN = 4,
COEX_ALGO_A2DP_HID = 5,
COEX_ALGO_A2DP_PAN = 6,
COEX_ALGO_PAN_HID = 7,
COEX_ALGO_A2DP_PAN_HID = 8,
COEX_ALGO_MAX
};
enum coex_wl_link_mode {
COEX_WLINK_2G1PORT = 0x0,
COEX_WLINK_5G = 0x3,
COEX_WLINK_MAX
};
enum coex_wl2bt_scoreboard {
COEX_SCBD_ACTIVE = BIT(0),
COEX_SCBD_ONOFF = BIT(1),
COEX_SCBD_SCAN = BIT(2),
COEX_SCBD_UNDERTEST = BIT(3),
COEX_SCBD_RXGAIN = BIT(4),
COEX_SCBD_BT_RFK = BIT(5),
COEX_SCBD_WLBUSY = BIT(6),
COEX_SCBD_EXTFEM = BIT(8),
COEX_SCBD_TDMA = BIT(9),
COEX_SCBD_FIX2M = BIT(10),
COEX_SCBD_ALL = GENMASK(15, 0),
};
enum coex_power_save_type {
COEX_PS_WIFI_NATIVE = 0,
COEX_PS_LPS_ON = 1,
COEX_PS_LPS_OFF = 2,
};
enum coex_rssi_state {
COEX_RSSI_STATE_HIGH,
COEX_RSSI_STATE_MEDIUM,
COEX_RSSI_STATE_LOW,
COEX_RSSI_STATE_STAY_HIGH,
COEX_RSSI_STATE_STAY_MEDIUM,
COEX_RSSI_STATE_STAY_LOW,
};
enum coex_notify_type_ips {
COEX_IPS_LEAVE = 0x0,
COEX_IPS_ENTER = 0x1,
};
enum coex_notify_type_lps {
COEX_LPS_DISABLE = 0x0,
COEX_LPS_ENABLE = 0x1,
};
enum coex_notify_type_scan {
COEX_SCAN_FINISH,
COEX_SCAN_START,
COEX_SCAN_START_2G,
COEX_SCAN_START_5G,
};
enum coex_notify_type_switchband {
COEX_NOT_SWITCH,
COEX_SWITCH_TO_24G,
COEX_SWITCH_TO_5G,
COEX_SWITCH_TO_24G_NOFORSCAN,
};
enum coex_notify_type_associate {
COEX_ASSOCIATE_FINISH,
COEX_ASSOCIATE_START,
COEX_ASSOCIATE_5G_FINISH,
COEX_ASSOCIATE_5G_START,
};
enum coex_notify_type_media_status {
COEX_MEDIA_DISCONNECT,
COEX_MEDIA_CONNECT,
COEX_MEDIA_CONNECT_5G,
};
enum coex_bt_status {
COEX_BTSTATUS_NCON_IDLE = 0,
COEX_BTSTATUS_CON_IDLE = 1,
COEX_BTSTATUS_INQ_PAGE = 2,
COEX_BTSTATUS_ACL_BUSY = 3,
COEX_BTSTATUS_SCO_BUSY = 4,
COEX_BTSTATUS_ACL_SCO_BUSY = 5,
COEX_BTSTATUS_MAX
};
enum coex_wl_tput_dir {
COEX_WL_TPUT_TX = 0x0,
COEX_WL_TPUT_RX = 0x1,
COEX_WL_TPUT_MAX
};
enum coex_wl_priority_mask {
COEX_WLPRI_RX_RSP = 2,
COEX_WLPRI_TX_RSP = 3,
COEX_WLPRI_TX_BEACON = 4,
COEX_WLPRI_TX_OFDM = 11,
COEX_WLPRI_TX_CCK = 12,
COEX_WLPRI_TX_BEACONQ = 27,
COEX_WLPRI_RX_CCK = 28,
COEX_WLPRI_RX_OFDM = 29,
COEX_WLPRI_MAX
};
enum coex_commom_chip_setup {
COEX_CSETUP_INIT_HW = 0x0,
COEX_CSETUP_ANT_SWITCH = 0x1,
COEX_CSETUP_GNT_FIX = 0x2,
COEX_CSETUP_GNT_DEBUG = 0x3,
COEX_CSETUP_RFE_TYPE = 0x4,
COEX_CSETUP_COEXINFO_HW = 0x5,
COEX_CSETUP_WL_TX_POWER = 0x6,
COEX_CSETUP_WL_RX_GAIN = 0x7,
COEX_CSETUP_WLAN_ACT_IPS = 0x8,
COEX_CSETUP_MAX
};
enum coex_indirect_reg_type {
COEX_INDIRECT_1700 = 0x0,
COEX_INDIRECT_7C0 = 0x1,
COEX_INDIRECT_MAX
};
enum coex_pstdma_type {
COEX_PSTDMA_FORCE_LPSOFF = 0x0,
COEX_PSTDMA_FORCE_LPSON = 0x1,
COEX_PSTDMA_MAX
};
enum coex_btrssi_type {
COEX_BTRSSI_RATIO = 0x0,
COEX_BTRSSI_DBM = 0x1,
COEX_BTRSSI_MAX
};
struct coex_table_para {
u32 bt;
u32 wl;
};
struct coex_tdma_para {
u8 para[5];
};
struct coex_5g_afh_map {
u32 wl_5g_ch;
u8 bt_skip_ch;
u8 bt_skip_span;
};
struct coex_rf_para {
u8 wl_pwr_dec_lvl;
u8 bt_pwr_dec_lvl;
bool wl_low_gain_en;
u8 bt_lna_lvl;
};
static inline void rtw_coex_set_init(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
chip->ops->coex_set_init(rtwdev);
}
static inline
void rtw_coex_set_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, u8 pos_type)
{
struct rtw_chip_info *chip = rtwdev->chip;
if (!chip->ops->coex_set_ant_switch)
return;
chip->ops->coex_set_ant_switch(rtwdev, ctrl_type, pos_type);
}
static inline void rtw_coex_set_gnt_fix(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
chip->ops->coex_set_gnt_fix(rtwdev);
}
static inline void rtw_coex_set_gnt_debug(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
chip->ops->coex_set_gnt_debug(rtwdev);
}
static inline void rtw_coex_set_rfe_type(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
chip->ops->coex_set_rfe_type(rtwdev);
}
static inline void rtw_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
{
struct rtw_chip_info *chip = rtwdev->chip;
chip->ops->coex_set_wl_tx_power(rtwdev, wl_pwr);
}
static inline
void rtw_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
{
struct rtw_chip_info *chip = rtwdev->chip;
chip->ops->coex_set_wl_rx_gain(rtwdev, low_gain);
}
void rtw_coex_info_response(struct rtw_dev *rtwdev, struct sk_buff *skb);
void rtw_coex_write_indirect_reg(struct rtw_dev *rtwdev, u16 addr,
u32 mask, u32 val);
void rtw_coex_write_scbd(struct rtw_dev *rtwdev, u16 bitpos, bool set);
void rtw_coex_bt_relink_work(struct work_struct *work);
void rtw_coex_bt_reenable_work(struct work_struct *work);
void rtw_coex_defreeze_work(struct work_struct *work);
void rtw_coex_power_on_setting(struct rtw_dev *rtwdev);
void rtw_coex_init_hw_config(struct rtw_dev *rtwdev, bool wifi_only);
void rtw_coex_ips_notify(struct rtw_dev *rtwdev, u8 type);
void rtw_coex_lps_notify(struct rtw_dev *rtwdev, u8 type);
void rtw_coex_scan_notify(struct rtw_dev *rtwdev, u8 type);
void rtw_coex_connect_notify(struct rtw_dev *rtwdev, u8 action);
void rtw_coex_media_status_notify(struct rtw_dev *rtwdev, u8 status);
void rtw_coex_bt_info_notify(struct rtw_dev *rtwdev, u8 *buf, u8 len);
void rtw_coex_wl_fwdbginfo_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length);
void rtw_coex_switchband_notify(struct rtw_dev *rtwdev, u8 type);
void rtw_coex_wl_status_change_notify(struct rtw_dev *rtwdev);
#endif

112
drivers/net/wireless/realtek/rtw88/debug.c
View File

@ -8,6 +8,7 @@
#include "sec.h"
#include "fw.h"
#include "debug.h"
#include "phy.h"
#ifdef CONFIG_RTW88_DEBUGFS
@ -460,6 +461,112 @@ static int rtw_debug_get_rf_dump(struct seq_file *m, void *v)
return 0;
}
static void rtw_print_cck_rate_txt(struct seq_file *m, u8 rate)
{
static const char * const
cck_rate[] = {"1M", "2M", "5.5M", "11M"};
u8 idx = rate - DESC_RATE1M;
seq_printf(m, " CCK_%-5s", cck_rate[idx]);
}
static void rtw_print_ofdm_rate_txt(struct seq_file *m, u8 rate)
{
static const char * const
ofdm_rate[] = {"6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M"};
u8 idx = rate - DESC_RATE6M;
seq_printf(m, " OFDM_%-4s", ofdm_rate[idx]);
}
static void rtw_print_ht_rate_txt(struct seq_file *m, u8 rate)
{
u8 mcs_n = rate - DESC_RATEMCS0;
seq_printf(m, " MCS%-6u", mcs_n);
}
static void rtw_print_vht_rate_txt(struct seq_file *m, u8 rate)
{
u8 idx = rate - DESC_RATEVHT1SS_MCS0;
u8 n_ss, mcs_n;
/* n spatial stream */
n_ss = 1 + idx / 10;
/* MCS n */
mcs_n = idx % 10;
seq_printf(m, " VHT%uSMCS%u", n_ss, mcs_n);
}
static int rtw_debugfs_get_tx_pwr_tbl(struct seq_file *m, void *v)
{
struct rtw_debugfs_priv *debugfs_priv = m->private;
struct rtw_dev *rtwdev = debugfs_priv->rtwdev;
struct rtw_hal *hal = &rtwdev->hal;
void (*print_rate)(struct seq_file *, u8) = NULL;
u8 path, rate;
struct rtw_power_params pwr_param = {0};
u8 bw = hal->current_band_width;
u8 ch = hal->current_channel;
u8 regd = rtwdev->regd.txpwr_regd;
seq_printf(m, "%-4s %-10s %-3s%6s %-4s %4s (%-4s %-4s)\n",
"path", "rate", "pwr", "", "base", "", "byr", "lmt");
mutex_lock(&hal->tx_power_mutex);
for (path = RF_PATH_A; path <= RF_PATH_B; path++) {
/* there is no CCK rates used in 5G */
if (hal->current_band_type == RTW_BAND_5G)
rate = DESC_RATE6M;
else
rate = DESC_RATE1M;
/* now, not support vht 3ss and vht 4ss*/
for (; rate <= DESC_RATEVHT2SS_MCS9; rate++) {
/* now, not support ht 3ss and ht 4ss*/
if (rate > DESC_RATEMCS15 &&
rate < DESC_RATEVHT1SS_MCS0)
continue;
switch (rate) {
case DESC_RATE1M...DESC_RATE11M:
print_rate = rtw_print_cck_rate_txt;
break;
case DESC_RATE6M...DESC_RATE54M:
print_rate = rtw_print_ofdm_rate_txt;
break;
case DESC_RATEMCS0...DESC_RATEMCS15:
print_rate = rtw_print_ht_rate_txt;
break;
case DESC_RATEVHT1SS_MCS0...DESC_RATEVHT2SS_MCS9:
print_rate = rtw_print_vht_rate_txt;
break;
default:
print_rate = NULL;
break;
}
rtw_get_tx_power_params(rtwdev, path, rate, bw,
ch, regd, &pwr_param);
seq_printf(m, "%4c ", path + 'A');
if (print_rate)
print_rate(m, rate);
seq_printf(m, " %3u(0x%02x) %4u %4d (%4d %4d)\n",
hal->tx_pwr_tbl[path][rate],
hal->tx_pwr_tbl[path][rate],
pwr_param.pwr_base,
min_t(s8, pwr_param.pwr_offset,
pwr_param.pwr_limit),
pwr_param.pwr_offset, pwr_param.pwr_limit);
}
}
mutex_unlock(&hal->tx_power_mutex);
return 0;
}
#define rtw_debug_impl_mac(page, addr) \
static struct rtw_debugfs_priv rtw_debug_priv_mac_ ##page = { \
.cb_read = rtw_debug_get_mac_page, \
@ -514,6 +621,10 @@ static struct rtw_debugfs_priv rtw_debug_priv_rf_dump = {
.cb_read = rtw_debug_get_rf_dump,
};
static struct rtw_debugfs_priv rtw_debug_priv_tx_pwr_tbl = {
.cb_read = rtw_debugfs_get_tx_pwr_tbl,
};
static struct rtw_debugfs_priv rtw_debug_priv_write_reg = {
.cb_write = rtw_debugfs_set_write_reg,
};
@ -610,6 +721,7 @@ void rtw_debugfs_init(struct rtw_dev *rtwdev)
rtw_debugfs_add_r(bb_41);
}
rtw_debugfs_add_r(rf_dump);
rtw_debugfs_add_r(tx_pwr_tbl);
}
#endif /* CONFIG_RTW88_DEBUGFS */

135
drivers/net/wireless/realtek/rtw88/fw.c
View File

@ -3,6 +3,7 @@
*/
#include "main.h"
#include "coex.h"
#include "fw.h"
#include "tx.h"
#include "reg.h"
@ -36,18 +37,52 @@ void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb)
c2h = (struct rtw_c2h_cmd *)(skb->data + pkt_offset);
len = skb->len - pkt_offset - 2;
rtw_dbg(rtwdev, RTW_DBG_FW, "recv C2H, id=0x%02x, seq=0x%02x, len=%d\n",
c2h->id, c2h->seq, len);
mutex_lock(&rtwdev->mutex);
switch (c2h->id) {
case C2H_BT_INFO:
rtw_coex_bt_info_notify(rtwdev, c2h->payload, len);
break;
case C2H_WLAN_INFO:
rtw_coex_wl_fwdbginfo_notify(rtwdev, c2h->payload, len);
break;
case C2H_HALMAC:
rtw_fw_c2h_cmd_handle_ext(rtwdev, skb);
break;
default:
break;
}
mutex_unlock(&rtwdev->mutex);
}
void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset,
struct sk_buff *skb)
{
struct rtw_c2h_cmd *c2h;
u8 len;
c2h = (struct rtw_c2h_cmd *)(skb->data + pkt_offset);
len = skb->len - pkt_offset - 2;
*((u32 *)skb->cb) = pkt_offset;
rtw_dbg(rtwdev, RTW_DBG_FW, "recv C2H, id=0x%02x, seq=0x%02x, len=%d\n",
c2h->id, c2h->seq, len);
switch (c2h->id) {
case C2H_BT_MP_INFO:
rtw_coex_info_response(rtwdev, skb);
break;
default:
/* pass offset for further operation */
*((u32 *)skb->cb) = pkt_offset;
skb_queue_tail(&rtwdev->c2h_queue, skb);
ieee80211_queue_work(rtwdev->hw, &rtwdev->c2h_work);
break;
}
}
EXPORT_SYMBOL(rtw_fw_c2h_cmd_rx_irqsafe);
static void rtw_fw_send_h2c_command(struct rtw_dev *rtwdev,
u8 *h2c)
{
@ -181,6 +216,102 @@ void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para)
rtw_fw_send_h2c_packet(rtwdev, h2c_pkt);
}
void rtw_fw_query_bt_info(struct rtw_dev *rtwdev)
{
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_QUERY_BT_INFO);
SET_QUERY_BT_INFO(h2c_pkt, true);
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
}
void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw)
{
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_WL_CH_INFO);
SET_WL_CH_INFO_LINK(h2c_pkt, link);
SET_WL_CH_INFO_CHNL(h2c_pkt, ch);
SET_WL_CH_INFO_BW(h2c_pkt, bw);
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
}
void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev,
struct rtw_coex_info_req *req)
{
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_QUERY_BT_MP_INFO);
SET_BT_MP_INFO_SEQ(h2c_pkt, req->seq);
SET_BT_MP_INFO_OP_CODE(h2c_pkt, req->op_code);
SET_BT_MP_INFO_PARA1(h2c_pkt, req->para1);
SET_BT_MP_INFO_PARA2(h2c_pkt, req->para2);
SET_BT_MP_INFO_PARA3(h2c_pkt, req->para3);
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
}
void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl)
{
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
u8 index = 0 - bt_pwr_dec_lvl;
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_FORCE_BT_TX_POWER);
SET_BT_TX_POWER_INDEX(h2c_pkt, index);
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
}
void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable)
{
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_IGNORE_WLAN_ACTION);
SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, enable);
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
}
void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev,
u8 para1, u8 para2, u8 para3, u8 para4, u8 para5)
{
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_COEX_TDMA_TYPE);
SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, para1);
SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, para2);
SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, para3);
SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, para4);
SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, para5);
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
}
void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data)
{
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_BT_WIFI_CONTROL);
SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, op_code);
SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, *data);
SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, *(data + 1));
SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, *(data + 2));
SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, *(data + 3));
SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, *(data + 4));
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
}
void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si)
{
u8 h2c_pkt[H2C_PKT_SIZE] = {0};

73
drivers/net/wireless/realtek/rtw88/fw.h
View File

@ -35,7 +35,9 @@
enum rtw_c2h_cmd_id {
C2H_BT_INFO = 0x09,
C2H_BT_MP_INFO = 0x0b,
C2H_HW_FEATURE_REPORT = 0x19,
C2H_WLAN_INFO = 0x27,
C2H_HW_FEATURE_DUMP = 0xfd,
C2H_HALMAC = 0xff,
};
@ -71,6 +73,14 @@ enum rtw_fw_rf_type {
FW_RF_MAX_TYPE = 0xF,
};
struct rtw_coex_info_req {
u8 seq;
u8 op_code;
u8 para1;
u8 para2;
u8 para3;
};
struct rtw_iqk_para {
u8 clear;
u8 segment_iqk;
@ -139,6 +149,14 @@ static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id)
#define H2C_CMD_RA_INFO 0x40
#define H2C_CMD_RSSI_MONITOR 0x42
#define H2C_CMD_COEX_TDMA_TYPE 0x60
#define H2C_CMD_QUERY_BT_INFO 0x61
#define H2C_CMD_FORCE_BT_TX_POWER 0x62
#define H2C_CMD_IGNORE_WLAN_ACTION 0x63
#define H2C_CMD_WL_CH_INFO 0x66
#define H2C_CMD_QUERY_BT_MP_INFO 0x67
#define H2C_CMD_BT_WIFI_CONTROL 0x69
#define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0))
@ -191,6 +209,50 @@ static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id)
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
#define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24))
#define SET_QUERY_BT_INFO(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
#define SET_WL_CH_INFO_LINK(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
#define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
#define SET_WL_CH_INFO_BW(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
#define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
#define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
#define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
#define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
#define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
#define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
#define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
#define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
#define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
#define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
#define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
#define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
#define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
#define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
#define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
#define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
#define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
#define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb)
{
@ -200,12 +262,23 @@ static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb)
return (struct rtw_c2h_cmd *)(skb->data + pkt_offset);
}
void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset,
struct sk_buff *skb);
void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb);
void rtw_fw_send_general_info(struct rtw_dev *rtwdev);
void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev);
void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para);
void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev);
void rtw_fw_query_bt_info(struct rtw_dev *rtwdev);
void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw);
void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev,
struct rtw_coex_info_req *req);
void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl);
void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable);
void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev,
u8 para1, u8 para2, u8 para3, u8 para4, u8 para5);
void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data);
void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn);

19
drivers/net/wireless/realtek/rtw88/mac80211.c
View File

@ -7,6 +7,7 @@
#include "tx.h"
#include "fw.h"
#include "mac.h"
#include "coex.h"
#include "ps.h"
#include "reg.h"
#include "debug.h"
@ -253,6 +254,7 @@ static void rtw_ops_bss_info_changed(struct ieee80211_hw *hw,
enum rtw_net_type net_type;
if (conf->assoc) {
rtw_coex_connect_notify(rtwdev, COEX_ASSOCIATE_FINISH);
net_type = RTW_NET_MGD_LINKED;
chip->ops->do_iqk(rtwdev);
@ -262,6 +264,7 @@ static void rtw_ops_bss_info_changed(struct ieee80211_hw *hw,
rtw_add_rsvd_page(rtwdev, RSVD_NULL, true);
rtw_fw_download_rsvd_page(rtwdev, vif);
rtw_send_rsvd_page_h2c(rtwdev);
rtw_coex_media_status_notify(rtwdev, conf->assoc);
} else {
net_type = RTW_NET_NO_LINK;
rtwvif->aid = 0;
@ -469,6 +472,8 @@ static void rtw_ops_sw_scan_start(struct ieee80211_hw *hw,
config |= PORT_SET_MAC_ADDR;
rtw_vif_port_config(rtwdev, rtwvif, config);
rtw_coex_scan_notify(rtwdev, COEX_SCAN_START);
rtw_flag_set(rtwdev, RTW_FLAG_DIG_DISABLE);
rtw_flag_set(rtwdev, RTW_FLAG_SCANNING);
@ -491,6 +496,19 @@ static void rtw_ops_sw_scan_complete(struct ieee80211_hw *hw,
config |= PORT_SET_MAC_ADDR;
rtw_vif_port_config(rtwdev, rtwvif, config);
rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH);
mutex_unlock(&rtwdev->mutex);
}
static void rtw_ops_mgd_prepare_tx(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
u16 duration)
{
struct rtw_dev *rtwdev = hw->priv;
mutex_lock(&rtwdev->mutex);
rtw_coex_connect_notify(rtwdev, COEX_ASSOCIATE_START);
mutex_unlock(&rtwdev->mutex);
}
@ -509,5 +527,6 @@ const struct ieee80211_ops rtw_ops = {
.ampdu_action = rtw_ops_ampdu_action,
.sw_scan_start = rtw_ops_sw_scan_start,
.sw_scan_complete = rtw_ops_sw_scan_complete,
.mgd_prepare_tx = rtw_ops_mgd_prepare_tx,
};
EXPORT_SYMBOL(rtw_ops);

45
drivers/net/wireless/realtek/rtw88/main.c
View File

@ -8,6 +8,7 @@
#include "ps.h"
#include "sec.h"
#include "mac.h"
#include "coex.h"
#include "phy.h"
#include "reg.h"
#include "efuse.h"
@ -149,6 +150,7 @@ static void rtw_watch_dog_work(struct work_struct *work)
struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
watch_dog_work.work);
struct rtw_watch_dog_iter_data data = {};
bool busy_traffic = rtw_flag_check(rtwdev, RTW_FLAG_BUSY_TRAFFIC);
if (!rtw_flag_check(rtwdev, RTW_FLAG_RUNNING))
return;
@ -156,6 +158,14 @@ static void rtw_watch_dog_work(struct work_struct *work)
ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
RTW_WATCH_DOG_DELAY_TIME);
if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
rtw_flag_set(rtwdev, RTW_FLAG_BUSY_TRAFFIC);
else
rtw_flag_clear(rtwdev, RTW_FLAG_BUSY_TRAFFIC);
if (busy_traffic != rtw_flag_check(rtwdev, RTW_FLAG_BUSY_TRAFFIC))
rtw_coex_wl_status_change_notify(rtwdev);
/* reset tx/rx statictics */
rtwdev->stats.tx_unicast = 0;
rtwdev->stats.rx_unicast = 0;
@ -298,6 +308,15 @@ void rtw_set_channel(struct rtw_dev *rtwdev)
chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx);
if (hal->current_band_type == RTW_BAND_5G) {
rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
} else {
if (rtw_flag_check(rtwdev, RTW_FLAG_SCANNING))
rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
else
rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
}
rtw_phy_set_tx_power_level(rtwdev, center_chan);
}
@ -641,6 +660,7 @@ static int rtw_power_on(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_fw_state *fw = &rtwdev->fw;
bool wifi_only;
int ret;
ret = rtw_hci_setup(rtwdev);
@ -684,6 +704,10 @@ static int rtw_power_on(struct rtw_dev *rtwdev)
goto err_off;
}
wifi_only = !rtwdev->efuse.btcoex;
rtw_coex_power_on_setting(rtwdev);
rtw_coex_init_hw_config(rtwdev, wifi_only);
return 0;
err_off:
@ -722,10 +746,15 @@ static void rtw_power_off(struct rtw_dev *rtwdev)
void rtw_core_stop(struct rtw_dev *rtwdev)
{
struct rtw_coex *coex = &rtwdev->coex;
rtw_flag_clear(rtwdev, RTW_FLAG_RUNNING);
rtw_flag_clear(rtwdev, RTW_FLAG_FW_RUNNING);
cancel_delayed_work_sync(&rtwdev->watch_dog_work);
cancel_delayed_work_sync(&coex->bt_relink_work);
cancel_delayed_work_sync(&coex->bt_reenable_work);
cancel_delayed_work_sync(&coex->defreeze_work);
rtw_power_off(rtwdev);
}
@ -876,7 +905,6 @@ static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_hal *hal = &rtwdev->hal;
struct rtw_efuse *efuse = &rtwdev->efuse;
u32 wl_bt_pwr_ctrl;
int ret = 0;
switch (rtw_hci_type(rtwdev)) {
@ -888,9 +916,6 @@ static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
return -EINVAL;
}
wl_bt_pwr_ctrl = rtw_read32(rtwdev, REG_WL_BT_PWR_CTRL);
if (wl_bt_pwr_ctrl & BIT_BT_FUNC_EN)
rtwdev->efuse.btcoex = true;
hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
hal->fab_version = BIT_GET_VENDOR_ID(hal->chip_version) >> 2;
hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
@ -1044,11 +1069,14 @@ static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
efuse->lna_type_5g = 0;
if (efuse->channel_plan == 0xff)
efuse->channel_plan = 0x7f;
if (efuse->rf_board_option == 0xff)
efuse->rf_board_option = 0;
if (efuse->bt_setting & BIT(0))
efuse->share_ant = true;
if (efuse->regd == 0xff)
efuse->regd = 0;
efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
@ -1111,6 +1139,7 @@ EXPORT_SYMBOL(rtw_chip_info_setup);
int rtw_core_init(struct rtw_dev *rtwdev)
{
struct rtw_coex *coex = &rtwdev->coex;
int ret;
INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
@ -1120,8 +1149,12 @@ int rtw_core_init(struct rtw_dev *rtwdev)
INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
INIT_DELAYED_WORK(&rtwdev->lps_work, rtw_lps_work);
INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
skb_queue_head_init(&rtwdev->c2h_queue);
skb_queue_head_init(&rtwdev->coex.queue);
skb_queue_head_init(&rtwdev->tx_report.queue);
spin_lock_init(&rtwdev->dm_lock);
@ -1130,8 +1163,11 @@ int rtw_core_init(struct rtw_dev *rtwdev)
spin_lock_init(&rtwdev->tx_report.q_lock);
mutex_init(&rtwdev->mutex);
mutex_init(&rtwdev->coex.mutex);
mutex_init(&rtwdev->hal.tx_power_mutex);
init_waitqueue_head(&rtwdev->coex.wait);
rtwdev->sec.total_cam_num = 32;
rtwdev->hal.current_channel = 1;
set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map);
@ -1174,6 +1210,7 @@ void rtw_core_deinit(struct rtw_dev *rtwdev)
}
mutex_destroy(&rtwdev->mutex);
mutex_destroy(&rtwdev->coex.mutex);
mutex_destroy(&rtwdev->hal.tx_power_mutex);
}
EXPORT_SYMBOL(rtw_core_deinit);

233
drivers/net/wireless/realtek/rtw88/main.h
View File

@ -310,6 +310,7 @@ enum rtw_flags {
RTW_FLAG_INACTIVE_PS,
RTW_FLAG_LEISURE_PS,
RTW_FLAG_DIG_DISABLE,
RTW_FLAG_BUSY_TRAFFIC,
NUM_OF_RTW_FLAGS,
};
@ -640,6 +641,16 @@ struct rtw_chip_ops {
void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
void (*do_iqk)(struct rtw_dev *rtwdev);
/* for coex */
void (*coex_set_init)(struct rtw_dev *rtwdev);
void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
u8 ctrl_type, u8 pos_type);
void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
};
#define RTW_PWR_POLLING_CNT 20000
@ -852,6 +863,216 @@ struct rtw_chip_info {
const struct rtw_rfe_def *rfe_defs;
u32 rfe_defs_size;
/* coex paras */
u32 coex_para_ver;
u8 bt_desired_ver;
bool scbd_support;
bool new_scbd10_def; /* true: fix 2M(8822c) */
u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
u8 bt_rssi_type;
u8 ant_isolation;
u8 rssi_tolerance;
u8 table_sant_num;
u8 table_nsant_num;
u8 tdma_sant_num;
u8 tdma_nsant_num;
u8 bt_afh_span_bw20;
u8 bt_afh_span_bw40;
u8 afh_5g_num;
u8 wl_rf_para_num;
const u8 *bt_rssi_step;
const u8 *wl_rssi_step;
const struct coex_table_para *table_nsant;
const struct coex_table_para *table_sant;
const struct coex_tdma_para *tdma_sant;
const struct coex_tdma_para *tdma_nsant;
const struct coex_rf_para *wl_rf_para_tx;
const struct coex_rf_para *wl_rf_para_rx;
const struct coex_5g_afh_map *afh_5g;
};
enum rtw_coex_bt_state_cnt {
COEX_CNT_BT_RETRY,
COEX_CNT_BT_REINIT,
COEX_CNT_BT_REENABLE,
COEX_CNT_BT_POPEVENT,
COEX_CNT_BT_SETUPLINK,
COEX_CNT_BT_IGNWLANACT,
COEX_CNT_BT_INQ,
COEX_CNT_BT_PAGE,
COEX_CNT_BT_ROLESWITCH,
COEX_CNT_BT_AFHUPDATE,
COEX_CNT_BT_INFOUPDATE,
COEX_CNT_BT_IQK,
COEX_CNT_BT_IQKFAIL,
COEX_CNT_BT_MAX
};
enum rtw_coex_wl_state_cnt {
COEX_CNT_WL_CONNPKT,
COEX_CNT_WL_COEXRUN,
COEX_CNT_WL_NOISY0,
COEX_CNT_WL_NOISY1,
COEX_CNT_WL_NOISY2,
COEX_CNT_WL_5MS_NOEXTEND,
COEX_CNT_WL_FW_NOTIFY,
COEX_CNT_WL_MAX
};
struct rtw_coex_rfe {
bool ant_switch_exist;
bool ant_switch_diversity;
bool ant_switch_with_bt;
u8 rfe_module_type;
u8 ant_switch_polarity;
/* true if WLG at BTG, else at WLAG */
bool wlg_at_btg;
};
struct rtw_coex_dm {
bool cur_ps_tdma_on;
bool cur_wl_rx_low_gain_en;
u8 reason;
u8 bt_rssi_state[4];
u8 wl_rssi_state[4];
u8 wl_ch_info[3];
u8 cur_ps_tdma;
u8 cur_table;
u8 ps_tdma_para[5];
u8 cur_bt_pwr_lvl;
u8 cur_bt_lna_lvl;
u8 cur_wl_pwr_lvl;
u8 bt_status;
u32 cur_ant_pos_type;
u32 cur_switch_status;
u32 setting_tdma;
};
#define COEX_BTINFO_SRC_WL_FW 0x0
#define COEX_BTINFO_SRC_BT_RSP 0x1
#define COEX_BTINFO_SRC_BT_ACT 0x2
#define COEX_BTINFO_SRC_BT_IQK 0x3
#define COEX_BTINFO_SRC_BT_SCBD 0x4
#define COEX_BTINFO_SRC_MAX 0x5
#define COEX_INFO_FTP BIT(7)
#define COEX_INFO_A2DP BIT(6)
#define COEX_INFO_HID BIT(5)
#define COEX_INFO_SCO_BUSY BIT(4)
#define COEX_INFO_ACL_BUSY BIT(3)
#define COEX_INFO_INQ_PAGE BIT(2)
#define COEX_INFO_SCO_ESCO BIT(1)
#define COEX_INFO_CONNECTION BIT(0)
#define COEX_BTINFO_LENGTH_MAX 10
struct rtw_coex_stat {
bool bt_disabled;
bool bt_disabled_pre;
bool bt_link_exist;
bool bt_whck_test;
bool bt_inq_page;
bool bt_inq;
bool bt_page;
bool bt_ble_voice;
bool bt_ble_exist;
bool bt_hfp_exist;
bool bt_a2dp_exist;
bool bt_hid_exist;
bool bt_pan_exist; /* PAN or OPP */
bool bt_opp_exist; /* OPP only */
bool bt_acl_busy;
bool bt_fix_2M;
bool bt_setup_link;
bool bt_multi_link;
bool bt_a2dp_sink;
bool bt_a2dp_active;
bool bt_reenable;
bool bt_ble_scan_en;
bool bt_init_scan;
bool bt_slave;
bool bt_418_hid_exist;
bool bt_mailbox_reply;
bool wl_under_lps;
bool wl_under_ips;
bool wl_hi_pri_task1;
bool wl_hi_pri_task2;
bool wl_force_lps_ctrl;
bool wl_gl_busy;
bool wl_linkscan_proc;
bool wl_ps_state_fail;
bool wl_tx_limit_en;
bool wl_ampdu_limit_en;
bool wl_connected;
bool wl_slot_extend;
bool wl_cck_lock;
bool wl_cck_lock_pre;
bool wl_cck_lock_ever;
u32 bt_supported_version;
u32 bt_supported_feature;
s8 bt_rssi;
u8 kt_ver;
u8 gnt_workaround_state;
u8 tdma_timer_base;
u8 bt_profile_num;
u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
u8 bt_info_lb2;
u8 bt_info_lb3;
u8 bt_info_hb0;
u8 bt_info_hb1;
u8 bt_info_hb2;
u8 bt_info_hb3;
u8 bt_ble_scan_type;
u8 bt_hid_pair_num;
u8 bt_hid_slot;
u8 bt_a2dp_bitpool;
u8 bt_iqk_state;
u8 wl_noisy_level;
u8 wl_fw_dbg_info[10];
u8 wl_fw_dbg_info_pre[10];
u8 wl_coex_mode;
u8 ampdu_max_time;
u8 wl_tput_dir;
u16 score_board;
u16 retry_limit;
/* counters to record bt states */
u32 cnt_bt[COEX_CNT_BT_MAX];
/* counters to record wifi states */
u32 cnt_wl[COEX_CNT_WL_MAX];
u32 darfrc;
u32 darfrch;
};
struct rtw_coex {
/* protects coex info request section */
struct mutex mutex;
struct sk_buff_head queue;
wait_queue_head_t wait;
bool under_5g;
bool stop_dm;
bool freeze;
bool freerun;
bool wl_rf_off;
struct rtw_coex_stat stat;
struct rtw_coex_dm dm;
struct rtw_coex_rfe rfe;
struct delayed_work bt_relink_work;
struct delayed_work bt_reenable_work;
struct delayed_work defreeze_work;
};
#define DACK_MSBK_BACKUP_NUM 0xf
@ -861,6 +1082,16 @@ struct rtw_dm_info {
u32 cck_fa_cnt;
u32 ofdm_fa_cnt;
u32 total_fa_cnt;
u32 cck_ok_cnt;
u32 cck_err_cnt;
u32 ofdm_ok_cnt;
u32 ofdm_err_cnt;
u32 ht_ok_cnt;
u32 ht_err_cnt;
u32 vht_ok_cnt;
u32 vht_err_cnt;
u8 min_rssi;
u8 pre_min_rssi;
u16 fa_history[4];
@ -888,6 +1119,7 @@ struct rtw_efuse {
u8 addr[ETH_ALEN];
u8 channel_plan;
u8 country_code[2];
u8 rf_board_option;
u8 rfe_option;
u8 thermal_meter;
u8 crystal_cap;
@ -1047,6 +1279,7 @@ struct rtw_dev {
struct rtw_regulatory regd;
struct rtw_dm_info dm_info;
struct rtw_coex coex;
/* ensures exclusive access from mac80211 callbacks */
struct mutex mutex;

72
drivers/net/wireless/realtek/rtw88/pci.c
View File

@ -8,6 +8,7 @@
#include "pci.h"
#include "tx.h"
#include "rx.h"
#include "fw.h"
#include "debug.h"
static u32 rtw_pci_tx_queue_idx_addr[] = {
@ -206,6 +207,23 @@ static int rtw_pci_reset_rx_desc(struct rtw_dev *rtwdev, struct sk_buff *skb,
return 0;
}
static void rtw_pci_sync_rx_desc_device(struct rtw_dev *rtwdev, dma_addr_t dma,
struct rtw_pci_rx_ring *rx_ring,
u32 idx, u32 desc_sz)
{
struct device *dev = rtwdev->dev;
struct rtw_pci_rx_buffer_desc *buf_desc;
int buf_sz = RTK_PCI_RX_BUF_SIZE;
dma_sync_single_for_device(dev, dma, buf_sz, DMA_FROM_DEVICE);
buf_desc = (struct rtw_pci_rx_buffer_desc *)(rx_ring->r.head +
idx * desc_sz);
memset(buf_desc, 0, sizeof(*buf_desc));
buf_desc->buf_size = cpu_to_le16(RTK_PCI_RX_BUF_SIZE);
buf_desc->dma = cpu_to_le32(dma);
}
static int rtw_pci_init_rx_ring(struct rtw_dev *rtwdev,
struct rtw_pci_rx_ring *rx_ring,
u8 desc_size, u32 len)
@ -765,6 +783,7 @@ static void rtw_pci_rx_isr(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci,
u32 pkt_offset;
u32 pkt_desc_sz = chip->rx_pkt_desc_sz;
u32 buf_desc_sz = chip->rx_buf_desc_sz;
u32 new_len;
u8 *rx_desc;
dma_addr_t dma;
@ -783,8 +802,8 @@ static void rtw_pci_rx_isr(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci,
rtw_pci_dma_check(rtwdev, ring, cur_rp);
skb = ring->buf[cur_rp];
dma = *((dma_addr_t *)skb->cb);
pci_unmap_single(rtwpci->pdev, dma, RTK_PCI_RX_BUF_SIZE,
PCI_DMA_FROMDEVICE);
dma_sync_single_for_cpu(rtwdev->dev, dma, RTK_PCI_RX_BUF_SIZE,
DMA_FROM_DEVICE);
rx_desc = skb->data;
chip->ops->query_rx_desc(rtwdev, rx_desc, &pkt_stat, &rx_status);
@ -792,40 +811,32 @@ static void rtw_pci_rx_isr(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci,
pkt_offset = pkt_desc_sz + pkt_stat.drv_info_sz +
pkt_stat.shift;
/* allocate a new skb for this frame,
* discard the frame if none available
*/
new_len = pkt_stat.pkt_len + pkt_offset;
new = dev_alloc_skb(new_len);
if (WARN_ONCE(!new, "rx routine starvation\n"))
goto next_rp;
/* put the DMA data including rx_desc from phy to new skb */
skb_put_data(new, skb->data, new_len);
if (pkt_stat.is_c2h) {
/* keep rx_desc, halmac needs it */
skb_put(skb, pkt_stat.pkt_len + pkt_offset);
/* pass offset for further operation */
*((u32 *)skb->cb) = pkt_offset;
skb_queue_tail(&rtwdev->c2h_queue, skb);
ieee80211_queue_work(rtwdev->hw, &rtwdev->c2h_work);
rtw_fw_c2h_cmd_rx_irqsafe(rtwdev, pkt_offset, new);
} else {
/* remove rx_desc, maybe use skb_pull? */
skb_put(skb, pkt_stat.pkt_len);
skb_reserve(skb, pkt_offset);
/* remove rx_desc */
skb_pull(new, pkt_offset);
/* alloc a smaller skb to mac80211 */
new = dev_alloc_skb(pkt_stat.pkt_len);
if (!new) {
new = skb;
} else {
skb_put_data(new, skb->data, skb->len);
dev_kfree_skb_any(skb);
}
/* TODO: merge into rx.c */
rtw_rx_stats(rtwdev, pkt_stat.vif, skb);
rtw_rx_stats(rtwdev, pkt_stat.vif, new);
memcpy(new->cb, &rx_status, sizeof(rx_status));
ieee80211_rx_irqsafe(rtwdev->hw, new);
}
/* skb delivered to mac80211, alloc a new one in rx ring */
new = dev_alloc_skb(RTK_PCI_RX_BUF_SIZE);
if (WARN(!new, "rx routine starvation\n"))
return;
ring->buf[cur_rp] = new;
rtw_pci_reset_rx_desc(rtwdev, new, ring, cur_rp, buf_desc_sz);
next_rp:
/* new skb delivered to mac80211, re-enable original skb DMA */
rtw_pci_sync_rx_desc_device(rtwdev, dma, ring, cur_rp,
buf_desc_sz);
/* host read next element in ring */
if (++cur_rp >= ring->r.len)
@ -977,7 +988,6 @@ static void rtw_pci_phy_cfg(struct rtw_dev *rtwdev)
u16 cut;
u16 value;
u16 offset;
u16 ip_sel;
int i;
cut = BIT(0) << rtwdev->hal.cut_version;
@ -990,7 +1000,6 @@ static void rtw_pci_phy_cfg(struct rtw_dev *rtwdev)
break;
offset = para->offset;
value = para->value;
ip_sel = para->ip_sel;
if (para->ip_sel == RTW_IP_SEL_PHY)
rtw_mdio_write(rtwdev, offset, value, true);
else
@ -1005,7 +1014,6 @@ static void rtw_pci_phy_cfg(struct rtw_dev *rtwdev)
break;
offset = para->offset;
value = para->value;
ip_sel = para->ip_sel;
if (para->ip_sel == RTW_IP_SEL_PHY)
rtw_mdio_write(rtwdev, offset, value, false);
else

15
drivers/net/wireless/realtek/rtw88/phy.c
View File

@ -29,15 +29,6 @@ struct phy_pg_cfg_pair {
u32 data;
};
struct txpwr_lmt_cfg_pair {
u8 regd;
u8 band;
u8 bw;
u8 rs;
u8 ch;
s8 txpwr_lmt;
};
static const u32 db_invert_table[12][8] = {
{10, 13, 16, 20,
25, 32, 40, 50},
@ -1267,10 +1258,8 @@ static void rtw_xref_txpwr_lmt(struct rtw_dev *rtwdev)
void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev,
const struct rtw_table *tbl)
{
const struct txpwr_lmt_cfg_pair *p = tbl->data;
const struct txpwr_lmt_cfg_pair *end = p + tbl->size / 6;
BUILD_BUG_ON(sizeof(struct txpwr_lmt_cfg_pair) != sizeof(u8) * 6);
const struct rtw_txpwr_lmt_cfg_pair *p = tbl->data;
const struct rtw_txpwr_lmt_cfg_pair *end = p + tbl->size;
for (; p < end; p++) {
rtw_phy_set_tx_power_limit(rtwdev, p->regd, p->band,

9
drivers/net/wireless/realtek/rtw88/phy.h
View File

@ -45,6 +45,15 @@ void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel);
void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal);
void rtw_phy_tx_power_limit_config(struct rtw_hal *hal);
struct rtw_txpwr_lmt_cfg_pair {
u8 regd;
u8 band;
u8 bw;
u8 rs;
u8 ch;
s8 txpwr_lmt;
};
#define RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, path) \
const struct rtw_table name ## _tbl = { \
.data = name, \

9
drivers/net/wireless/realtek/rtw88/ps.c
View File

@ -6,6 +6,7 @@
#include "fw.h"
#include "ps.h"
#include "mac.h"
#include "coex.h"
#include "debug.h"
static int rtw_ips_pwr_up(struct rtw_dev *rtwdev)
@ -26,6 +27,8 @@ int rtw_enter_ips(struct rtw_dev *rtwdev)
{
rtw_flag_set(rtwdev, RTW_FLAG_INACTIVE_PS);
rtw_coex_ips_notify(rtwdev, COEX_IPS_ENTER);
rtw_core_stop(rtwdev);
return 0;
@ -53,6 +56,8 @@ int rtw_leave_ips(struct rtw_dev *rtwdev)
rtw_iterate_vifs_atomic(rtwdev, rtw_restore_port_cfg_iter, rtwdev);
rtw_coex_ips_notify(rtwdev, COEX_IPS_LEAVE);
return 0;
}
@ -67,6 +72,8 @@ static void rtw_leave_lps_core(struct rtw_dev *rtwdev)
rtw_fw_set_pwr_mode(rtwdev);
rtw_flag_clear(rtwdev, RTW_FLAG_LEISURE_PS);
rtw_coex_lps_notify(rtwdev, COEX_LPS_DISABLE);
}
static void rtw_enter_lps_core(struct rtw_dev *rtwdev)
@ -78,6 +85,8 @@ static void rtw_enter_lps_core(struct rtw_dev *rtwdev)
conf->rlbm = 1;
conf->smart_ps = 2;
rtw_coex_lps_notify(rtwdev, COEX_LPS_ENABLE);
rtw_fw_set_pwr_mode(rtwdev);
rtw_flag_set(rtwdev, RTW_FLAG_LEISURE_PS);
}

62
drivers/net/wireless/realtek/rtw88/reg.h
View File

@ -37,17 +37,28 @@
#define REG_GPIO_MUXCFG 0x0040
#define BIT_FSPI_EN BIT(19)
#define BIT_BT_AOD_GPIO3 BIT(9)
#define BIT_BT_PTA_EN BIT(5)
#define BIT_WLRFE_4_5_EN BIT(2)
#define REG_LED_CFG 0x004C
#define BIT_LNAON_SEL_EN BIT(26)
#define BIT_PAPE_SEL_EN BIT(25)
#define BIT_DPDT_WL_SEL BIT(24)
#define BIT_DPDT_SEL_EN BIT(23)
#define REG_PAD_CTRL1 0x0064
#define BIT_PAPE_WLBT_SEL BIT(29)
#define BIT_LNAON_WLBT_SEL BIT(28)
#define BIT_BTGP_JTAG_EN BIT(24)
#define BIT_BTGP_SPI_EN BIT(20)
#define BIT_LED1DIS BIT(15)
#define BIT_SW_DPDT_SEL_DATA BIT(0)
#define REG_WL_BT_PWR_CTRL 0x0068
#define BIT_BT_FUNC_EN BIT(18)
#define BIT_BT_DIG_CLK_EN BIT(8)
#define REG_SYS_SDIO_CTRL 0x0070
#define BIT_DBG_GNT_WL_BT BIT(27)
#define BIT_LTE_MUX_CTRL_PATH BIT(26)
#define REG_HCI_OPT_CTRL 0x0074
#define REG_MCUFW_CTRL 0x0080
@ -70,6 +81,8 @@
#define FW_READY_MASK 0xffff
#define REG_WLRF1 0x00EC
#define REG_WIFI_BT_INFO 0x00AA
#define BIT_BT_INT_EN BIT(15)
#define REG_SYS_CFG1 0x00F0
#define BIT_RTL_ID BIT(23)
#define BIT_RF_TYPE_ID BIT(27)
@ -187,6 +200,7 @@
#define REG_LIFETIME_EN 0x0426
#define BIT_BA_PARSER_EN BIT(5)
#define REG_SPEC_SIFS 0x0428
#define REG_RETRY_LIMIT 0x042a
#define REG_DARFRC 0x0430
#define REG_DARFRCH 0x0434
#define REG_RARFRCH 0x043C
@ -199,18 +213,25 @@
#define REG_AMPDU_MAX_TIME_V1 0x0455
#define REG_BCNQ1_BDNY_V1 0x0456
#define REG_TX_HANG_CTRL 0x045E
#define BIT_EN_GNT_BT_AWAKE BIT(3)
#define BIT_EN_EOF_V1 BIT(2)
#define REG_DATA_SC 0x0483
#define REG_ARFR4 0x049C
#define BIT_WL_RFK BIT(0)
#define REG_ARFRH4 0x04A0
#define REG_ARFR5 0x04A4
#define REG_ARFRH5 0x04A8
#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
#define BIT_PRE_TX_CMD BIT(6)
#define REG_QUEUE_CTRL 0x04C6
#define BIT_PTA_WL_TX_EN BIT(4)
#define BIT_PTA_EDCCA_EN BIT(5)
#define REG_PROT_MODE_CTRL 0x04C8
#define REG_BAR_MODE_CTRL 0x04CC
#define REG_PRECNT_CTRL 0x04E5
#define BIT_BTCCA_CTRL (BIT(0) | BIT(1))
#define BIT_EN_PRECNT BIT(11)
#define REG_DUMMY_PAGE4_V1 0x04FC
#define REG_EDCA_VO_PARAM 0x0500
#define REG_EDCA_VI_PARAM 0x0504
@ -297,11 +318,34 @@
#define REG_RXFLTMAP0 0x06A0
#define REG_RXFLTMAP1 0x06A2
#define REG_RXFLTMAP2 0x06A4
#define REG_BT_COEX_TABLE0 0x06C0
#define REG_BT_COEX_TABLE1 0x06C4
#define REG_BT_COEX_BRK_TABLE 0x06C8
#define REG_BT_COEX_TABLE_H 0x06CC
#define REG_BT_COEX_TABLE_H1 0x06CD
#define REG_BT_COEX_TABLE_H2 0x06CE
#define REG_BT_COEX_TABLE_H3 0x06CF
#define REG_BBPSF_CTRL 0x06DC
#define REG_BT_COEX_V2 0x0763
#define BIT_GNT_BT_POLARITY BIT(4)
#define BIT_LTE_COEX_EN BIT(7)
#define REG_BT_STAT_CTRL 0x0778
#define REG_BT_TDMA_TIME 0x0790
#define REG_WMAC_OPTION_FUNCTION 0x07D0
#define REG_WMAC_OPTION_FUNCTION_1 0x07D4
#define REG_RX_GAIN_EN 0x081c
#define REG_RFE_CTRL_E 0x0974
#define REG_RFE_CTRL8 0x0cb4
#define BIT_MASK_RFE_SEL89 GENMASK(7, 0)
#define REG_RFE_INV8 0x0cbd
#define BIT_MASK_RFE_INV89 GENMASK(1, 0)
#define REG_RFE_INV16 0x0cbe
#define BIT_RFE_BUF_EN BIT(3)
#define REG_ANAPAR_XTAL_0 0x1040
#define REG_CPU_DMEM_CON 0x1080
#define BIT_WL_PLATFORM_RST BIT(16)
@ -407,15 +451,33 @@
#define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1
#define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1
#define REG_IGN_GNT_BT1 0x1860
#define REG_RFESEL_CTRL 0x1990
#define REG_NOMASK_TXBT 0x1ca7
#define REG_ANAPAR 0x1c30
#define BIT_ANAPAR_BTPS BIT(22)
#define REG_RSTB_SEL 0x1c38
#define REG_IGN_GNTBT4 0x4160
#define RF_MODOPT 0x01
#define RF_DTXLOK 0x08
#define RF_CFGCH 0x18
#define RF_RCK 0x1d
#define RF_LUTWA 0x33
#define RF_LUTWD1 0x3e
#define RF_LUTWD0 0x3f
#define RF_XTALX2 0xb8
#define RF_MALSEL 0xbe
#define RF_RCKD 0xde
#define RF_LUTDBG 0xdf
#define RF_LUTWE2 0xee
#define RF_LUTWE 0xef
#define LTE_COEX_CTRL 0x38
#define LTE_WL_TRX_CTRL 0xa0
#define LTE_BT_TRX_CTRL 0xa4
#endif

462
drivers/net/wireless/realtek/rtw88/rtw8822b.c
View File

@ -3,6 +3,7 @@
*/
#include "main.h"
#include "coex.h"
#include "fw.h"
#include "tx.h"
#include "rx.h"
@ -31,6 +32,7 @@ static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
map = (struct rtw8822b_efuse *)log_map;
efuse->rfe_option = map->rfe_option;
efuse->rf_board_option = map->rf_board_option;
efuse->crystal_cap = map->xtal_k;
efuse->pa_type_2g = map->pa_type;
efuse->pa_type_5g = map->pa_type;
@ -104,24 +106,6 @@ static void rtw8822b_phy_set_param(struct rtw_dev *rtwdev)
rtw_phy_init(rtwdev);
rtw8822b_phy_rfe_init(rtwdev);
/* wifi path controller */
rtw_write32_mask(rtwdev, 0x70, 0x4000000, 1);
/* BB control */
rtw_write32_mask(rtwdev, 0x4c, 0x01800000, 0x2);
/* antenna mux switch */
rtw_write8(rtwdev, 0x974, 0xff);
rtw_write32_mask(rtwdev, 0x1990, 0x300, 0);
rtw_write32_mask(rtwdev, 0xcbc, 0x80000, 0x0);
/* SW control */
rtw_write8(rtwdev, 0xcb4, 0x77);
/* switch to WL side controller and gnt_wl gnt_bt debug signal */
rtw_write32_mask(rtwdev, 0x70, 0xff000000, 0x0e);
/* gnt_wl = 1, gnt_bt = 0 */
rtw_write32(rtwdev, 0x1704, 0x7700);
rtw_write32(rtwdev, 0x1700, 0xc00f0038);
/* switch for WL 2G */
rtw_write8(rtwdev, 0xcbd, 0x2);
}
#define WLAN_SLOT_TIME 0x09
@ -960,6 +944,7 @@ static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev)
u32 cck_enable;
u32 cck_fa_cnt;
u32 ofdm_fa_cnt;
u32 crc32_cnt;
cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28);
cck_fa_cnt = rtw_read16(rtwdev, 0xa5c);
@ -970,6 +955,19 @@ static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev)
dm_info->total_fa_cnt = ofdm_fa_cnt;
dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
crc32_cnt = rtw_read32(rtwdev, 0xf04);
dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
crc32_cnt = rtw_read32(rtwdev, 0xf14);
dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
crc32_cnt = rtw_read32(rtwdev, 0xf10);
dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
crc32_cnt = rtw_read32(rtwdev, 0xf0c);
dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
rtw_write32_set(rtwdev, 0x9a4, BIT(17));
rtw_write32_clr(rtwdev, 0x9a4, BIT(17));
rtw_write32_clr(rtwdev, 0xa2c, BIT(15));
@ -997,12 +995,260 @@ static void rtw8822b_do_iqk(struct rtw_dev *rtwdev)
rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(0, 7));
iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
rtw_dbg(rtwdev, RTW_DBG_PHY,
"iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
counter, reload, ++do_iqk_cnt, iqk_fail_mask);
}
static void rtw8822b_coex_cfg_init(struct rtw_dev *rtwdev)
{
/* enable TBTT nterrupt */
rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
/* BT report packet sample rate */
/* 0x790[5:0]=0x5 */
rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05);
/* enable BT counter statistics */
rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
/* enable PTA (3-wire function form BT side) */
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3);
/* enable PTA (tx/rx signal form WiFi side) */
rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
/* wl tx signal to PTA not case EDCCA */
rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
/* GNT_BT=1 while select both */
rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
}
static void rtw8822b_coex_cfg_ant_switch(struct rtw_dev *rtwdev,
u8 ctrl_type, u8 pos_type)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_dm *coex_dm = &coex->dm;
struct rtw_coex_rfe *coex_rfe = &coex->rfe;
bool polarity_inverse;
u8 regval = 0;
if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status)
return;
coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type;
if (coex_rfe->ant_switch_diversity &&
ctrl_type == COEX_SWITCH_CTRL_BY_BBSW)
ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV;
polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
switch (ctrl_type) {
default:
case COEX_SWITCH_CTRL_BY_BBSW:
/* 0x4c[23] = 0 */
rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
/* 0x4c[24] = 1 */
rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77);
if (pos_type == COEX_SWITCH_TO_WLG_BT) {
if (coex_rfe->rfe_module_type != 0x4 &&
coex_rfe->rfe_module_type != 0x2)
regval = 0x3;
else
regval = (!polarity_inverse ? 0x2 : 0x1);
} else if (pos_type == COEX_SWITCH_TO_WLG) {
regval = (!polarity_inverse ? 0x2 : 0x1);
} else {
regval = (!polarity_inverse ? 0x1 : 0x2);
}
rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
break;
case COEX_SWITCH_CTRL_BY_PTA:
/* 0x4c[23] = 0 */
rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
/* 0x4c[24] = 1 */
rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
/* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66);
regval = (!polarity_inverse ? 0x2 : 0x1);
rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
break;
case COEX_SWITCH_CTRL_BY_ANTDIV:
/* 0x4c[23] = 0 */
rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
/* 0x4c[24] = 1 */
rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88);
break;
case COEX_SWITCH_CTRL_BY_MAC:
/* 0x4c[23] = 1 */
rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1);
regval = (!polarity_inverse ? 0x0 : 0x1);
rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval);
break;
case COEX_SWITCH_CTRL_BY_FW:
/* 0x4c[23] = 0 */
rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
/* 0x4c[24] = 1 */
rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
break;
case COEX_SWITCH_CTRL_BY_BT:
/* 0x4c[23] = 0 */
rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
/* 0x4c[24] = 0 */
rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0);
break;
}
}
static void rtw8822b_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
{
}
static void rtw8822b_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
{
rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
}
static void rtw8822b_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_rfe *coex_rfe = &coex->rfe;
struct rtw_efuse *efuse = &rtwdev->efuse;
bool is_ext_fem = false;
coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
coex_rfe->ant_switch_polarity = 0;
coex_rfe->ant_switch_diversity = false;
if (coex_rfe->rfe_module_type == 0x12 ||
coex_rfe->rfe_module_type == 0x15 ||
coex_rfe->rfe_module_type == 0x16)
coex_rfe->ant_switch_exist = false;
else
coex_rfe->ant_switch_exist = true;
if (coex_rfe->rfe_module_type == 2 ||
coex_rfe->rfe_module_type == 4) {
rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, true);
is_ext_fem = true;
} else {
rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, false);
}
coex_rfe->wlg_at_btg = false;
if (efuse->share_ant &&
coex_rfe->ant_switch_exist && !is_ext_fem)
coex_rfe->ant_switch_with_bt = true;
else
coex_rfe->ant_switch_with_bt = false;
/* Ext switch buffer mux */
rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff);
rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0);
rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0);
/* Disable LTE Coex Function in WiFi side */
rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0);
/* BTC_CTT_WL_VS_LTE */
rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
/* BTC_CTT_BT_VS_LTE */
rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
}
static void rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_dm *coex_dm = &coex->dm;
static const u16 reg_addr[] = {0xc58, 0xe58};
static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8};
u8 i, pwr;
if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
return;
coex_dm->cur_wl_pwr_lvl = wl_pwr;
if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power))
coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1;
pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl];
for (i = 0; i < ARRAY_SIZE(reg_addr); i++)
rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr);
}
static void rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_dm *coex_dm = &coex->dm;
/* WL Rx Low gain on */
static const u32 wl_rx_low_gain_on[] = {
0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003,
0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003,
0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003,
0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003,
0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003,
0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003,
0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003,
0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003,
0x007e0403
};
/* WL Rx Low gain off */
static const u32 wl_rx_low_gain_off[] = {
0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003,
0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003,
0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003,
0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003,
0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003,
0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003,
0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003,
0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003,
0x007e0403
};
u8 i;
if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
return;
coex_dm->cur_wl_rx_low_gain_en = low_gain;
if (coex_dm->cur_wl_rx_low_gain_en) {
for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++)
rtw_write32(rtwdev, REG_RX_GAIN_EN, wl_rx_low_gain_on[i]);
/* set Rx filter corner RCK offset */
rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1);
rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f);
rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1);
rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f);
} else {
for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++)
rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]);
/* set Rx filter corner RCK offset */
rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4);
rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0);
rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4);
rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0);
}
}
static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822b[] = {
{0x0086,
RTW_PWR_CUT_ALL_MSK,
@ -1549,8 +1795,160 @@ static struct rtw_chip_ops rtw8822b_ops = {
.cfg_ldo25 = rtw8822b_cfg_ldo25,
.false_alarm_statistics = rtw8822b_false_alarm_statistics,
.do_iqk = rtw8822b_do_iqk,
.coex_set_init = rtw8822b_coex_cfg_init,
.coex_set_ant_switch = rtw8822b_coex_cfg_ant_switch,
.coex_set_gnt_fix = rtw8822b_coex_cfg_gnt_fix,
.coex_set_gnt_debug = rtw8822b_coex_cfg_gnt_debug,
.coex_set_rfe_type = rtw8822b_coex_cfg_rfe_type,
.coex_set_wl_tx_power = rtw8822b_coex_cfg_wl_tx_power,
.coex_set_wl_rx_gain = rtw8822b_coex_cfg_wl_rx_gain,
};
/* Shared-Antenna Coex Table */
static const struct coex_table_para table_sant_8822b[] = {
{0xffffffff, 0xffffffff}, /* case-0 */
{0x55555555, 0x55555555},
{0x66555555, 0x66555555},
{0xaaaaaaaa, 0xaaaaaaaa},
{0x5a5a5a5a, 0x5a5a5a5a},
{0xfafafafa, 0xfafafafa}, /* case-5 */
{0x6a5a6a5a, 0xaaaaaaaa},
{0x6a5a56aa, 0x6a5a56aa},
{0x6a5a5a5a, 0x6a5a5a5a},
{0x66555555, 0x5a5a5a5a},
{0x66555555, 0x6a5a5a5a}, /* case-10 */
{0x66555555, 0xfafafafa},
{0x66555555, 0x6a5a5aaa},
{0x66555555, 0x5aaa5aaa},
{0x66555555, 0xaaaa5aaa},
{0x66555555, 0xaaaaaaaa}, /* case-15 */
{0xffff55ff, 0xfafafafa},
{0xffff55ff, 0x6afa5afa},
{0xaaffffaa, 0xfafafafa},
{0xaa5555aa, 0x5a5a5a5a},
{0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
{0xaa5555aa, 0xaaaaaaaa},
{0xffffffff, 0x5a5a5a5a},
{0xffffffff, 0x6a5a5a5a},
{0xffffffff, 0x55555555},
{0xffffffff, 0x6a5a5aaa}, /* case-25 */
{0x55555555, 0x5a5a5a5a},
{0x55555555, 0xaaaaaaaa},
{0x55555555, 0x6a5a6a5a},
{0x66556655, 0x66556655}
};
/* Non-Shared-Antenna Coex Table */
static const struct coex_table_para table_nsant_8822b[] = {
{0xffffffff, 0xffffffff}, /* case-100 */
{0x55555555, 0x55555555},
{0x66555555, 0x66555555},
{0xaaaaaaaa, 0xaaaaaaaa},
{0x5a5a5a5a, 0x5a5a5a5a},
{0xfafafafa, 0xfafafafa}, /* case-105 */
{0x5afa5afa, 0x5afa5afa},
{0x55555555, 0xfafafafa},
{0x66555555, 0xfafafafa},
{0x66555555, 0x5a5a5a5a},
{0x66555555, 0x6a5a5a5a}, /* case-110 */
{0x66555555, 0xaaaaaaaa},
{0xffff55ff, 0xfafafafa},
{0xffff55ff, 0x5afa5afa},
{0xffff55ff, 0xaaaaaaaa},
{0xaaffffaa, 0xfafafafa}, /* case-115 */
{0xaaffffaa, 0x5afa5afa},
{0xaaffffaa, 0xaaaaaaaa},
{0xffffffff, 0xfafafafa},
{0xffffffff, 0x5afa5afa},
{0xffffffff, 0xaaaaaaaa}, /* case-120 */
{0x55ff55ff, 0x5afa5afa},
{0x55ff55ff, 0xaaaaaaaa},
{0x55ff55ff, 0x55ff55ff}
};
/* Shared-Antenna TDMA */
static const struct coex_tdma_para tdma_sant_8822b[] = {
{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
{ {0x61, 0x45, 0x03, 0x11, 0x11} },
{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
{ {0x61, 0x30, 0x03, 0x11, 0x11} },
{ {0x61, 0x20, 0x03, 0x11, 0x11} },
{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
{ {0x61, 0x45, 0x03, 0x11, 0x10} },
{ {0x61, 0x3a, 0x03, 0x11, 0x10} },
{ {0x61, 0x30, 0x03, 0x11, 0x10} },
{ {0x61, 0x20, 0x03, 0x11, 0x10} },
{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
{ {0x61, 0x08, 0x03, 0x11, 0x14} },
{ {0x61, 0x08, 0x03, 0x10, 0x14} },
{ {0x51, 0x08, 0x03, 0x10, 0x54} },
{ {0x51, 0x08, 0x03, 0x10, 0x55} },
{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
{ {0x51, 0x45, 0x03, 0x10, 0x10} },
{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
{ {0x51, 0x30, 0x03, 0x10, 0x50} },
{ {0x51, 0x20, 0x03, 0x10, 0x50} },
{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
{ {0x51, 0x4a, 0x03, 0x10, 0x50} },
{ {0x51, 0x0c, 0x03, 0x10, 0x54} },
{ {0x55, 0x08, 0x03, 0x10, 0x54} },
{ {0x65, 0x10, 0x03, 0x11, 0x11} },
{ {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
{ {0x51, 0x08, 0x03, 0x10, 0x50} }
};
/* Non-Shared-Antenna TDMA */
static const struct coex_tdma_para tdma_nsant_8822b[] = {
{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
{ {0x61, 0x45, 0x03, 0x11, 0x11} },
{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
{ {0x61, 0x30, 0x03, 0x11, 0x11} },
{ {0x61, 0x20, 0x03, 0x11, 0x11} },
{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
{ {0x61, 0x45, 0x03, 0x11, 0x10} },
{ {0x61, 0x3a, 0x03, 0x11, 0x10} },
{ {0x61, 0x30, 0x03, 0x11, 0x10} },
{ {0x61, 0x20, 0x03, 0x11, 0x10} },
{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
{ {0x61, 0x08, 0x03, 0x11, 0x14} },
{ {0x61, 0x08, 0x03, 0x10, 0x14} },
{ {0x51, 0x08, 0x03, 0x10, 0x54} },
{ {0x51, 0x08, 0x03, 0x10, 0x55} },
{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
{ {0x51, 0x45, 0x03, 0x10, 0x50} },
{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
{ {0x51, 0x30, 0x03, 0x10, 0x50} },
{ {0x51, 0x20, 0x03, 0x10, 0x50} },
{ {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */
};
/* rssi in percentage % (dbm = % - 100) */
static const u8 wl_rssi_step_8822b[] = {60, 50, 44, 30};
static const u8 bt_rssi_step_8822b[] = {30, 30, 30, 30};
static const struct coex_5g_afh_map afh_5g_8822b[] = { {0, 0, 0} };
/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
static const struct coex_rf_para rf_para_tx_8822b[] = {
{0, 0, false, 7}, /* for normal */
{0, 16, false, 7}, /* for WL-CPT */
{4, 0, true, 1},
{3, 6, true, 1},
{2, 9, true, 1},
{1, 13, true, 1}
};
static const struct coex_rf_para rf_para_rx_8822b[] = {
{0, 0, false, 7}, /* for normal */
{0, 16, false, 7}, /* for WL-CPT */
{4, 0, true, 1},
{3, 6, true, 1},
{2, 9, true, 1},
{1, 13, true, 1}
};
static_assert(ARRAY_SIZE(rf_para_tx_8822b) == ARRAY_SIZE(rf_para_rx_8822b));
struct rtw_chip_info rtw8822b_hw_spec = {
.ops = &rtw8822b_ops,
.id = RTW_CHIP_TYPE_8822B,
@ -1588,6 +1986,32 @@ struct rtw_chip_info rtw8822b_hw_spec = {
.rf_tbl = {&rtw8822b_rf_a_tbl, &rtw8822b_rf_b_tbl},
.rfe_defs = rtw8822b_rfe_defs,
.rfe_defs_size = ARRAY_SIZE(rtw8822b_rfe_defs),
.coex_para_ver = 0x19062706,
.bt_desired_ver = 0x6,
.scbd_support = true,
.new_scbd10_def = false,
.pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
.bt_rssi_type = COEX_BTRSSI_RATIO,
.ant_isolation = 15,
.rssi_tolerance = 2,
.wl_rssi_step = wl_rssi_step_8822b,
.bt_rssi_step = bt_rssi_step_8822b,
.table_sant_num = ARRAY_SIZE(table_sant_8822b),
.table_sant = table_sant_8822b,
.table_nsant_num = ARRAY_SIZE(table_nsant_8822b),
.table_nsant = table_nsant_8822b,
.tdma_sant_num = ARRAY_SIZE(tdma_sant_8822b),
.tdma_sant = tdma_sant_8822b,
.tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822b),
.tdma_nsant = tdma_nsant_8822b,
.wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822b),
.wl_rf_para_tx = rf_para_tx_8822b,
.wl_rf_para_rx = rf_para_rx_8822b,
.bt_afh_span_bw20 = 0x24,
.bt_afh_span_bw40 = 0x36,
.afh_5g_num = ARRAY_SIZE(afh_5g_8822b),
.afh_5g = afh_5g_8822b,
};
EXPORT_SYMBOL(rtw8822b_hw_spec);

1564
drivers/net/wireless/realtek/rtw88/rtw8822b_table.c
View File

File diff suppressed because it is too large Load Diff

355
drivers/net/wireless/realtek/rtw88/rtw8822c.c
View File

@ -3,6 +3,7 @@
*/
#include "main.h"
#include "coex.h"
#include "fw.h"
#include "tx.h"
#include "rx.h"
@ -31,6 +32,7 @@ static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
map = (struct rtw8822c_efuse *)log_map;
efuse->rfe_option = map->rfe_option;
efuse->rf_board_option = map->rf_board_option;
efuse->crystal_cap = map->xtal_k;
efuse->channel_plan = map->channel_plan;
efuse->country_code[0] = map->country_code[0];
@ -1041,12 +1043,6 @@ static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev)
dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb));
rtw8822c_rf_init(rtwdev);
/* wifi path controller */
rtw_write32_mask(rtwdev, 0x70, 0xff000000, 0x0e);
rtw_write32_mask(rtwdev, 0x1704, 0xffffffff, 0x7700);
rtw_write32_mask(rtwdev, 0x1700, 0xffffffff, 0xc00f0038);
rtw_write32_mask(rtwdev, 0x6c0, 0xffffffff, 0xaaaaaaaa);
rtw_write32_mask(rtwdev, 0x6c4, 0xffffffff, 0xaaaaaaaa);
}
#define WLAN_TXQ_RPT_EN 0x1F
@ -1817,6 +1813,7 @@ static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev)
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u32 cck_enable;
u32 cck_fa_cnt;
u32 crc32_cnt;
u32 ofdm_fa_cnt;
u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5;
u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail,
@ -1848,6 +1845,19 @@ static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev)
dm_info->total_fa_cnt = ofdm_fa_cnt;
dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
crc32_cnt = rtw_read32(rtwdev, 0x2c04);
dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
crc32_cnt = rtw_read32(rtwdev, 0x2c14);
dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
crc32_cnt = rtw_read32(rtwdev, 0x2c10);
dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
crc32_cnt = rtw_read32(rtwdev, 0x2c0c);
dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0);
rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2);
rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0);
@ -1864,6 +1874,161 @@ static void rtw8822c_do_iqk(struct rtw_dev *rtwdev)
{
}
/* for coex */
static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev)
{
/* enable TBTT nterrupt */
rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
/* BT report packet sample rate */
/* 0x790[5:0]=0x5 */
rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05);
/* enable BT counter statistics */
rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
/* enable PTA (3-wire function form BT side) */
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3);
/* enable PTA (tx/rx signal form WiFi side) */
rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
/* wl tx signal to PTA not case EDCCA */
rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
/* GNT_BT=1 while select both */
rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
/* BT_CCA = ~GNT_WL_BB, (not or GNT_BT_BB, LTE_Rx */
rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL);
/* to avoid RF parameter error */
rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, 0x40000);
}
static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
struct rtw_efuse *efuse = &rtwdev->efuse;
u32 rf_0x1;
if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode)
return;
coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode;
if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun)
rf_0x1 = 0x40021;
else
rf_0x1 = 0x40000;
/* BT at S1 for Shared-Ant */
if (efuse->share_ant)
rf_0x1 |= BIT(13);
rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1);
/* WL-S0 2G RF TRX cannot be masked by GNT_BT
* enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type
* disable:0x1860[3] = 1, enable:0x1860[3] = 0
*
* enable "DAC off if GNT_WL = 0" for non-shared-antenna
* disable 0x1c30[22] = 0,
* enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1
*
* disable WL-S1 BB chage RF mode if GNT_BT
* since RF TRx mask can do it
*/
rtw_write8_mask(rtwdev, 0x1c32, BIT(6), 1);
rtw_write8_mask(rtwdev, 0x1c39, BIT(4), 0);
rtw_write8_mask(rtwdev, 0x1c3b, BIT(4), 1);
rtw_write8_mask(rtwdev, 0x4160, BIT(3), 1);
/* disable WL-S0 BB chage RF mode if wifi is at 5G,
* or antenna path is separated
*/
if (coex_stat->wl_coex_mode == COEX_WLINK_5G ||
coex->under_5g || !efuse->share_ant) {
if (coex_stat->kt_ver >= 3) {
rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 1);
} else {
rtw_write8_mask(rtwdev, 0x1860, BIT(3), 1);
}
} else {
/* shared-antenna */
rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
if (coex_stat->kt_ver >= 3)
rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 0);
}
}
static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
{
rtw_write8_mask(rtwdev, 0x66, BIT(4), 0);
rtw_write8_mask(rtwdev, 0x67, BIT(0), 0);
rtw_write8_mask(rtwdev, 0x42, BIT(3), 0);
rtw_write8_mask(rtwdev, 0x65, BIT(7), 0);
rtw_write8_mask(rtwdev, 0x73, BIT(3), 0);
}
static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_rfe *coex_rfe = &coex->rfe;
struct rtw_efuse *efuse = &rtwdev->efuse;
coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
coex_rfe->ant_switch_polarity = 0;
coex_rfe->ant_switch_exist = false;
coex_rfe->ant_switch_with_bt = false;
coex_rfe->ant_switch_diversity = false;
if (efuse->share_ant)
coex_rfe->wlg_at_btg = true;
else
coex_rfe->wlg_at_btg = false;
/* disable LTE coex in wifi side */
rtw_coex_write_indirect_reg(rtwdev, 0x38, BIT_LTE_COEX_EN, 0x0);
rtw_coex_write_indirect_reg(rtwdev, 0xa0, MASKLWORD, 0xffff);
rtw_coex_write_indirect_reg(rtwdev, 0xa4, MASKLWORD, 0xffff);
}
static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_dm *coex_dm = &coex->dm;
if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
return;
coex_dm->cur_wl_pwr_lvl = wl_pwr;
}
static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_dm *coex_dm = &coex->dm;
if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
return;
coex_dm->cur_wl_rx_low_gain_en = low_gain;
if (coex_dm->cur_wl_rx_low_gain_en) {
/* set Rx filter corner RCK offset */
rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x22);
rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x36);
rtw_write_rf(rtwdev, RF_PATH_B, 0xde, 0xfffff, 0x22);
rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x36);
} else {
/* set Rx filter corner RCK offset */
rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x20);
rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x0);
rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x0);
}
}
static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = {
{0x0086,
RTW_PWR_CUT_ALL_MSK,
@ -2232,8 +2397,160 @@ static struct rtw_chip_ops rtw8822c_ops = {
.cfg_ldo25 = rtw8822c_cfg_ldo25,
.false_alarm_statistics = rtw8822c_false_alarm_statistics,
.do_iqk = rtw8822c_do_iqk,
.coex_set_init = rtw8822c_coex_cfg_init,
.coex_set_ant_switch = NULL,
.coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix,
.coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug,
.coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type,
.coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power,
.coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain,
};
/* Shared-Antenna Coex Table */
static const struct coex_table_para table_sant_8822c[] = {
{0xffffffff, 0xffffffff}, /* case-0 */
{0x55555555, 0x55555555},
{0x66555555, 0x66555555},
{0xaaaaaaaa, 0xaaaaaaaa},
{0x5a5a5a5a, 0x5a5a5a5a},
{0xfafafafa, 0xfafafafa}, /* case-5 */
{0x6a5a6a5a, 0xaaaaaaaa},
{0x6a5a56aa, 0x6a5a56aa},
{0x6a5a5a5a, 0x6a5a5a5a},
{0x66555555, 0x5a5a5a5a},
{0x66555555, 0x6a5a5a5a}, /* case-10 */
{0x66555555, 0xfafafafa},
{0x66555555, 0x6a5a5aaa},
{0x66555555, 0x5aaa5aaa},
{0x66555555, 0xaaaa5aaa},
{0x66555555, 0xaaaaaaaa}, /* case-15 */
{0xffff55ff, 0xfafafafa},
{0xffff55ff, 0x6afa5afa},
{0xaaffffaa, 0xfafafafa},
{0xaa5555aa, 0x5a5a5a5a},
{0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
{0xaa5555aa, 0xaaaaaaaa},
{0xffffffff, 0x5a5a5a5a},
{0xffffffff, 0x6a5a5a5a},
{0xffffffff, 0x55555555},
{0xffffffff, 0x6a5a5aaa}, /* case-25 */
{0x55555555, 0x5a5a5a5a},
{0x55555555, 0xaaaaaaaa},
{0x55555555, 0x6a5a6a5a},
{0x66556655, 0x66556655}
};
/* Non-Shared-Antenna Coex Table */
static const struct coex_table_para table_nsant_8822c[] = {
{0xffffffff, 0xffffffff}, /* case-100 */
{0x55555555, 0x55555555},
{0x66555555, 0x66555555},
{0xaaaaaaaa, 0xaaaaaaaa},
{0x5a5a5a5a, 0x5a5a5a5a},
{0xfafafafa, 0xfafafafa}, /* case-105 */
{0x5afa5afa, 0x5afa5afa},
{0x55555555, 0xfafafafa},
{0x66555555, 0xfafafafa},
{0x66555555, 0x5a5a5a5a},
{0x66555555, 0x6a5a5a5a}, /* case-110 */
{0x66555555, 0xaaaaaaaa},
{0xffff55ff, 0xfafafafa},
{0xffff55ff, 0x5afa5afa},
{0xffff55ff, 0xaaaaaaaa},
{0xaaffffaa, 0xfafafafa}, /* case-115 */
{0xaaffffaa, 0x5afa5afa},
{0xaaffffaa, 0xaaaaaaaa},
{0xffffffff, 0xfafafafa},
{0xffffffff, 0x5afa5afa},
{0xffffffff, 0xaaaaaaaa},/* case-120 */
{0x55ff55ff, 0x5afa5afa},
{0x55ff55ff, 0xaaaaaaaa},
{0x55ff55ff, 0x55ff55ff}
};
/* Shared-Antenna TDMA */
static const struct coex_tdma_para tdma_sant_8822c[] = {
{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
{ {0x61, 0x45, 0x03, 0x11, 0x11} },
{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
{ {0x61, 0x30, 0x03, 0x11, 0x11} },
{ {0x61, 0x20, 0x03, 0x11, 0x11} },
{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
{ {0x61, 0x45, 0x03, 0x11, 0x10} },
{ {0x61, 0x3a, 0x03, 0x11, 0x10} },
{ {0x61, 0x30, 0x03, 0x11, 0x10} },
{ {0x61, 0x20, 0x03, 0x11, 0x10} },
{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
{ {0x61, 0x08, 0x03, 0x11, 0x14} },
{ {0x61, 0x08, 0x03, 0x10, 0x14} },
{ {0x51, 0x08, 0x03, 0x10, 0x54} },
{ {0x51, 0x08, 0x03, 0x10, 0x55} },
{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
{ {0x51, 0x45, 0x03, 0x10, 0x10} },
{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
{ {0x51, 0x30, 0x03, 0x10, 0x50} },
{ {0x51, 0x20, 0x03, 0x10, 0x50} },
{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
{ {0x51, 0x4a, 0x03, 0x10, 0x50} },
{ {0x51, 0x0c, 0x03, 0x10, 0x54} },
{ {0x55, 0x08, 0x03, 0x10, 0x54} },
{ {0x65, 0x10, 0x03, 0x11, 0x11} },
{ {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
{ {0x51, 0x08, 0x03, 0x10, 0x50} }
};
/* Non-Shared-Antenna TDMA */
static const struct coex_tdma_para tdma_nsant_8822c[] = {
{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
{ {0x61, 0x45, 0x03, 0x11, 0x11} },
{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
{ {0x61, 0x30, 0x03, 0x11, 0x11} },
{ {0x61, 0x20, 0x03, 0x11, 0x11} },
{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
{ {0x61, 0x45, 0x03, 0x11, 0x10} },
{ {0x61, 0x3a, 0x03, 0x11, 0x10} },
{ {0x61, 0x30, 0x03, 0x11, 0x10} },
{ {0x61, 0x20, 0x03, 0x11, 0x10} },
{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
{ {0x61, 0x08, 0x03, 0x11, 0x14} },
{ {0x61, 0x08, 0x03, 0x10, 0x14} },
{ {0x51, 0x08, 0x03, 0x10, 0x54} },
{ {0x51, 0x08, 0x03, 0x10, 0x55} },
{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
{ {0x51, 0x45, 0x03, 0x10, 0x50} },
{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
{ {0x51, 0x30, 0x03, 0x10, 0x50} },
{ {0x51, 0x20, 0x03, 0x10, 0x50} },
{ {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */
};
/* rssi in percentage % (dbm = % - 100) */
static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30};
static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25};
static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} };
/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
static const struct coex_rf_para rf_para_tx_8822c[] = {
{0, 0, false, 7}, /* for normal */
{0, 16, false, 7}, /* for WL-CPT */
{8, 17, true, 4},
{7, 18, true, 4},
{6, 19, true, 4},
{5, 20, true, 4}
};
static const struct coex_rf_para rf_para_rx_8822c[] = {
{0, 0, false, 7}, /* for normal */
{0, 16, false, 7}, /* for WL-CPT */
{3, 24, true, 5},
{2, 26, true, 5},
{1, 27, true, 5},
{0, 28, true, 5}
};
static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c));
struct rtw_chip_info rtw8822c_hw_spec = {
.ops = &rtw8822c_ops,
.id = RTW_CHIP_TYPE_8822C,
@ -2272,6 +2589,32 @@ struct rtw_chip_info rtw8822c_hw_spec = {
.rf_tbl = {&rtw8822c_rf_a_tbl, &rtw8822c_rf_b_tbl},
.rfe_defs = rtw8822c_rfe_defs,
.rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs),
.coex_para_ver = 0x19062706,
.bt_desired_ver = 0x6,
.scbd_support = true,
.new_scbd10_def = true,
.pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
.bt_rssi_type = COEX_BTRSSI_DBM,
.ant_isolation = 15,
.rssi_tolerance = 2,
.wl_rssi_step = wl_rssi_step_8822c,
.bt_rssi_step = bt_rssi_step_8822c,
.table_sant_num = ARRAY_SIZE(table_sant_8822c),
.table_sant = table_sant_8822c,
.table_nsant_num = ARRAY_SIZE(table_nsant_8822c),
.table_nsant = table_nsant_8822c,
.tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c),
.tdma_sant = tdma_sant_8822c,
.tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c),
.tdma_nsant = tdma_nsant_8822c,
.wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c),
.wl_rf_para_tx = rf_para_tx_8822c,
.wl_rf_para_rx = rf_para_rx_8822c,
.bt_afh_span_bw20 = 0x24,
.bt_afh_span_bw40 = 0x36,
.afh_5g_num = ARRAY_SIZE(afh_5g_8822c),
.afh_5g = afh_5g_8822c,
};
EXPORT_SYMBOL(rtw8822c_hw_spec);

2635
drivers/net/wireless/realtek/rtw88/rtw8822c_table.c
View File

File diff suppressed because it is too large Load Diff

31
drivers/net/wireless/rsi/rsi_91x_sdio.c
View File

@ -230,19 +230,16 @@ static void rsi_reset_card(struct sdio_func *pfunction)
rsi_dbg(ERR_ZONE, "%s: CMD0 failed : %d\n", __func__, err);
/* Issue CMD5, arg = 0 */
if (!host->ocr_avail) {
err = rsi_issue_sdiocommand(pfunction, SD_IO_SEND_OP_COND, 0,
(MMC_RSP_R4 | MMC_CMD_BCR), &resp);
if (err)
rsi_dbg(ERR_ZONE, "%s: CMD5 failed : %d\n",
__func__, err);
host->ocr_avail = resp;
}
err = rsi_issue_sdiocommand(pfunction, SD_IO_SEND_OP_COND, 0,
(MMC_RSP_R4 | MMC_CMD_BCR), &resp);
if (err)
rsi_dbg(ERR_ZONE, "%s: CMD5 failed : %d\n",
__func__, err);
card->ocr = resp;
/* Issue CMD5, arg = ocr. Wait till card is ready */
for (i = 0; i < 100; i++) {
err = rsi_issue_sdiocommand(pfunction, SD_IO_SEND_OP_COND,
host->ocr_avail,
card->ocr,
(MMC_RSP_R4 | MMC_CMD_BCR), &resp);
if (err) {
rsi_dbg(ERR_ZONE, "%s: CMD5 failed : %d\n",
@ -844,11 +841,11 @@ static int rsi_init_sdio_interface(struct rsi_hw *adapter,
struct sdio_func *pfunction)
{
struct rsi_91x_sdiodev *rsi_91x_dev;
int status = -ENOMEM;
int status;
rsi_91x_dev = kzalloc(sizeof(*rsi_91x_dev), GFP_KERNEL);
if (!rsi_91x_dev)
return status;
return -ENOMEM;
adapter->rsi_dev = rsi_91x_dev;
@ -890,7 +887,7 @@ static int rsi_init_sdio_interface(struct rsi_hw *adapter,
#ifdef CONFIG_RSI_DEBUGFS
adapter->num_debugfs_entries = MAX_DEBUGFS_ENTRIES;
#endif
return status;
return 0;
fail:
sdio_disable_func(pfunction);
sdio_release_host(pfunction);
@ -944,7 +941,7 @@ static int rsi_sdio_ta_reset(struct rsi_hw *adapter)
put_unaligned_le32(TA_HOLD_THREAD_VALUE, data);
addr = TA_HOLD_THREAD_REG | RSI_SD_REQUEST_MASTER;
status = rsi_sdio_write_register_multiple(adapter, addr,
(u8 *)&data,
(u8 *)data,
RSI_9116_REG_SIZE);
if (status < 0) {
rsi_dbg(ERR_ZONE, "Unable to hold TA threads\n");
@ -954,7 +951,7 @@ static int rsi_sdio_ta_reset(struct rsi_hw *adapter)
put_unaligned_le32(TA_SOFT_RST_CLR, data);
addr = TA_SOFT_RESET_REG | RSI_SD_REQUEST_MASTER;
status = rsi_sdio_write_register_multiple(adapter, addr,
(u8 *)&data,
(u8 *)data,
RSI_9116_REG_SIZE);
if (status < 0) {
rsi_dbg(ERR_ZONE, "Unable to get TA out of reset\n");
@ -964,7 +961,7 @@ static int rsi_sdio_ta_reset(struct rsi_hw *adapter)
put_unaligned_le32(TA_PC_ZERO, data);
addr = TA_TH0_PC_REG | RSI_SD_REQUEST_MASTER;
status = rsi_sdio_write_register_multiple(adapter, addr,
(u8 *)&data,
(u8 *)data,
RSI_9116_REG_SIZE);
if (status < 0) {
rsi_dbg(ERR_ZONE, "Unable to Reset TA PC value\n");
@ -975,7 +972,7 @@ static int rsi_sdio_ta_reset(struct rsi_hw *adapter)
put_unaligned_le32(TA_RELEASE_THREAD_VALUE, data);
addr = TA_RELEASE_THREAD_REG | RSI_SD_REQUEST_MASTER;
status = rsi_sdio_write_register_multiple(adapter, addr,
(u8 *)&data,
(u8 *)data,
RSI_9116_REG_SIZE);
if (status < 0) {
rsi_dbg(ERR_ZONE, "Unable to release TA threads\n");

4
drivers/net/wireless/wl3501_cs.c
View File

@ -1226,7 +1226,6 @@ static int wl3501_init_firmware(struct wl3501_card *this)
static int wl3501_close(struct net_device *dev)
{
struct wl3501_card *this = netdev_priv(dev);
int rc = -ENODEV;
unsigned long flags;
struct pcmcia_device *link;
link = this->p_dev;
@ -1241,10 +1240,9 @@ static int wl3501_close(struct net_device *dev)
/* Mask interrupts from the SUTRO */
wl3501_block_interrupt(this);
rc = 0;
printk(KERN_INFO "%s: WL3501 closed\n", dev->name);
spin_unlock_irqrestore(&this->lock, flags);
return rc;
return 0;
}
/**