mirror of https://gitee.com/openkylin/linux.git
iommu/vt-d: Use dev_printk() when possible
Use dev_printk() when possible so the IOMMU messages are more consistent with other messages related to the device. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Bjorn Helgaas
Joerg Roedel
parent
1a9eb9b98f
commit
932a6523ce
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@ -19,6 +19,7 @@
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*/
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#define pr_fmt(fmt) "DMAR: " fmt
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#define dev_fmt(fmt) pr_fmt(fmt)
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#include <linux/init.h>
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#include <linux/bitmap.h>
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@ -1815,7 +1816,7 @@ static int dmar_init_reserved_ranges(void)
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IOVA_PFN(r->start),
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IOVA_PFN(r->end));
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if (!iova) {
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pr_err("Reserve iova failed\n");
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pci_err(pdev, "Reserve iova for %pR failed\n", r);
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return -ENODEV;
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}
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}
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@ -2544,8 +2545,7 @@ static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu,
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if (dev && dev_is_pci(dev) && sm_supported(iommu)) {
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ret = intel_pasid_alloc_table(dev);
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if (ret) {
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pr_err("PASID table allocation for %s failed\n",
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dev_name(dev));
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dev_err(dev, "PASID table allocation failed\n");
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dmar_remove_one_dev_info(domain, dev);
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return NULL;
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}
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@ -2560,15 +2560,14 @@ static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu,
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dev, PASID_RID2PASID);
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spin_unlock(&iommu->lock);
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if (ret) {
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pr_err("Setup RID2PASID for %s failed\n",
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dev_name(dev));
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dev_err(dev, "Setup RID2PASID failed\n");
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dmar_remove_one_dev_info(domain, dev);
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return NULL;
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}
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}
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if (dev && domain_context_mapping(domain, dev)) {
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pr_err("Domain context map for %s failed\n", dev_name(dev));
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dev_err(dev, "Domain context map failed\n");
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dmar_remove_one_dev_info(domain, dev);
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return NULL;
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}
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@ -2723,13 +2722,12 @@ static int domain_prepare_identity_map(struct device *dev,
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range which is reserved in E820, so which didn't get set
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up to start with in si_domain */
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if (domain == si_domain && hw_pass_through) {
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pr_warn("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
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dev_name(dev), start, end);
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dev_warn(dev, "Ignoring identity map for HW passthrough [0x%Lx - 0x%Lx]\n",
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start, end);
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return 0;
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}
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pr_info("Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
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dev_name(dev), start, end);
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dev_info(dev, "Setting identity map [0x%Lx - 0x%Lx]\n", start, end);
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if (end < start) {
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WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
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@ -3016,8 +3014,8 @@ static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw
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ret = domain_add_dev_info(si_domain, dev);
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if (!ret)
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pr_info("%s identity mapping for device %s\n",
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hw ? "Hardware" : "Software", dev_name(dev));
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dev_info(dev, "%s identity mapping\n",
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hw ? "Hardware" : "Software");
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else if (ret == -ENODEV)
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/* device not associated with an iommu */
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ret = 0;
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@ -3550,8 +3548,7 @@ static unsigned long intel_alloc_iova(struct device *dev,
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iova_pfn = alloc_iova_fast(&domain->iovad, nrpages,
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IOVA_PFN(dma_mask), true);
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if (unlikely(!iova_pfn)) {
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pr_err("Allocating %ld-page iova for %s failed",
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nrpages, dev_name(dev));
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dev_err(dev, "Allocating %ld-page iova failed", nrpages);
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return 0;
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}
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@ -3599,7 +3596,7 @@ struct dmar_domain *get_valid_domain_for_dev(struct device *dev)
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out:
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if (!domain)
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pr_err("Allocating domain for %s failed\n", dev_name(dev));
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dev_err(dev, "Allocating domain failed\n");
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return domain;
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@ -3626,8 +3623,7 @@ static int iommu_no_mapping(struct device *dev)
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* to non-identity mapping.
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*/
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dmar_remove_one_dev_info(si_domain, dev);
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pr_info("32bit %s uses non-identity mapping\n",
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dev_name(dev));
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dev_info(dev, "32bit DMA uses non-identity mapping\n");
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return 0;
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}
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} else {
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@ -3639,8 +3635,7 @@ static int iommu_no_mapping(struct device *dev)
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int ret;
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ret = domain_add_dev_info(si_domain, dev);
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if (!ret) {
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pr_info("64bit %s uses identity mapping\n",
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dev_name(dev));
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dev_info(dev, "64bit DMA uses identity mapping\n");
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return 1;
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}
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}
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@ -3703,8 +3698,8 @@ static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr,
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error:
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if (iova_pfn)
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free_iova_fast(&domain->iovad, iova_pfn, dma_to_mm_pfn(size));
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pr_err("Device %s request: %zx@%llx dir %d --- failed\n",
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dev_name(dev), size, (unsigned long long)paddr, dir);
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dev_err(dev, "Device request: %zx@%llx dir %d --- failed\n",
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size, (unsigned long long)paddr, dir);
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return DMA_MAPPING_ERROR;
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}
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@ -3747,8 +3742,7 @@ static void intel_unmap(struct device *dev, dma_addr_t dev_addr, size_t size)
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start_pfn = mm_to_dma_pfn(iova_pfn);
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last_pfn = start_pfn + nrpages - 1;
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pr_debug("Device %s unmapping: pfn %lx-%lx\n",
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dev_name(dev), start_pfn, last_pfn);
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dev_dbg(dev, "Device unmapping: pfn %lx-%lx\n", start_pfn, last_pfn);
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freelist = domain_unmap(domain, start_pfn, last_pfn);
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@ -5105,9 +5099,9 @@ static int intel_iommu_attach_device(struct iommu_domain *domain,
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addr_width = cap_mgaw(iommu->cap);
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if (dmar_domain->max_addr > (1LL << addr_width)) {
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pr_err("%s: iommu width (%d) is not "
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"sufficient for the mapped address (%llx)\n",
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__func__, addr_width, dmar_domain->max_addr);
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dev_err(dev, "%s: iommu width (%d) is not "
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"sufficient for the mapped address (%llx)\n",
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__func__, addr_width, dmar_domain->max_addr);
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return -EFAULT;
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}
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dmar_domain->gaw = addr_width;
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@ -5408,7 +5402,7 @@ const struct iommu_ops intel_iommu_ops = {
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static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
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{
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/* G4x/GM45 integrated gfx dmar support is totally busted. */
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pr_info("Disabling IOMMU for graphics on this chipset\n");
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pci_info(dev, "Disabling IOMMU for graphics on this chipset\n");
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dmar_map_gfx = 0;
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}
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@ -5426,7 +5420,7 @@ static void quirk_iommu_rwbf(struct pci_dev *dev)
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* Mobile 4 Series Chipset neglects to set RWBF capability,
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* but needs it. Same seems to hold for the desktop versions.
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*/
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pr_info("Forcing write-buffer flush capability\n");
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pci_info(dev, "Forcing write-buffer flush capability\n");
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rwbf_quirk = 1;
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}
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@ -5456,11 +5450,11 @@ static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
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return;
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if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
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pr_info("BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
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pci_info(dev, "BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
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dmar_map_gfx = 0;
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} else if (dmar_map_gfx) {
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/* we have to ensure the gfx device is idle before we flush */
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pr_info("Disabling batched IOTLB flush on Ironlake\n");
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pci_info(dev, "Disabling batched IOTLB flush on Ironlake\n");
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intel_iommu_strict = 1;
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}
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}
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