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ARM: SoC device tree updates for 4.20 

There are close to 800 indivudal changesets in this branch again, which
 feels like a lot. There are particularly many changes for the NVIDIA
 Tegra platform this time, in fact more than it has seen in the two years
 since the v4.9 merge window. Aside from this, it's been fairly normal,
 with lots of changes going into Renesas R-CAR, NXP i.MX, Allwinner Sunxi,
 Samsung Exynos, and TI OMAP.
 
 Most of the changes are for adding new features into existing boards,
 for brevity I'm only mentioning completely new machines and SoCs here.
 For the first time I think we have (slightly) more new 64-bit hardware
 than 32-bit:
 
 Two boards get added for TI OMAP: Moxa UC-2101 is an industrial
 computer, see https://www.moxa.com/product/UC-2100.htm; GTA04A5
 is a minor variation of the motherboards of the GTA04 phone, see
 https://shop.goldelico.com/wiki.php?page=GTA04A5
 
 Clearfog is a nice little board for quad-core
 Marvell Armada 8040 network processor, see
 https://www.solid-run.com/marvell-armada-family/clearfog-gt-8k/
 
 Two additional server boards come with the Aspeed baseboard management
 controllers: Stardragon4800 is an arm64 reference platform made by HXT
 (based on Qualcomm's server chips), and TiogaPass is an Open Compute
 mainboard with x86 CPUs. Both use the ARM11 based AST2500 chips in
 the BMC.
 
 NXP i.MX usually sees a lot of new boards each release. This time there
 we only add one minor variant: ConnectCore 6UL SBC Pro uses the same
 SoM design as the ConnectCore 6UL SBC Express added later. However,
 there is a new chip, the i.MX6ULZ, which is an even smaller variant
 of the i.MX6ULL, with features removed. There is also support for the
 reference board design, the i.MX6ULZ 14x14 EVK.
 
 A new Raspberry Pi variant gets added, this one is the CM3 compute module
 based on bcm2837, it was launched in early 2017 but only now added to
 the kernel, both as 32-bit and as 64-bit files, as we tend to do for
 Raspberry Pi.
 
 On the Allwinner side, everything is again about cheap development
 boards, usually of the "Fruit Pi" variety. The new ones this time
 are:
 Orange Pi Zero Plus2: http://www.orangepi.org/OrangePiZeroPlus2/
 Orange Pi One Plus: http://www.orangepi.org/OrangePiOneplus/
 Pine64 LTS: https://www.pine64.org/?product=pine-a64-lts
 Banana Pi M2+ H5: http://www.banana-pi.org/m2plus.html
 The last one of these is now a 64-bit version of the earlier Banana
 Pi M2+ H3, with the same board layout.
 
 Similarly, for Rockchips, get get another variant of the 32-bit
 Asus Tinker board, the model 'S' based on rk3288, and three now
 boards based on the popular RK3399 chip:
 ROC-RK3399-PC: https://libre.computer/products/boards/roc-rk3399-pc/
 Rock960: https://www.96boards.org/product/rock960/
 RockPro64: https://www.pine64.org/?page_id=61454
 These are all quite powerful boards with lots of RAM and I/O, and
 the RK3399 is the same chip used in several Chromebooks.  Finally,
 we get support for the PX30 (aka rk3326) chip, which is based on the
 low-end 64-bit Cortex-A35 CPU core. So far, only the evaluation board
 is supported.
 
 One more Banana Pi is added with a Mediatek chip: Banana Pi R64 is based
 on the MT7622 WiFi router platform, and the first product I've seen with
 a 64-bit Mediatek chip in that market: http://www.banana-pi.org/r64.html
 
 For HiSilicon, we gain support for the Hi3670 SoC and HiKey 370
 development board, which are similar to the Hi3660 and Hikey 360
 respectively, but add support for an NPU.
 
 Amlogic gets initial support for the Meson-G12A chip (S905D2),
 another quad-core Cortex-A53 SoC, and its evaluation platform.
 On the 32-bit side, we gain support for an actual end-user product,
 the Endless Computers Endless Mini based on Meson8b (S805), see
 https://endlessos.com/computers/
 
 Qualcomm adds support for their MSM8998 SoC and evaluation platform. This
 chip is commonly known as the Snapdragon 835, and is used in high-end
 phones as well as low-end laptops.
 
 For Renesas, a very bare support for the r8a774a1 (RZ/G2M) is added,
 but no boards for this one. However, we do add boards for the previously
 added r8a77965 (R-Car M3-N): the M3NULCB Kingfisher and the M3NULCB
 Starter Kit Pro.
 
 While we have lots of DT changes for NVIDIA to update the existing files,
 the only board that gets added is the Toradex Colibri T20 on Colibri
 Evaluation Board for the old Tegra2.
 
 Synaptics add support for their AS370 SoC, which is part of the (formerly
 Marvell) Berlin line of set-top-box chips used e.g.  in the various Google
 Chromecast. Only the .dtsi gets added at this point, no actual machines.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device tree updates from Arnd Bergmann:
 "There are close to 800 indivudal changesets in this branch again,
  which feels like a lot. There are particularly many changes for the
  NVIDIA Tegra platform this time, in fact more than it has seen in the
  two years since the v4.9 merge window. Aside from this, it's been
  fairly normal, with lots of changes going into Renesas R-CAR, NXP
  i.MX, Allwinner Sunxi, Samsung Exynos, and TI OMAP.

  Most of the changes are for adding new features into existing boards,
  for brevity I'm only mentioning completely new machines and SoCs here.
  For the first time I think we have (slightly) more new 64-bit hardware
  than 32-bit:

  Two boards get added for TI OMAP: Moxa UC-2101 is an industrial
  computer, see https://www.moxa.com/product/UC-2100.htm; GTA04A5 is a
  minor variation of the motherboards of the GTA04 phone, see
  https://shop.goldelico.com/wiki.php?page=GTA04A5

  Clearfog is a nice little board for quad-core Marvell Armada 8040
  network processor, see
  https://www.solid-run.com/marvell-armada-family/clearfog-gt-8k/

  Two additional server boards come with the Aspeed baseboard management
  controllers: Stardragon4800 is an arm64 reference platform made by HXT
  (based on Qualcomm's server chips), and TiogaPass is an Open Compute
  mainboard with x86 CPUs. Both use the ARM11 based AST2500 chips in the
  BMC.

  NXP i.MX usually sees a lot of new boards each release. This time
  there we only add one minor variant: ConnectCore 6UL SBC Pro uses the
  same SoM design as the ConnectCore 6UL SBC Express added later.
  However, there is a new chip, the i.MX6ULZ, which is an even smaller
  variant of the i.MX6ULL, with features removed. There is also support
  for the reference board design, the i.MX6ULZ 14x14 EVK.

  A new Raspberry Pi variant gets added, this one is the CM3 compute
  module based on bcm2837, it was launched in early 2017 but only now
  added to the kernel, both as 32-bit and as 64-bit files, as we tend to
  do for Raspberry Pi.

  On the Allwinner side, everything is again about cheap development
  boards, usually of the "Fruit Pi" variety. The new ones this time are:
   - Orange Pi Zero Plus2: http://www.orangepi.org/OrangePiZeroPlus2/
   - Orange Pi One Plus: http://www.orangepi.org/OrangePiOneplus/
   - Pine64 LTS: https://www.pine64.org/?product=pine-a64-lts
   - Banana Pi M2+ H5: http://www.banana-pi.org/m2plus.html
  The last one of these is now a 64-bit version of the earlier Banana Pi
  M2+ H3, with the same board layout.

  Similarly, for Rockchips, get get another variant of the 32-bit Asus
  Tinker board, the model 'S' based on rk3288, and three now boards
  based on the popular RK3399 chip:
   - ROC-RK3399-PC: https://libre.computer/products/boards/roc-rk3399-pc/
   - Rock960: https://www.96boards.org/product/rock960/
   - RockPro64: https://www.pine64.org/?page_id=61454
  These are all quite powerful boards with lots of RAM and I/O, and the
  RK3399 is the same chip used in several Chromebooks. Finally, we get
  support for the PX30 (aka rk3326) chip, which is based on the low-end
  64-bit Cortex-A35 CPU core. So far, only the evaluation board is
  supported.

  One more Banana Pi is added with a Mediatek chip: Banana Pi R64 is
  based on the MT7622 WiFi router platform, and the first product I've
  seen with a 64-bit Mediatek chip in that market:
  http://www.banana-pi.org/r64.html

  For HiSilicon, we gain support for the Hi3670 SoC and HiKey 370
  development board, which are similar to the Hi3660 and Hikey 360
  respectively, but add support for an NPU.

  Amlogic gets initial support for the Meson-G12A chip (S905D2), another
  quad-core Cortex-A53 SoC, and its evaluation platform. On the 32-bit
  side, we gain support for an actual end-user product, the Endless
  Computers Endless Mini based on Meson8b (S805), see
  https://endlessos.com/computers/

  Qualcomm adds support for their MSM8998 SoC and evaluation platform.
  This chip is commonly known as the Snapdragon 835, and is used in
  high-end phones as well as low-end laptops.

  For Renesas, a very bare support for the r8a774a1 (RZ/G2M) is added,
  but no boards for this one. However, we do add boards for the
  previously added r8a77965 (R-Car M3-N): the M3NULCB Kingfisher and the
  M3NULCB Starter Kit Pro.

  While we have lots of DT changes for NVIDIA to update the existing
  files, the only board that gets added is the Toradex Colibri T20 on
  Colibri Evaluation Board for the old Tegra2.

  Synaptics add support for their AS370 SoC, which is part of the
  (formerly Marvell) Berlin line of set-top-box chips used e.g. in the
  various Google Chromecast. Only the .dtsi gets added at this point, no
  actual machines"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (721 commits)
  ARM: dts: socfgpa: remove ethernet aliases from dtsi
  arm64: dts: stratix10: add ethernet aliases
  dt-bindings: mediatek: Add bindig for MT7623 IOMMU and SMI
  dt-bindings: mediatek: Add JPEG Decoder binding for MT7623
  dt-bindings: iommu: mediatek: Add binding for MT7623
  dt-bindings: clock: mediatek: add support for MT7623
  ARM: dts: mvebu: armada-385-db-88f6820-amc: auto-detect nand ECC properites
  ARM: dts: da850-lego-ev3: slow down A/DC as much as possible
  ARM: dts: da850-evm: Enable tca6416 on baseboard
  arm64: dts: uniphier: Add USB2 PHY nodes
  arm64: dts: uniphier: Add USB3 controller nodes
  ARM: dts: uniphier: Add USB2 PHY nodes
  ARM: dts: uniphier: Add USB3 controller nodes
  arm64: dts: meson-axg: s400: disable emmc
  arm64: dts: meson-axg: s400: add missing emmc pwrseq
  arm64: dts: clearfog-gt-8k: add PCIe slot description
  ARM: dts: at91: sama5d4_xplained: even nand memory partitions
  ARM: dts: at91: sama5d3_xplained: even nand memory partitions
  ARM: dts: at91: at91sam9x5cm: even nand memory partitions
  ARM: dts: at91: sama5d2_ptc_ek: fix bootloader env offsets
  ...
This commit is contained in:
Linus Torvalds 2018-10-29 15:05:20 -07:00
parent c38239b4be be59a3282c
commit 93335e5911
509 changed files with 29255 additions and 6396 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/arm/Samsung/Bootloader-interface.txt
View File

@ -26,6 +26,7 @@ Offset Value Purpose
0x20 0xfcba0d10 (Magic cookie) AFTR
0x24 exynos_cpu_resume_ns AFTR
0x28 + 4*cpu 0x8 (Magic cookie, Exynos3250) AFTR
0x28 0x0 or last value during resume (Exynos542x) System suspend
2. Secure mode

7
Documentation/devicetree/bindings/arm/amlogic.txt
View File

@ -57,12 +57,17 @@ Boards with the Amlogic Meson AXG A113D SoC shall have the following properties:
Required root node property:
compatible: "amlogic,a113d", "amlogic,meson-axg";
Boards with the Amlogic Meson G12A S905D2 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,g12a";
Board compatible values (alphabetically, grouped by SoC):
- "geniatech,atv1200" (Meson6)
- "minix,neo-x8" (Meson8)
- "endless,ec100" (Meson8b)
- "hardkernel,odroid-c1" (Meson8b)
- "tronfy,mxq" (Meson8b)
@ -101,6 +106,8 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,s400" (Meson axg a113d)
- "amlogic,u200" (Meson g12a s905d2)
Amlogic Meson Firmware registers Interface
------------------------------------------

8
Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
View File

@ -42,6 +42,14 @@ Raspberry Pi Compute Module
Required root node properties:
compatible = "raspberrypi,compute-module", "brcm,bcm2835";
Raspberry Pi Compute Module 3
Required root node properties:
compatible = "raspberrypi,3-compute-module", "brcm,bcm2837";
Raspberry Pi Compute Module 3 Lite
Required root node properties:
compatible = "raspberrypi,3-compute-module-lite", "brcm,bcm2837";
Raspberry Pi Zero
Required root node properties:
compatible = "raspberrypi,model-zero", "brcm,bcm2835";

44
Documentation/devicetree/bindings/arm/fsl.txt
View File

@ -57,6 +57,50 @@ i.MX6SLL EVK board
Required root node properties:
- compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
i.MX6 Quad Plus SABRE Smart Device Board
Required root node properties:
- compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
i.MX6 Quad Plus SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
i.MX6 DualLite SABRE Smart Device Board
Required root node properties:
- compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
i.MX6 DualLite/Solo SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
i.MX6 SoloLite EVK Board
Required root node properties:
- compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
i.MX6 UltraLite 14x14 EVK Board
Required root node properties:
- compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
i.MX6 UltraLiteLite 14x14 EVK Board
Required root node properties:
- compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
i.MX6 ULZ 14x14 EVK Board
Required root node properties:
- compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";
i.MX6 SoloX SDB Board
Required root node properties:
- compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
i.MX6 SoloX Sabre Auto Board
Required root node properties:
- compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
i.MX7 SabreSD Board
Required root node properties:
- compatible = "fsl,imx7d-sdb", "fsl,imx7d";
Generic i.MX boards
-------------------

8
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
View File

@ -8,6 +8,14 @@ HiKey960 Board
Required root node properties:
- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
Hi3670 SoC
Required root node properties:
- compatible = "hisilicon,hi3670";
HiKey970 Board
Required root node properties:
- compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
Hi3798cv200 SoC
Required root node properties:
- compatible = "hisilicon,hi3798cv200";

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
View File

@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt2712-apmixedsys", "syscon"
- "mediatek,mt6797-apmixedsys"
- "mediatek,mt7622-apmixedsys"
- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8173-apmixedsys"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
View File

@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt7622-audsys", "syscon"
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
- #clock-cells: Must be 1
The AUDSYS controller uses the common clk binding from

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
View File

@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt2701-bdpsys", "syscon"
- "mediatek,mt2712-bdpsys", "syscon"
- "mediatek,mt7623-bdpsys", "mediatek,mt2701-bdpsys", "syscon"
- #clock-cells: Must be 1
The bdpsys controller uses the common clk binding from

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
View File

@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7622-ethsys", "syscon"
- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
View File

@ -9,6 +9,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt2701-hifsys", "syscon"
- "mediatek,mt7622-hifsys", "syscon"
- "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon"
- #clock-cells: Must be 1
The hifsys controller uses the common clk binding from

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
View File

@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-imgsys", "syscon"
- "mediatek,mt2712-imgsys", "syscon"
- "mediatek,mt6797-imgsys", "syscon"
- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
- "mediatek,mt8173-imgsys", "syscon"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
View File

@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt2712-infracfg", "syscon"
- "mediatek,mt6797-infracfg", "syscon"
- "mediatek,mt7622-infracfg", "syscon"
- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
View File

@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt2712-mmsys", "syscon"
- "mediatek,mt6797-mmsys", "syscon"
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt8173-mmsys", "syscon"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
View File

@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt2701-pericfg", "syscon"
- "mediatek,mt2712-pericfg", "syscon"
- "mediatek,mt7622-pericfg", "syscon"
- "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"
- "mediatek,mt8135-pericfg", "syscon"
- "mediatek,mt8173-pericfg", "syscon"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
View File

@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt2712-topckgen", "syscon"
- "mediatek,mt6797-topckgen"
- "mediatek,mt7622-topckgen"
- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
- "mediatek,mt8135-topckgen"
- "mediatek,mt8173-topckgen"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
View File

@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-vdecsys", "syscon"
- "mediatek,mt2712-vdecsys", "syscon"
- "mediatek,mt6797-vdecsys", "syscon"
- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
- "mediatek,mt8173-vdecsys", "syscon"
- #clock-cells: Must be 1

20
Documentation/devicetree/bindings/arm/rockchip.txt
View File

@ -5,6 +5,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "vamrs,ficus", "rockchip,rk3399";
- 96boards RK3399 Rock960 (ROCK960 Consumer Edition)
Required root node properties:
- compatible = "vamrs,rock960", "rockchip,rk3399";
- Amarula Vyasa RK3288 board
Required root node properties:
- compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
@ -13,6 +17,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "asus,rk3288-tinker", "rockchip,rk3288";
- Asus Tinker board S
Required root node properties:
- compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";
- Kylin RK3036 board:
Required root node properties:
- compatible = "rockchip,kylin-rk3036", "rockchip,rk3036";
@ -59,6 +67,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
- Firefly ROC-RK3399-PC board:
Required root node properties:
- compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
@ -160,6 +172,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "pine64,rock64", "rockchip,rk3328";
- Pine64 RockPro64 board:
Required root node properties:
- compatible = "pine64,rockpro64", "rockchip,rk3399";
- Rockchip PX3 Evaluation board:
Required root node properties:
- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
@ -168,6 +184,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
- Rockchip PX30 Evaluation board:
Required root node properties:
- compatible = "rockchip,px30-evb", "rockchip,px30";
- Rockchip RV1108 Evaluation board
Required root node properties:
- compatible = "rockchip,rv1108-evb", "rockchip,rv1108";

2
Documentation/devicetree/bindings/arm/scu.txt
View File

@ -22,7 +22,7 @@ References:
Example:
scu@a04100000 {
scu@a0410000 {
compatible = "arm,cortex-a9-scu";
reg = <0xa0410000 0x100>;
};

16
Documentation/devicetree/bindings/arm/shmobile.txt
View File

@ -7,6 +7,8 @@ SoCs:
compatible = "renesas,emev2"
- RZ/A1H (R7S72100)
compatible = "renesas,r7s72100"
- RZ/A2 (R7S9210)
compatible = "renesas,r7s9210"
- SH-Mobile AG5 (R8A73A00/SH73A0)
compatible = "renesas,sh73a0"
- R-Mobile APE6 (R8A73A40)
@ -23,6 +25,10 @@ SoCs:
compatible = "renesas,r8a7745"
- RZ/G1C (R8A77470)
compatible = "renesas,r8a77470"
- RZ/G2M (R8A774A1)
compatible = "renesas,r8a774a1"
- RZ/G2E (RA8774C0)
compatible = "renesas,r8a774c0"
- R-Car M1A (R8A77781)
compatible = "renesas,r8a7778"
- R-Car H1 (R8A77790)
@ -107,6 +113,8 @@ Boards:
compatible = "renesas,lager", "renesas,r8a7790"
- M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0))
compatible = "renesas,m3ulcb", "renesas,r8a7796"
- M3NULCB (R-Car Starter Kit Pro, RTP0RC77965SKBX010SA00 (M3-N ES1.1))
compatible = "renesas,m3nulcb", "renesas,r8a77965"
- Marzen (R0P7779A00010S)
compatible = "renesas,marzen", "renesas,r8a7779"
- Porter (M2-LCDP)
@ -143,12 +151,12 @@ Boards:
compatible = "renesas,wheat", "renesas,r8a7792"
Most Renesas ARM SoCs have a Product Register that allows to retrieve SoC
product and revision information. If present, a device node for this register
should be added.
Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
allows to retrieve SoC product and revision information. If present, a device
node for this register should be added.
Required properties:
- compatible: Must be "renesas,prr".
- compatible: Must be "renesas,prr" or "renesas,bsid"
- reg: Base address and length of the register block.

11
Documentation/devicetree/bindings/arm/marvell/marvell,berlin.txt → Documentation/devicetree/bindings/arm/syna.txt
View File

@ -1,4 +1,9 @@
Marvell Berlin SoC Family Device Tree Bindings
Synaptics SoC Device Tree Bindings
According to https://www.synaptics.com/company/news/conexant-marvell
Synaptics has acquired the Multimedia Solutions Business of Marvell, so
berlin SoCs are now Synaptics' SoCs now.
---------------------------------------------------------------
Work in progress statement:
@ -13,6 +18,10 @@ stable binding/ABI.
---------------------------------------------------------------
Boards with the Synaptics AS370 SoC shall have the following properties:
Required root node property:
compatible: "syna,as370"
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
shall have the following properties:

9
Documentation/devicetree/bindings/arm/tegra.txt
View File

@ -47,12 +47,17 @@ board-specific compatible values:
nvidia,ventana
toradex,apalis_t30
toradex,apalis_t30-eval
toradex,apalis_t30-v1.1
toradex,apalis_t30-v1.1-eval
toradex,apalis-tk1
toradex,apalis-tk1-eval
toradex,colibri_t20-512
toradex,apalis-tk1-v1.2
toradex,apalis-tk1-v1.2-eval
toradex,colibri_t20
toradex,colibri_t20-eval-v3
toradex,colibri_t20-iris
toradex,colibri_t30
toradex,colibri_t30-eval-v3
toradex,iris
Trusted Foundations
-------------------------------------------

93
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
View File

@ -34,3 +34,96 @@ Board DTS:
pmc@c360000 {
nvidia,invert-interrupt;
};
== Pad Control ==
On Tegra SoCs a pad is a set of pins which are configured as a group.
The pin grouping is a fixed attribute of the hardware. The PMC can be
used to set pad power state and signaling voltage. A pad can be either
in active or power down mode. The support for power state and signaling
voltage configuration varies depending on the pad in question. 3.3 V and
1.8 V signaling voltages are supported on pins where software
controllable signaling voltage switching is available.
Pad configurations are described with pin configuration nodes which
are placed under the pmc node and they are referred to by the pinctrl
client properties. For more information see
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
The following pads are present on Tegra186:
csia csib dsi mipi-bias
pex-clk-bias pex-clk3 pex-clk2 pex-clk1
usb0 usb1 usb2 usb-bias
uart audio hsic dbg
hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv
sdmmc4 cam dsib dsic
dsid csic csid csie
dsif spi ufs dmic-hv
edp sdmmc1-hv sdmmc3-hv conn
audio-hv ao-hv
Required pin configuration properties:
- pins: A list of strings, each of which contains the name of a pad
to be configured.
Optional pin configuration properties:
- low-power-enable: Configure the pad into power down mode
- low-power-disable: Configure the pad into active mode
- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
The values are defined in
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
Note: The power state can be configured on all of the above pads except
for ao-hv. Following pads have software configurable signaling
voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv,
ao-hv.
Pad configuration state example:
pmc: pmc@7000e400 {
compatible = "nvidia,tegra186-pmc";
reg = <0 0x0c360000 0 0x10000>,
<0 0x0c370000 0 0x10000>,
<0 0x0c380000 0 0x10000>,
<0 0x0c390000 0 0x10000>;
reg-names = "pmc", "wake", "aotag", "scratch";
...
sdmmc1_3v3: sdmmc1-3v3 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc1_1v8: sdmmc1-1v8 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
hdmi_off: hdmi-off {
pins = "hdmi";
low-power-enable;
}
hdmi_on: hdmi-on {
pins = "hdmi";
low-power-disable;
}
};
Pinctrl client example:
sdmmc1: sdhci@3400000 {
...
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
};
...
sor0: sor@15540000 {
...
pinctrl-0 = <&hdmi_off>;
pinctrl-1 = <&hdmi_on>;
pinctrl-names = "hdmi-on", "hdmi-off";
};

103
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
View File

@ -195,3 +195,106 @@ Example:
power-domains = <&pd_audio>;
...
};
== Pad Control ==
On Tegra SoCs a pad is a set of pins which are configured as a group.
The pin grouping is a fixed attribute of the hardware. The PMC can be
used to set pad power state and signaling voltage. A pad can be either
in active or power down mode. The support for power state and signaling
voltage configuration varies depending on the pad in question. 3.3 V and
1.8 V signaling voltages are supported on pins where software
controllable signaling voltage switching is available.
The pad configuration state nodes are placed under the pmc node and they
are referred to by the pinctrl client properties. For more information
see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
The pad name should be used as the value of the pins property in pin
configuration nodes.
The following pads are present on Tegra124 and Tegra132:
audio bb cam comp
csia csb cse dsi
dsib dsic dsid hdmi
hsic hv lvds mipi-bias
nand pex-bias pex-clk1 pex-clk2
pex-cntrl sdmmc1 sdmmc3 sdmmc4
sys_ddc uart usb0 usb1
usb2 usb_bias
The following pads are present on Tegra210:
audio audio-hv cam csia
csib csic csid csie
csif dbg debug-nonao dmic
dp dsi dsib dsic
dsid emmc emmc2 gpio
hdmi hsic lvds mipi-bias
pex-bias pex-clk1 pex-clk2 pex-cntrl
sdmmc1 sdmmc3 spi spi-hv
uart usb0 usb1 usb2
usb3 usb-bias
Required pin configuration properties:
- pins: Must contain name of the pad(s) to be configured.
Optional pin configuration properties:
- low-power-enable: Configure the pad into power down mode
- low-power-disable: Configure the pad into active mode
- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8
or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
The values are defined in
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
Note: The power state can be configured on all of the Tegra124 and
Tegra132 pads. None of the Tegra124 or Tegra132 pads support
signaling voltage switching.
Note: All of the listed Tegra210 pads except pex-cntrl support power
state configuration. Signaling voltage switching is supported on
following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio,
pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart.
Pad configuration state example:
pmc: pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
...
sdmmc1_3v3: sdmmc1-3v3 {
pins = "sdmmc1";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc1_1v8: sdmmc1-1v8 {
pins = "sdmmc1";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
hdmi_off: hdmi-off {
pins = "hdmi";
low-power-enable;
}
hdmi_on: hdmi-on {
pins = "hdmi";
low-power-disable;
}
};
Pinctrl client example:
sdmmc1: sdhci@700b0000 {
...
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
};
...
sor@54540000 {
...
pinctrl-0 = <&hdmi_off>;
pinctrl-1 = <&hdmi_on>;
pinctrl-names = "hdmi-on", "hdmi-off";
};

2
Documentation/devicetree/bindings/arm/ux500/boards.txt
View File

@ -60,7 +60,7 @@ Example:
<0xa0410100 0x100>;
};
scu@a04100000 {
scu@a0410000 {
compatible = "arm,cortex-a9-scu";
reg = <0xa0410000 0x100>;
};

8
Documentation/devicetree/bindings/clock/imx6q-clock.txt
View File

@ -6,6 +6,14 @@ Required properties:
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
Optional properties:
- fsl,pmic-stby-poweroff: Configure CCM to assert PMIC_STBY_REQ signal
on power off.
Use this property if the SoC should be powered off by external power
management IC (PMIC) triggered via PMIC_STBY_REQ signal.
Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should
be using "syscon-poweroff" driver instead.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
for the full list of i.MX6 Quad and DualLite clock IDs.

4
Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
View File

@ -41,6 +41,8 @@ Required properties:
- compatible : must be one of the following string:
"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
"mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
generation one m4u HW.
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
- reg : m4u register base and size.
- interrupts : the interrupt of m4u.
@ -51,7 +53,7 @@ Required properties:
according to the local arbiter index, like larb0, larb1, larb2...
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
Specifies the mtk_m4u_id as defined in
dt-binding/memory/mt2701-larb-port.h for mt2701,
dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
dt-binding/memory/mt2712-larb-port.h for mt2712, and
dt-binding/memory/mt8173-larb-port.h for mt8173.

1
Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt
View File

@ -5,6 +5,7 @@ Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs
Required properties:
- compatible : must be one of the following string:
"mediatek,mt8173-jpgdec"
"mediatek,mt7623-jpgdec", "mediatek,mt2701-jpgdec"
"mediatek,mt2701-jpgdec"
- reg : physical base address of the jpeg decoder registers and length of
memory mapped region.

1
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
View File

@ -17,6 +17,7 @@ Required properties:
- compatible : must be one of :
"mediatek,mt2701-smi-common"
"mediatek,mt2712-smi-common"
"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
"mediatek,mt8173-smi-common"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.

3
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
View File

@ -6,6 +6,7 @@ Required properties:
- compatible : must be one of :
"mediatek,mt2701-smi-larb"
"mediatek,mt2712-smi-larb"
"mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
"mediatek,mt8173-smi-larb"
- reg : the register and size of this local arbiter.
- mediatek,smi : a phandle to the smi_common node.
@ -16,7 +17,7 @@ Required properties:
the register.
- "smi" : It's the clock for transfer data and command.
Required property for mt2701 and mt2712:
Required property for mt2701, mt2712 and mt7623:
- mediatek,larb-id :the hardware id of this larb.
Example:

36
Documentation/devicetree/bindings/net/dsa/b53.txt
View File

@ -46,6 +46,42 @@ Required properties:
"brcm,bcm6328-switch"
"brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"
Required properties for BCM585xx/586xx/88312 SoCs:
- reg: a total of 3 register base addresses, the first one must be the
Switch Register Access block base, the second is the port 5/4 mux
configuration register and the third one is the SGMII configuration
and status register base address.
- interrupts: a total of 13 interrupts must be specified, in the following
order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,
then the timestamping interrupt and the sleep timer interrupts for ports
5,7,8.
Optional properties for BCM585xx/586xx/88312 SoCs:
- reg-names: a total of 3 names matching the 3 base register address, must
be in the following order:
"srab"
"mux_config"
"sgmii_config"
- interrupt-names: a total of 13 names matching the 13 interrupts specified
must be in the following order:
"link_state_p0"
"link_state_p1"
"link_state_p2"
"link_state_p3"
"link_state_p4"
"link_state_p5"
"link_state_p7"
"link_state_p8"
"phy"
"ts"
"imp_sleep_timer_p5"
"imp_sleep_timer_p7"
"imp_sleep_timer_p8"
See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required and optional properties.

1
Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt
View File

@ -7,6 +7,7 @@ Required properties:
"allwinner,sun8i-a83t-sid"
"allwinner,sun8i-h3-sid"
"allwinner,sun50i-a64-sid"
"allwinner,sun50i-h5-sid"
- reg: Should contain registers location and length

2
Documentation/devicetree/bindings/power/actions,owl-sps.txt
View File

@ -3,11 +3,13 @@ Actions Semi Owl Smart Power System (SPS)
Required properties:
- compatible : "actions,s500-sps" for S500
"actions,s700-sps" for S700
"actions,s900-sps" for S900
- reg : Offset and length of the register set for the device.
- #power-domain-cells : Must be 1.
See macros in:
include/dt-bindings/power/owl-s500-powergate.h for S500
include/dt-bindings/power/owl-s700-powergate.h for S700
include/dt-bindings/power/owl-s900-powergate.h for S900
Example:

2
Documentation/devicetree/bindings/soc/rockchip/grf.txt
View File

@ -13,6 +13,7 @@ On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,
Required Properties:
- compatible: GRF should be one of the following:
- "rockchip,px30-grf", "syscon": for px30
- "rockchip,rk3036-grf", "syscon": for rk3036
- "rockchip,rk3066-grf", "syscon": for rk3066
- "rockchip,rk3188-grf", "syscon": for rk3188
@ -23,6 +24,7 @@ Required Properties:
- "rockchip,rk3399-grf", "syscon": for rk3399
- "rockchip,rv1108-grf", "syscon": for rv1108
- compatible: PMUGRF should be one of the following:
- "rockchip,px30-pmugrf", "syscon": for px30
- "rockchip,rk3368-pmugrf", "syscon": for rk3368
- "rockchip,rk3399-pmugrf", "syscon": for rk3399
- compatible: SGRF should be one of the following

1
Documentation/devicetree/bindings/usb/dwc2.txt
View File

@ -6,6 +6,7 @@ Required properties:
- brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
- hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
- rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
- "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2": for px30 Soc;
- "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
- "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
- "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;

2
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -115,6 +115,7 @@ elan Elan Microelectronic Corp.
embest Shenzhen Embest Technology Co., Ltd.
emmicro EM Microelectronic
emtrion emtrion GmbH
endless Endless Mobile, Inc.
energymicro Silicon Laboratories (formerly Energy Micro AS)
engicam Engicam S.r.l.
epcos EPCOS AG
@ -301,6 +302,7 @@ pine64 Pine64
pixcir PIXCIR MICROELECTRONICS Co., Ltd
plathome Plat'Home Co., Ltd.
plda PLDA
plx Broadcom Corporation (formerly PLX Technology)
portwell Portwell Inc.
poslab Poslab Technology Co., Ltd.
powervr PowerVR (deprecated, use img)

18
arch/arm/boot/dts/Makefile
View File

@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
bcm2836-rpi-2-b.dtb \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
bcm2837-rpi-cm3-io3.dtb \
bcm2835-rpi-zero.dtb \
bcm2835-rpi-zero-w.dtb
dtb-$(CONFIG_ARCH_BCM_5301X) += \
@ -321,6 +322,7 @@ dtb-$(CONFIG_MACH_MESON6) += \
meson6-atv1200.dtb
dtb-$(CONFIG_MACH_MESON8) += \
meson8-minix-neo-x8.dtb \
meson8b-ec100.dtb \
meson8b-mxq.dtb \
meson8b-odroidc1.dtb \
meson8m2-mxiii-plus.dtb
@ -548,6 +550,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb \
imx6ul-ccimx6ulsbcexpress.dtb \
imx6ul-ccimx6ulsbcpro.dtb \
imx6ul-geam.dtb \
imx6ul-isiot-emmc.dtb \
imx6ul-isiot-nand.dtb \
@ -559,7 +562,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ulz-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-emmc-eval-v3.dtb \
@ -649,6 +653,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
omap3-gta04a3.dtb \
omap3-gta04a4.dtb \
omap3-gta04a5.dtb \
omap3-gta04a5one.dtb \
omap3-ha.dtb \
omap3-ha-lcd.dtb \
omap3-igep0020.dtb \
@ -706,6 +711,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-evmsk.dtb \
am335x-icev2.dtb \
am335x-lxm.dtb \
am335x-moxa-uc-2101.dtb \
am335x-moxa-uc-8100-me-t.dtb \
am335x-nano.dtb \
am335x-pdu001.dtb \
@ -864,6 +870,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-r89.dtb \
rk3288-rock2-square.dtb \
rk3288-tinker.dtb \
rk3288-tinker-s.dtb \
rk3288-veyron-brain.dtb \
rk3288-veyron-jaq.dtb \
rk3288-veyron-jerry.dtb \
@ -892,7 +899,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_de0_sockit.dtb \
socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sodia.dtb \
@ -1033,6 +1040,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h2-plus-orangepi-r1.dtb \
sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-h3-bananapi-m2-plus-v1.2.dtb \
sun8i-h3-beelink-x2.dtb \
sun8i-h3-libretech-all-h3-cc.dtb \
sun8i-h3-nanopi-m1.dtb \
@ -1046,6 +1054,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-pc-plus.dtb \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-orangepi-zero-plus2.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-nintendo-nes-classic.dtb \
sun8i-r16-nintendo-super-nes-classic.dtb \
@ -1061,6 +1070,7 @@ dtb-$(CONFIG_ARCH_TANGO) += \
tango4-vantage-1172.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-harmony.dtb \
tegra20-colibri-eval-v3.dtb \
tegra20-colibri-iris.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
@ -1071,6 +1081,7 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-ventana.dtb
dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-apalis-eval.dtb \
tegra30-apalis-v1.1-eval.dtb \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
@ -1149,6 +1160,7 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-db-88f6820-amc.dtb \
armada-385-db-ap.dtb \
armada-385-linksys-caiman.dtb \
armada-385-linksys-cobra.dtb \
@ -1199,6 +1211,8 @@ dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-bmc-arm-centriq2400-rep.dtb \
aspeed-bmc-arm-stardragon4800-rep2.dtb \
aspeed-bmc-facebook-tiogapass.dtb \
aspeed-bmc-intel-s2600wf.dtb \
aspeed-bmc-opp-lanyang.dtb \
aspeed-bmc-opp-palmetto.dtb \

6
arch/arm/boot/dts/am335x-bone-common.dtsi
View File

@ -379,7 +379,7 @@ ldo4_reg: regulator@6 {
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "mii";
};
@ -396,6 +396,10 @@ &davinci_mdio {
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
&mmc1 {

5
arch/arm/boot/dts/am335x-boneblack-common.dtsi
View File

@ -7,6 +7,7 @@
*/
#include <dt-bindings/display/tda998x.h>
#include <dt-bindings/interrupt-controller/irq.h>
&ldo3_reg {
regulator-min-microvolt = <1800000>;
@ -88,9 +89,11 @@ lcdc_0: endpoint@0 {
};
&i2c0 {
tda19988: tda19988 {
tda19988: tda19988@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
nxp,calib-gpios = <&gpio1 25 0>;
interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default", "off";
pinctrl-0 = <&nxp_hdmi_bonelt_pins>;

6
arch/arm/boot/dts/am335x-chiliboard.dts
View File

@ -140,10 +140,14 @@ &davinci_mdio {
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "rmii";
};

6
arch/arm/boot/dts/am335x-cm-t335.dts
View File

@ -486,10 +486,14 @@ &davinci_mdio {
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-txid";
};

12
arch/arm/boot/dts/am335x-evm.dts
View File

@ -713,6 +713,7 @@ &mac {
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
slaves = <1>;
};
&davinci_mdio {
@ -720,15 +721,14 @@ &davinci_mdio {
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-txid";
};

12
arch/arm/boot/dts/am335x-evmsk.dts
View File

@ -639,16 +639,24 @@ &davinci_mdio {
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-handle = <&ethphy1>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
};

13
arch/arm/boot/dts/am335x-igep0033.dtsi
View File

@ -102,15 +102,24 @@ &mac {
&davinci_mdio {
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "rmii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-handle = <&ethphy1>;
phy-mode = "rmii";
};

12
arch/arm/boot/dts/am335x-lxm.dts
View File

@ -317,13 +317,13 @@ &cppi41dma {
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <5>;
phy-handle = <&ethphy0>;
phy-mode = "rmii";
dual_emac_res_vlan = <2>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <4>;
phy-handle = <&ethphy1>;
phy-mode = "rmii";
dual_emac_res_vlan = <3>;
};
@ -345,6 +345,14 @@ &davinci_mdio {
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@5 {
reg = <5>;
};
ethphy1: ethernet-phy@4 {
reg = <4>;
};
};
&mmc1 {

249
arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi Normal file
View File

@ -0,0 +1,249 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/
*
* Authors: SZ Lin (林上智) <sz.lin@moxa.com>
* Wes Huang (黃淵河) <wes.huang@moxa.com>
* Fero JD Zhou (周俊達) <FeroJD.Zhou@moxa.com>
*/
#include "am33xx.dtsi"
/ {
vbat: vbat-regulator {
compatible = "regulator-fixed";
};
/* Power supply provides a fixed 3.3V @3A */
vmmcsd_fixed: vmmcsd-regulator {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
buttons: push_button {
compatible = "gpio-keys";
};
};
&am33xx_pinmux {
pinctrl-names = "default";
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
push_button_pins: pinmux_push_button {
pinctrl-single,pins = <
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2_23 */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
mmc1_pins_default: pinmux_mmc1_pins {
pinctrl-single,pins = <
/* eMMC */
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad12.mmc1_dat0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad13.mmc1_dat1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad14.mmc1_dat2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad15.mmc1_dat3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad8.mmc1_dat4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad9.mmc1_dat5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad10.mmc1_dat6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad11.mmc1_dat7 */
AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
>;
};
spi0_pins: pinmux_spi0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
>;
};
};
&uart0 {
/* Console */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <400000>;
eeprom: eeprom@50 {
compatible = "atmel,24c16";
pagesize = <16>;
reg = <0x50>;
};
rtc_wdt: rtc_wdt@68 {
compatible = "dallas,ds1374";
reg = <0x68>;
};
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
/* Power */
&vbat {
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
&mac {
pinctrl-names = "default";
pinctrl-0 = <&cpsw_default>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default";
pinctrl-0 = <&davinci_mdio_default>;
status = "okay";
};
&cpsw_emac0 {
status = "okay";
};
&cpsw_emac1 {
status = "okay";
};
&phy_sel {
reg= <0x44e10650 0xf5>;
rmii-clock-ext;
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};
&gpio0 {
ti,no-reset-on-init;
};
&mmc2 {
pinctrl-names = "default";
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <8>;
pinctrl-0 = <&mmc1_pins_default>;
ti,non-removable;
status = "okay";
};
&buttons {
pinctrl-names = "default";
pinctrl-0 = <&push_button_pins>;
#address-cells = <1>;
#size-cells = <0>;
button@0 {
label = "push_button";
linux,code = <0x100>;
gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
};
};
/* SPI Busses */
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
m25p80@0 {
compatible = "mx25l6405d";
spi-max-frequency = <40000000>;
reg = <0>;
spi-cpol;
spi-cpha;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* reg : The partition's offset and size within the mtd bank. */
partitions@0 {
label = "MLO";
reg = <0x0 0x80000>;
};
partitions@1 {
label = "U-Boot";
reg = <0x80000 0x100000>;
};
partitions@2 {
label = "U-Boot Env";
reg = <0x180000 0x40000>;
};
};
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
tpm_spi_tis@0 {
compatible = "tcg,tpm_tis-spi";
reg = <0>;
spi-max-frequency = <500000>;
};
};

69
arch/arm/boot/dts/am335x-moxa-uc-2101.dts Normal file
View File

@ -0,0 +1,69 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/
*
* Authors: SZ Lin (林上智) <sz.lin@moxa.com>
* Wes Huang (黃淵河) <wes.huang@moxa.com>
* Fero JD Zhou (周俊達) <FeroJD.Zhou@moxa.com>
*/
/dts-v1/;
#include "am335x-moxa-uc-2100-common.dtsi"
/ {
model = "Moxa UC-2101";
compatible = "moxa,uc-2101", "ti,am33xx";
leds {
compatible = "gpio-leds";
led1 {
label = "UC2100:GREEN:USER";
gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
};
&am33xx_pinmux {
pinctrl-names = "default";
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_refclk.rmii1_refclk */
>;
};
spi1_pins: pinmux_spi1 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE4) /* ecap0_in_pwm0_out.spi1_sclk */
AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE4) /* uart1_ctsn.spi1_cs0 */
AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE4) /* uart0_ctsn.spi1_d0 */
AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart0_rtsn.spi1_d1 */
>;
};
};
&davinci_mdio {
phy0: ethernet-phy@4 {
reg = <4>;
};
};
&cpsw_emac0 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rmii";
};
&cpsw_emac1 {
status = "disabled";
};

12
arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
View File

@ -422,18 +422,26 @@ &davinci_mdio {
pinctrl-names = "default";
pinctrl-0 = <&davinci_mdio_default>;
status = "okay";
ethphy0: ethernet-phy@4 {
reg = <4>;
};
ethphy1: ethernet-phy@5 {
reg = <5>;
};
};
&cpsw_emac0 {
status = "okay";
phy_id = <&davinci_mdio>, <4>;
phy-handle = <&ethphy0>;
phy-mode = "rmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
status = "okay";
phy_id = <&davinci_mdio>, <5>;
phy-handle = <&ethphy1>;
phy-mode = "rmii";
dual_emac_res_vlan = <2>;
};

12
arch/arm/boot/dts/am335x-nano.dts
View File

@ -380,16 +380,24 @@ &mac {
&davinci_mdio {
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "mii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-handle = <&ethphy1>;
phy-mode = "mii";
dual_emac_res_vlan = <2>;
};

8
arch/arm/boot/dts/am335x-osd3358-sm-red.dts
View File

@ -161,7 +161,7 @@ ax8975@c {
invensense,key = [4e cc 7e eb f6 1e 35 22 00 34 0d 65 32 e9 94 89];*/
};
bmp280: pressure@78 {
bmp280: pressure@76 {
compatible = "bosch,bmp280";
reg = <0x76>;
};
@ -424,7 +424,7 @@ &i2c2 {
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <4>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-txid";
};
@ -441,6 +441,10 @@ &davinci_mdio {
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@4 {
reg = <4>;
};
};
&mmc1 {

14
arch/arm/boot/dts/am335x-pdu001.dts
View File

@ -373,7 +373,7 @@ &spi1 {
ti,pindir-d0-out-d1-in;
status = "okay";
cfaf240320a032t {
display-controller@0 {
compatible = "orisetech,otm3225a";
reg = <0>;
spi-max-frequency = <1000000>;
@ -533,16 +533,24 @@ &davinci_mdio {
pinctrl-names = "default";
pinctrl-0 = <&davinci_mdio_default>;
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "mii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-handle = <&ethphy1>;
phy-mode = "mii";
dual_emac_res_vlan = <2>;
};

12
arch/arm/boot/dts/am335x-pepper.dts
View File

@ -265,13 +265,13 @@ AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 */
/* Ethernet */
&cpsw_emac0 {
status = "okay";
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
};
&cpsw_emac1 {
status = "okay";
phy_id = <&davinci_mdio>, <1>;
phy-handle = <&ethphy1>;
phy-mode = "rgmii";
};
@ -279,6 +279,14 @@ &davinci_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
};
&mac {

6
arch/arm/boot/dts/am335x-sancloud-bbe.dts
View File

@ -103,10 +103,14 @@ &davinci_mdio {
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-txid";
};

1
arch/arm/boot/dts/am335x-shc.dts
View File

@ -206,7 +206,6 @@ &mac {
status = "okay";
slaves = <1>;
cpsw_emac0: slave@4a100200 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
phy-handle = <&ethernetphy0>;
};

220
arch/arm/boot/dts/am3517-evm-ui.dtsi Normal file
View File

@ -0,0 +1,220 @@
/*
* Copyright (C) 2018 Logic PD, Inc - http://www.logicpd.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/input/input.h>
/ {
codec1 {
compatible = "simple-audio-card";
simple-audio-card,name = "tlv320aic23-hifi";
simple-audio-card,widgets =
"Microphone", "Mic In",
"Line", "Line In",
"Line", "Line Out";
simple-audio-card,routing =
"Line Out", "LOUT",
"Line Out", "ROUT",
"LLINEIN", "Line In",
"RLINEIN", "Line In",
"MICIN", "Mic In";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sound_master>;
simple-audio-card,frame-master = <&sound_master>;
simple-audio-card,cpu {
sound-dai = <&mcbsp1>;
};
sound_master: simple-audio-card,codec {
sound-dai = <&tlv320aic23_1>;
system-clock-frequency = <12000000>;
};
};
codec2 {
compatible = "simple-audio-card";
simple-audio-card,name = "tlv320aic23-hifi";
simple-audio-card,widgets =
"Microphone", "Mic In",
"Line", "Line In",
"Line", "Line Out";
simple-audio-card,routing =
"Line Out", "LOUT",
"Line Out", "ROUT",
"LLINEIN", "Line In",
"RLINEIN", "Line In",
"MICIN", "Mic In";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sound_master2>;
simple-audio-card,frame-master = <&sound_master2>;
simple-audio-card,cpu {
sound-dai = <&mcbsp2>;
};
sound_master2: simple-audio-card,codec {
sound-dai = <&tlv320aic23_2>;
system-clock-frequency = <12000000>;
};
};
expander-keys {
compatible = "gpio-keys-polled";
poll-interval = <100>;
record {
label = "Record";
/* linux,code = <BTN_0>; */
gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>;
};
play {
label = "Play";
linux,code = <KEY_PLAY>;
gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>;
};
Stop {
label = "Stop";
linux,code = <KEY_STOP>;
gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>;
};
fwd {
label = "FWD";
linux,code = <KEY_FASTFORWARD>;
gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>;
};
rwd {
label = "RWD";
linux,code = <KEY_REWIND>;
gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>;
};
shift {
label = "Shift";
linux,code = <KEY_LEFTSHIFT>;
gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>;
};
Mode {
label = "Mode";
linux,code = <BTN_MODE>;
gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>;
};
Menu {
label = "Menu";
linux,code = <KEY_MENU>;
gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>;
};
Up {
label = "Up";
linux,code = <KEY_UP>;
gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>;
};
Down {
label = "Down";
linux,code = <KEY_DOWN>;
gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>;
};
};
};
&i2c2 {
/* Audio codecs */
tlv320aic23_1: codec@1a {
compatible = "ti,tlv320aic23";
reg = <0x1a>;
#sound-dai-cells= <0>;
status = "okay";
};
tlv320aic23_2: codec@1b {
compatible = "ti,tlv320aic23";
reg = <0x1b>;
#sound-dai-cells= <0>;
status = "okay";
};
};
&i2c3 {
/* Audio codecs */
tlv320aic23_3: codec@1a {
compatible = "ti,tlv320aic23";
reg = <0x1a>;
#sound-dai-cells= <0>;
status = "okay";
};
/* GPIO Expanders */
tca6416_2: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&vdd_io_reg>;
};
tca6416_3: gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&vdd_io_reg>;
};
/* TVP5146 Analog Video decoder input */
tvp5146@5c {
compatible = "ti,tvp5146m2";
reg = <0x5c>;
};
};
&mcbsp1 {
status = "ok";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcbsp1_pins>;
};
&mcbsp2 {
status = "ok";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
};
&omap3_pmx_core {
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */
OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */
OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp1_fsx */
OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */
>;
};
mcbsp2_pins: pinmux_mcbsp2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */
OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */
OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */
>;
};
};

1
arch/arm/boot/dts/am3517-evm.dts
View File

@ -9,6 +9,7 @@
#include "am3517.dtsi"
#include "am3517-som.dtsi"
#include "am3517-evm-ui.dtsi"
#include <dt-bindings/input/input.h>
/ {

2
arch/arm/boot/dts/am4372.dtsi
View File

@ -1101,7 +1101,7 @@ usb2: usb@483d0000 {
};
};
qspi: qspi@47900000 {
qspi: spi@47900000 {
compatible = "ti,am4372-qspi";
reg = <0x47900000 0x100>,
<0x30000000 0x4000000>;

12
arch/arm/boot/dts/am437x-cm-t43.dts
View File

@ -339,16 +339,24 @@ &davinci_mdio {
pinctrl-names = "default";
pinctrl-0 = <&davinci_mdio_default>;
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-handle = <&ethphy1>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
};

6
arch/arm/boot/dts/am437x-gp-evm.dts
View File

@ -831,10 +831,14 @@ &davinci_mdio {
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
};

6
arch/arm/boot/dts/am437x-idk-evm.dts
View File

@ -499,10 +499,14 @@ &davinci_mdio {
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
};

12
arch/arm/boot/dts/am437x-sk-evm.dts
View File

@ -799,16 +799,24 @@ &davinci_mdio {
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@4 {
reg = <4>;
};
ethphy1: ethernet-phy@5 {
reg = <5>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <4>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <5>;
phy-handle = <&ethphy1>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
};

6
arch/arm/boot/dts/am43x-epos-evm.dts
View File

@ -575,10 +575,14 @@ &davinci_mdio {
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethphy0: ethernet-phy@16 {
reg = <16>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <16>;
phy-handle = <&ethphy0>;
phy-mode = "rmii";
};

84
arch/arm/boot/dts/am571x-idk.dts
View File

@ -64,6 +64,82 @@ mmc0-led {
linux,default-trigger = "mmc0";
};
};
idk-leds {
status = "disabled";
compatible = "gpio-leds";
red0-led {
label = "idk:red0";
gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
green0-led {
label = "idk:green0";
gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
blue0-led {
label = "idk:blue0";
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
red1-led {
label = "idk:red1";
gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
green1-led {
label = "idk:green1";
gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
blue1-led {
label = "idk:blue1";
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
red2-led {
label = "idk:red2";
gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
green2-led {
label = "idk:green2";
gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
blue2-led {
label = "idk:blue2";
gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
red3-led {
label = "idk:red3";
gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
green3-led {
label = "idk:green3";
gpios = <&gpio7 25 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
blue3-led {
label = "idk:blue3";
gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
};
&extcon_usb2 {
@ -71,6 +147,10 @@ &extcon_usb2 {
vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>;
};
&sn65hvs882 {
load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
@ -114,7 +194,3 @@ &mmc2 {
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
};
&cpu0 {
vdd-supply = <&smps12_reg>;
};

76
arch/arm/boot/dts/am572x-idk-common.dtsi
View File

@ -55,6 +55,82 @@ mmc0-led {
linux,default-trigger = "mmc0";
};
};
idk-leds {
status = "disabled";
compatible = "gpio-leds";
red0-led {
label = "idk:red0";
gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
green0-led {
label = "idk:green0";
gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
blue0-led {
label = "idk:blue0";
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
red1-led {
label = "idk:red1";
gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
green1-led {
label = "idk:green1";
gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
blue1-led {
label = "idk:blue1";
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
red2-led {
label = "idk:red2";
gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
green2-led {
label = "idk:green2";
gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
blue2-led {
label = "idk:blue2";
gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
red3-led {
label = "idk:red3";
gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
green3-led {
label = "idk:green3";
gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
blue3-led {
label = "idk:blue3";
gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
};
&extcon_usb2 {

4
arch/arm/boot/dts/am572x-idk.dts
View File

@ -36,7 +36,3 @@ &mmc2 {
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20>;
};
&cpu0 {
vdd-supply = <&smps12_reg>;
};

14
arch/arm/boot/dts/am57xx-cl-som-am57x.dts
View File

@ -518,7 +518,7 @@ partition@100000 {
};
/* touch controller */
ads7846@0 {
touchscreen@1 {
pinctrl-names = "default";
pinctrl-0 = <&ads7846_pins>;
@ -558,13 +558,13 @@ &mac {
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <0>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-handle = <&ethphy1>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <1>;
};
@ -573,6 +573,14 @@ &davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_pins_default>;
pinctrl-1 = <&davinci_mdio_pins_sleep>;
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
};
&usb2_phy1 {

18
arch/arm/boot/dts/am57xx-idk-common.dtsi
View File

@ -372,17 +372,27 @@ &mac {
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-handle = <&ethphy1>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
};
&davinci_mdio {
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
};
&usb2_phy1 {
phy-supply = <&ldousb_reg>;
};
@ -478,3 +488,7 @@ partition@6 {
};
};
};
&cpu0 {
vdd-supply = <&smps12_reg>;
};

2
arch/arm/boot/dts/arm-realview-eb.dtsi
View File

@ -371,7 +371,7 @@ serial3: serial@1000c000 {
clock-names = "uartclk", "apb_pclk";
};
ssp: ssp@1000d000 {
ssp: spi@1000d000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x1000d000 0x1000>;
clocks = <&sspclk>, <&pclk>;

2
arch/arm/boot/dts/arm-realview-pb1176.dts
View File

@ -380,7 +380,7 @@ pb1176_gpio0: gpio@1010a000 {
clock-names = "apb_pclk";
};
pb1176_ssp: ssp@1010b000 {
pb1176_ssp: spi@1010b000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x1010b000 0x1000>;
interrupt-parent = <&intc_dc1176>;

2
arch/arm/boot/dts/arm-realview-pb11mp.dts
View File

@ -523,7 +523,7 @@ pb11mp_serial3: serial@1000c000 {
clock-names = "uartclk", "apb_pclk";
};
ssp@1000d000 {
spi@1000d000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x1000d000 0x1000>;
interrupt-parent = <&intc_pb11mp>;

2
arch/arm/boot/dts/arm-realview-pbx.dtsi
View File

@ -362,7 +362,7 @@ serial2: serial@1000b000 {
clock-names = "uartclk", "apb_pclk";
};
ssp: ssp@1000d000 {
ssp: spi@1000d000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x1000d000 0x1000>;
clocks = <&sspclk>, <&pclk>;

155
arch/arm/boot/dts/armada-385-db-88f6820-amc.dts Normal file
View File

@ -0,0 +1,155 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Marvell Armada 385 AMC board
* (DB-88F6820-AMC)
*
* Copyright (C) 2017 Allied Telesis Labs
*/
/dts-v1/;
#include "armada-385.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada 385 AMC";
compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
spi1 = &spi1;
};
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
&uart0 {
/*
* Exported on the micro USB connector CON3
* through an FTDI
*/
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&eth0 {
pinctrl-names = "default";
/*
* The Reference Clock 0 is used to provide a
* clock to the PHY
*/
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
&eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "sgmii";
};
&usb0 {
status = "okay";
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
phy0: ethernet-phy@1 {
reg = <1>;
};
phy1: ethernet-phy@0 {
reg = <0>;
};
};
&nand_controller {
status = "okay";
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0";
nand-rb = <0>;
nand-on-flash-bbt;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000000 0x40000000>;
label = "user";
};
};
};
};
&pciec {
status = "okay";
};
&pcie1 {
/* Port 0, Lane 0 */
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000000 0x00100000>;
label = "u-boot";
};
partition@100000 {
reg = <0x00100000 0x00040000>;
label = "u-boot-env";
};
};
};
};
&refclk {
clock-frequency = <20000000>;
};

2
arch/arm/boot/dts/armada-388-clearfog.dtsi
View File

@ -48,7 +48,7 @@ sdhci@d8000 {
&clearfog_sdhci_cd_pins>;
pinctrl-names = "default";
status = "okay";
vmmc = <&reg_3p3v>;
vmmc-supply = <&reg_3p3v>;
wp-inverted;
};

4
arch/arm/boot/dts/armada-xp-98dx3236.dtsi
View File

@ -189,7 +189,7 @@ xor11 {
};
};
nand: nand@d0000 {
nand_controller: nand-controller@d0000 {
clocks = <&dfx_coredivclk 0>;
};
@ -243,7 +243,7 @@ switch: switch@a8000000 {
ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
pp0: packet-processor@0 {
compatible = "marvell,prestera-98dx3236";
compatible = "marvell,prestera-98dx3236", "marvell,prestera";
reg = <0 0x4000000>;
interrupts = <33>, <34>, <35>;
dfx = <&dfx>;

2
arch/arm/boot/dts/armada-xp-98dx3336.dtsi
View File

@ -35,5 +35,5 @@ resume@20980 {
};
&pp0 {
compatible = "marvell,prestera-98dx3336";
compatible = "marvell,prestera-98dx3336", "marvell,prestera";
};

2
arch/arm/boot/dts/armada-xp-98dx4251.dtsi
View File

@ -49,6 +49,6 @@ sdio_pins: sdio-pins {
};
&pp0 {
compatible = "marvell,prestera-98dx4251";
compatible = "marvell,prestera-98dx4251", "marvell,prestera";
interrupts = <33>, <34>, <35>, <36>;
};

18
arch/arm/boot/dts/armada-xp-db-dxbc2.dts
View File

@ -68,14 +68,18 @@ &uart1 {
status = "okay";
};
&nand {
&nand_controller {
status = "okay";
label = "pxa3xx_nand-0";
num-cs = <1>;
marvell,nand-keep-config;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0";
nand-rb = <0>;
marvell,nand-keep-config;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
};
};
&sdio {

18
arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
View File

@ -67,14 +67,18 @@ &i2c0 {
status = "okay";
};
&nand {
&nand_controller {
status = "okay";
label = "pxa3xx_nand-0";
num-cs = <1>;
marvell,nand-keep-config;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0";
nand-rb = <0>;
marvell,nand-keep-config;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
};
};
&spi0 {

207
arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts Normal file
View File

@ -0,0 +1,207 @@
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "HXT StarDragon 4800 REP2 AST2520";
compatible = "hxt,stardragon4800-rep2-bmc", "aspeed,ast2500";
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory@80000000 {
reg = <0x80000000 0x40000000>;
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>;
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 7>;
};
leds {
compatible = "gpio-leds";
system_fault1 {
label = "System_fault1";
gpios = <&gpio ASPEED_GPIO(I, 3) GPIO_ACTIVE_LOW>;
};
system_fault2 {
label = "System_fault2";
gpios = <&gpio ASPEED_GPIO(I, 2) GPIO_ACTIVE_LOW>;
};
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
};
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2ck_default
&pinctrl_spi2miso_default
&pinctrl_spi2mosi_default
&pinctrl_spi2cs0_default>;
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
current-speed = <115200>;
};
&uart5 {
status = "okay";
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii2_default>;
use-ncsi;
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
tmp421@1e {
compatible = "ti,tmp421";
reg = <0x1e>;
};
tmp421@2a {
compatible = "ti,tmp421";
reg = <0x2a>;
};
tmp421@1c {
compatible = "ti,tmp421";
reg = <0x1c>;
};
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
tmp421@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
nvt210@4c {
compatible = "nvt210";
reg = <0x4c>;
};
eeprom@50 {
compatible = "atmel,24c128";
reg = <0x50>;
pagesize = <128>;
};
};
&i2c7 {
status = "okay";
};
&i2c8 {
status = "okay";
pca9641@70 {
compatible = "nxp,pca9641";
reg = <0x70>;
i2c-arb {
#address-cells = <1>;
#size-cells = <0>;
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
dps650ab@58 {
compatible = "dps650ab";
reg = <0x58>;
};
};
};
};
&i2c9 {
status = "okay";
};
&vuart {
status = "okay";
};
&gfx {
status = "okay";
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
&gpio {
pin_gpio_c7 {
gpio-hog;
gpios = <ASPEED_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "BIOS_SPI_MUX_S";
};
pin_gpio_d1 {
gpio-hog;
gpios = <ASPEED_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PHY2_RESET_N";
};
};

146
arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts Normal file
View File

@ -0,0 +1,146 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2018 Facebook Inc.
// Author: Vijay Khemka <vijaykhemka@fb.com>
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Facebook TiogaPass BMC";
compatible = "facebook,tiogapass-bmc", "aspeed,ast2500";
aliases {
serial0 = &uart1;
serial4 = &uart5;
};
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
#include "openbmc-flash-layout.dtsi"
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "pnor";
};
};
&uart1 {
// Host Console
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&uart5 {
// BMC Console
status = "okay";
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
use-ncsi;
};
&i2c0 {
status = "okay";
//Airmax Conn B, CPU0 PIROM, CPU1 PIROM
};
&i2c1 {
status = "okay";
//X24 Riser
};
&i2c2 {
status = "okay";
// Mezz Management SMBus
};
&i2c3 {
status = "okay";
// SMBus to Board ID EEPROM
};
&i2c4 {
status = "okay";
// BMC Debug Header
};
&i2c5 {
status = "okay";
// CPU Voltage regulators
};
&i2c6 {
status = "okay";
tpm@20 {
compatible = "infineon,slb9645tt";
reg = <0x20>;
};
tmp421@4e {
compatible = "ti,tmp421";
reg = <0x4e>;
};
tmp421@4f {
compatible = "ti,tmp421";
reg = <0x4f>;
};
eeprom@54 {
compatible = "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
};
};
&i2c7 {
status = "okay";
//HSC, AirMax Conn A
};
&i2c8 {
status = "okay";
//Mezz Sensor SMBus
};
&i2c9 {
status = "okay";
//USB Debug Connector
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
fan@1 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
};
};

47
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
View File

@ -7,6 +7,25 @@ / {
model = "Quanta Q71L BMC";
compatible = "quanta,q71l-bmc", "aspeed,ast2400";
aliases {
i2c14 = &i2c_pcie2;
i2c15 = &i2c_pcie3;
i2c16 = &i2c_pcie6;
i2c17 = &i2c_pcie7;
i2c18 = &i2c_pcie1;
i2c19 = &i2c_pcie4;
i2c20 = &i2c_pcie5;
i2c21 = &i2c_pcie8;
i2c22 = &i2c_pcie9;
i2c23 = &i2c_pcie10;
i2c24 = &i2c_ssd1;
i2c25 = &i2c_ssd2;
i2c26 = &i2c_psu4;
i2c27 = &i2c_psu1;
i2c28 = &i2c_psu3;
i2c29 = &i2c_psu2;
};
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
@ -93,6 +112,10 @@ &pinctrl {
&pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
};
&ibt {
status = "okay";
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
@ -299,24 +322,44 @@ i2c_psu4: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
psu@59 {
compatible = "pmbus";
reg = <0x59>;
};
};
i2c_psu1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
psu@58 {
compatible = "pmbus";
reg = <0x58>;
};
};
i2c_psu3: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
psu@58 {
compatible = "pmbus";
reg = <0x58>;
};
};
i2c_psu2: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
psu@59 {
compatible = "pmbus";
reg = <0x59>;
};
};
};
@ -345,6 +388,10 @@ &wdt2 {
status = "okay";
};
&adc {
status = "okay";
};
&pwm_tacho {
status = "okay";

2
arch/arm/boot/dts/aspeed-g4.dtsi
View File

@ -350,7 +350,7 @@ uart4: serial@1e78f000 {
status = "disabled";
};
i2c: i2c@1e78a000 {
i2c: bus@1e78a000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

2
arch/arm/boot/dts/aspeed-g5.dtsi
View File

@ -410,7 +410,7 @@ uart4: serial@1e78f000 {
status = "disabled";
};
i2c: i2c@1e78a000 {
i2c: bus@1e78a000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

4
arch/arm/boot/dts/at91-dvk_su60_somc.dtsi
View File

@ -70,9 +70,9 @@ wm8904: wm8904@1a {
&i2c1 {
status = "okay";
eeprom@87 {
eeprom@57 {
compatible = "giantec,gt24c32a", "atmel,24c32";
reg = <87>;
reg = <0x57>;
pagesize = <32>;
};
};

4
arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi
View File

@ -59,9 +59,9 @@ pinctrl_lcd_ctp_int: lcd_ctp_int {
&i2c1 {
status = "okay";
ft5426@56 {
ft5426@38 {
compatible = "focaltech,ft5426", "edt,edt-ft5406";
reg = <56>;
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_ctp_int>;

103
arch/arm/boot/dts/at91-nattis-2-natte-2.dts
View File

@ -16,46 +16,6 @@ / {
compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
ahb {
apb {
pinctrl@fffff200 {
nattis {
pinctrl_usba_vbus: usba_vbus {
atmel,pins =
<AT91_PIOD 28
AT91_PERIPH_GPIO
AT91_PINCTRL_DEGLITCH>;
};
pinctrl_mmc0_cd: mmc0_cd {
atmel,pins =
<AT91_PIOD 5
AT91_PERIPH_GPIO
AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_lcd_prlud0: lcd_prlud0 {
atmel,pins =
<AT91_PIOA 21
AT91_PERIPH_GPIO
AT91_PINCTRL_OUTPUT_VAL(0)>;
};
pinctrl_lcd_hipow0: lcd_hipow0 {
atmel,pins =
<AT91_PIOA 23
AT91_PERIPH_GPIO
AT91_PINCTRL_OUTPUT_VAL(0)>;
};
};
};
watchdog@fffffe40 {
status = "okay";
};
};
};
gpio-keys {
compatible = "gpio-keys";
@ -103,10 +63,29 @@ panel_bl: backlight {
};
panel: panel {
compatible = "sharp,lq150x1lg11";
compatible = "sharp,lq150x1lg11", "panel-lvds";
backlight = <&panel_bl>;
power-supply = <&panel_reg>;
width-mm = <304>;
height-mm = <228>;
data-mapping = "jeida-18";
panel-timing {
// 1024x768 @ 60Hz (typical)
clock-frequency = <50000000 65000000 80000000>;
hactive = <1024>;
vactive = <768>;
hfront-porch = <48 88 88>;
hback-porch = <96 168 168>;
hsync-len = <32 64 64>;
vsync-len = <3 13 74>;
vfront-porch = <3 13 74>;
vback-porch = <3 12 74>;
};
port {
panel_input: endpoint {
remote-endpoint = <&lvds_encoder_output>;
@ -115,7 +94,10 @@ panel_input: endpoint {
};
lvds-encoder {
compatible = "lvds-encoder";
compatible = "ti,ds90c185", "lvds-encoder";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds_prlud0 &pinctrl_lvds_hipow0>;
ports {
#address-cells = <1>;
@ -159,6 +141,36 @@ simple-audio-card,codec {
};
};
&pinctrl {
nattis {
pinctrl_usba_vbus: usba_vbus {
atmel,pins = <AT91_PIOD 28 AT91_PERIPH_GPIO
AT91_PINCTRL_DEGLITCH>;
};
pinctrl_mmc0_cd: mmc0_cd {
atmel,pins = <AT91_PIOD 5 AT91_PERIPH_GPIO
AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_lvds_prlud0: lvds_prlud0 {
atmel,pins = <AT91_PIOA 21 AT91_PERIPH_GPIO
(AT91_PINCTRL_OUTPUT |
AT91_PINCTRL_OUTPUT_VAL(0))>;
};
pinctrl_lvds_hipow0: lvds_hipow0 {
atmel,pins = <AT91_PIOA 23 AT91_PERIPH_GPIO
(AT91_PINCTRL_OUTPUT |
AT91_PINCTRL_OUTPUT_VAL(0))>;
};
};
};
&watchdog {
status = "okay";
};
&i2c0 {
status = "okay";
@ -195,14 +207,12 @@ &hlcdc {
hlcdc-display-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base
&pinctrl_lcd_rgb565
&pinctrl_lcd_prlud0
&pinctrl_lcd_hipow0>;
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>;
port@0 {
hlcdc_output: endpoint {
remote-endpoint = <&lvds_encoder_input>;
bus-width = <16>;
};
};
};
@ -219,6 +229,7 @@ slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cd-inverted;
};
};

42
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
View File

@ -283,6 +283,13 @@ i2c1: i2c@fc028000 {
status = "okay";
};
adc: adc@fc030000 {
vddana-supply = <&vddana>;
vref-supply = <&advref>;
status = "disabled";
};
pinctrl@fc038000 {
pinctrl_can1_default: can1_default {
@ -549,4 +556,39 @@ blue {
linux,default-trigger = "heartbeat";
};
};
vddin_3v3: fixed-regulator-vddin_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDIN_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
status = "okay";
};
vddana: fixed-regulator-vddana {
compatible = "regulator-fixed";
regulator-name = "VDDANA";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vddin_3v3>;
status = "okay";
};
advref: fixed-regulator-advref {
compatible = "regulator-fixed";
regulator-name = "advref";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vddana>;
status = "okay";
};
};

8
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
View File

@ -92,13 +92,13 @@ bootloader@40000 {
reg = <0x40000 0xc0000>;
};
bootloaderenv@0x100000 {
label = "bootloader env";
bootloaderenvred@0x100000 {
label = "bootloader env redundant";
reg = <0x100000 0x40000>;
};
bootloaderenvred@0x140000 {
label = "bootloader env redundant";
bootloaderenv@0x140000 {
label = "bootloader env";
reg = <0x140000 0x40000>;
};

30
arch/arm/boot/dts/at91-sama5d2_xplained.dts
View File

@ -281,6 +281,12 @@ watchdog@f8048040 {
status = "okay";
};
i2s0: i2s@f8050000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2s0_default>;
status = "disabled"; /* conflict with can0 */
};
can0: can@f8054000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_default>;
@ -424,6 +430,24 @@ pinctrl_i2c1_default: i2c1_default {
bias-disable;
};
pinctrl_i2s0_default: i2s0_default {
pinmux = <PIN_PC1__I2SC0_CK>,
<PIN_PC2__I2SC0_MCK>,
<PIN_PC3__I2SC0_WS>,
<PIN_PC4__I2SC0_DI0>,
<PIN_PC5__I2SC0_DO0>;
bias-disable;
};
pinctrl_i2s1_default: i2s1_default {
pinmux = <PIN_PA15__I2SC1_CK>,
<PIN_PA14__I2SC1_MCK>,
<PIN_PA16__I2SC1_WS>,
<PIN_PA17__I2SC1_DI0>,
<PIN_PA18__I2SC1_DO0>;
bias-disable;
};
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PB9__GPIO>;
bias-pull-up;
@ -546,6 +570,12 @@ classd: classd@fc048000 {
status = "okay";
};
i2s1: i2s@fc04c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2s1_default>;
status = "disabled"; /* conflict with spi0, sdmmc1 */
};
can1: can@fc050000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;

11
arch/arm/boot/dts/at91-sama5d3_xplained.dts
View File

@ -297,12 +297,17 @@ at91bootstrap@0 {
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0x80000>;
reg = <0x40000 0xc0000>;
};
bootloaderenv@c0000 {
bootloaderenvred@100000 {
label = "bootloader env redundant";
reg = <0x100000 0x40000>;
};
bootloaderenv@140000 {
label = "bootloader env";
reg = <0xc0000 0xc0000>;
reg = <0x140000 0x40000>;
};
dtb@180000 {

13
arch/arm/boot/dts/at91-sama5d4_xplained.dts
View File

@ -232,12 +232,17 @@ at91bootstrap@0 {
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0x80000>;
reg = <0x40000 0xc0000>;
};
bootloaderenv@c0000 {
bootloaderenvred@100000 {
label = "bootloader env redundant";
reg = <0x100000 0x40000>;
};
bootloaderenv@140000 {
label = "bootloader env";
reg = <0xc0000 0xc0000>;
reg = <0x140000 0x40000>;
};
dtb@180000 {
@ -252,7 +257,7 @@ kernel@200000 {
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
reg = <0x800000 0x1f800000>;
};
};
};

32
arch/arm/boot/dts/at91-tse850-3.dts
View File

@ -16,25 +16,6 @@ / {
compatible = "axentia,tse850v3", "axentia,linea",
"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
ahb {
apb {
pinctrl@fffff200 {
tse850 {
pinctrl_usba_vbus: usba-vbus {
atmel,pins =
<AT91_PIOC 31
AT91_PERIPH_GPIO
AT91_PINCTRL_DEGLITCH>;
};
};
};
watchdog@fffffe40 {
status = "okay";
};
};
};
sck: oscillator {
compatible = "fixed-clock";
@ -253,6 +234,19 @@ eeprom@50 {
};
};
&pinctrl {
tse850 {
pinctrl_usba_vbus: usba-vbus {
atmel,pins = <AT91_PIOC 31 AT91_PERIPH_GPIO
AT91_PINCTRL_DEGLITCH>;
};
};
};
&watchdog {
status = "okay";
};
&usart0 {
status = "okay";

2
arch/arm/boot/dts/at91-vinco.dts
View File

@ -128,7 +128,7 @@ ethernet-phy@1 {
i2c2: i2c@f8024000 {
status = "okay";
rtc1: rtc@64 {
rtc1: rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};

2
arch/arm/boot/dts/at91sam9260ek.dts
View File

@ -127,7 +127,7 @@ macb0: ethernet@fffc4000 {
spi0: spi@fffc8000 {
cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
mtd_dataflash@0 {
mtd_dataflash@1 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <50000000>;
reg = <1>;

2
arch/arm/boot/dts/at91sam9261ek.dts
View File

@ -160,7 +160,7 @@ mtd_dataflash@0 {
spi-max-frequency = <15000000>;
};
tsc2046@0 {
tsc2046@2 {
reg = <2>;
compatible = "ti,ads7843";
interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>;

2
arch/arm/boot/dts/at91sam9g20ek_common.dtsi
View File

@ -109,7 +109,7 @@ ssc0: ssc@fffbc000 {
spi0: spi@fffc8000 {
cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
mtd_dataflash@0 {
mtd_dataflash@1 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <50000000>;
reg = <1>;

2
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@ -570,7 +570,7 @@ pinctrl_usart0_cts: usart0_cts-0 {
};
};
uart1 {
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE

18
arch/arm/boot/dts/at91sam9x5cm.dtsi
View File

@ -85,12 +85,22 @@ at91bootstrap@0 {
uboot@40000 {
label = "u-boot";
reg = <0x40000 0x80000>;
reg = <0x40000 0xc0000>;
};
ubootenv@c0000 {
ubootenvred@100000 {
label = "U-Boot Env Redundant";
reg = <0x100000 0x40000>;
};
ubootenv@140000 {
label = "U-Boot Env";
reg = <0xc0000 0x140000>;
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
@ -100,7 +110,7 @@ kernel@200000 {
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x1f800000>;
reg = <0x800000 0x0f800000>;
};
};
};

2
arch/arm/boot/dts/bcm-hr2.dtsi
View File

@ -216,7 +216,7 @@ rng: rng@33000 {
reg = <0x33000 0x14>;
};
qspi: qspi@27200 {
qspi: spi@27200 {
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
reg = <0x027200 0x184>,
<0x027000 0x124>,

33
arch/arm/boot/dts/bcm-nsp.dtsi
View File

@ -273,7 +273,7 @@ nand: nand@26000 {
brcm,nand-has-wp;
};
qspi: qspi@27200 {
qspi: spi@27200 {
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
reg = <0x027200 0x184>,
<0x027000 0x124>,
@ -377,7 +377,36 @@ ccbtimer1: timer@35000 {
srab: srab@36000 {
compatible = "brcm,nsp-srab";
reg = <0x36000 0x1000>;
reg = <0x36000 0x1000>,
<0x3f308 0x8>,
<0x3f410 0xc>;
reg-names = "srab", "mux_config", "sgmii";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "link_state_p0",
"link_state_p1",
"link_state_p2",
"link_state_p3",
"link_state_p4",
"link_state_p5",
"link_state_p7",
"link_state_p8",
"phy",
"ts",
"imp_sleep_timer_p5",
"imp_sleep_timer_p7",
"imp_sleep_timer_p8";
#address-cells = <1>;
#size-cells = <0>;

87
arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts Normal file
View File

@ -0,0 +1,87 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2837-rpi-cm3.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
compatible = "raspberrypi,3-compute-module", "brcm,bcm2837";
model = "Raspberry Pi Compute Module 3 IO board V3.0";
};
&gpio {
/*
* This is based on the official GPU firmware DT blob.
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "GPIO0",
"GPIO1",
"GPIO2",
"GPIO3",
"GPIO4",
"GPIO5",
"GPIO6",
"GPIO7",
"GPIO8",
"GPIO9",
"GPIO10",
"GPIO11",
"GPIO12",
"GPIO13",
"GPIO14",
"GPIO15",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"GPIO28",
"GPIO29",
"GPIO30",
"GPIO31",
"GPIO32",
"GPIO33",
"GPIO34",
"GPIO35",
"GPIO36",
"GPIO37",
"GPIO38",
"GPIO39",
"GPIO40",
"GPIO41",
"GPIO42",
"GPIO43",
"GPIO44",
"GPIO45",
"GPIO46",
"GPIO47",
/* Used by eMMC */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0>;
};
&hdmi {
hpd-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
status = "okay";
};

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