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Device tree related changes to the omap iommu driver as that 

is finally getting updated. Also few trivial board related
 .dts updates to add more devices.
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Merge tag 'omap-for-v3.15/dt-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt

Pull "omap device tree changes for v3.15, part 3" from Tony Lindgren:

Device tree related changes to the omap iommu driver as that
is finally getting updated. Also few trivial board related
.dts updates to add more devices.

* tag 'omap-for-v3.15/dt-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: Add MMC2/SDIO/WLAN support for cm-t3530
  ARM: dts: am335x-evmsk: enable DMA controller for USB
  ARM: dts: OMAP5: Add IOMMU nodes
  ARM: dts: OMAP4: Add IOMMU nodes
  ARM: dts: OMAP3: Add IVA IOMMU node
  ARM: dts: OMAP3: Update ISP IOMMU node
  ARM: OMAP2+: extend iommu pdata-quirks to OMAP5
  ARM: OMAP5: hwmod data: add mmu data for ipu & dsp
  ARM: OMAP2+: use pdata quirks for iommu reset lines
  ARM: OMAP2+: change the ISP device archdata MMU name for DT
  ARM: OMAP3: fix iva mmu programming issues
  ARM: OMAP3: remove deprecated CONFIG_OMAP_IOMMU_IVA2

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-03-17 15:11:10 +01:00
parent a38f8913da e1902bbe44
commit 937b5991ca
11 changed files with 197 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/am335x-evmsk.dts
View File

@ -378,6 +378,10 @@ usb@47401800 {
status = "okay";
dr_mode = "host";
};
dma-controller@07402000 {
status = "okay";
};
};
&epwmss2 {

36
arch/arm/boot/dts/omap3-cm-t3530.dts
View File

@ -9,4 +9,40 @@
/ {
model = "CompuLab CM-T3530";
compatible = "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
/* Regulator to trigger the reset signal of the Wifi module */
mmc2_sdio_reset: regulator-mmc2-sdio-reset {
compatible = "regulator-fixed";
regulator-name = "regulator-mmc2-sdio-reset";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&omap3_pmx_core {
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */
OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */
OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */
OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */
>;
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&mmc2_sdio_reset>;
non-removable;
bus-width = <4>;
cap-power-off-card;
};

15
arch/arm/boot/dts/omap3.dtsi
View File

@ -416,10 +416,19 @@ mmc3: mmc@480ad000 {
};
mmu_isp: mmu@480bd400 {
compatible = "ti,omap3-mmu-isp";
ti,hwmods = "mmu_isp";
compatible = "ti,omap2-iommu";
reg = <0x480bd400 0x80>;
interrupts = <8>;
interrupts = <24>;
ti,hwmods = "mmu_isp";
ti,#tlb-entries = <8>;
};
mmu_iva: mmu@5d000000 {
compatible = "ti,omap2-iommu";
reg = <0x5d000000 0x80>;
interrupts = <28>;
ti,hwmods = "mmu_iva";
status = "disabled";
};
wdt2: wdt@48314000 {

15
arch/arm/boot/dts/omap4.dtsi
View File

@ -467,6 +467,21 @@ mmc5: mmc@480d5000 {
dma-names = "tx", "rx";
};
mmu_dsp: mmu@4a066000 {
compatible = "ti,omap4-iommu";
reg = <0x4a066000 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_dsp";
};
mmu_ipu: mmu@55082000 {
compatible = "ti,omap4-iommu";
reg = <0x55082000 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_ipu";
ti,iommu-bus-err-back;
};
wdt2: wdt@4a314000 {
compatible = "ti,omap4-wdt", "ti,omap3-wdt";
reg = <0x4a314000 0x80>;

15
arch/arm/boot/dts/omap5.dtsi
View File

@ -520,6 +520,21 @@ mmc5: mmc@480d5000 {
dma-names = "tx", "rx";
};
mmu_dsp: mmu@4a066000 {
compatible = "ti,omap4-iommu";
reg = <0x4a066000 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_dsp";
};
mmu_ipu: mmu@55082000 {
compatible = "ti,omap4-iommu";
reg = <0x55082000 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_ipu";
ti,iommu-bus-err-back;
};
keypad: keypad@4ae1c000 {
compatible = "ti,omap4-keypad";
reg = <0x4ae1c000 0x400>;

2
arch/arm/mach-omap2/clockdomains3xxx_data.c
View File

@ -247,7 +247,7 @@ static struct clockdomain neon_clkdm = {
static struct clockdomain iva2_clkdm = {
.name = "iva2_clkdm",
.pwrdm = { .name = "iva2_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.flags = CLKDM_CAN_SWSUP,
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
.wkdep_srcs = iva2_wkdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,

3
arch/arm/mach-omap2/devices.c
View File

@ -229,6 +229,9 @@ static struct omap_iommu_arch_data omap3_isp_iommu = {
int omap3_init_camera(struct isp_platform_data *pdata)
{
if (of_have_populated_dt())
omap3_isp_iommu.name = "480bd400.mmu";
omap3isp_device.dev.platform_data = pdata;
omap3isp_device.dev.archdata.iommu = &omap3_isp_iommu;

12
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -3029,8 +3029,6 @@ static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
#ifdef CONFIG_OMAP_IOMMU_IVA2
/* mmu iva */
static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
@ -3070,20 +3068,22 @@ static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
.name = "mmu_iva",
.class = &omap3xxx_mmu_hwmod_class,
.mpu_irqs = omap3xxx_mmu_iva_irqs,
.clkdm_name = "iva2_clkdm",
.rst_lines = omap3xxx_mmu_iva_resets,
.rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
.main_clk = "iva2_ck",
.prcm = {
.omap2 = {
.module_offs = OMAP3430_IVA2_MOD,
.module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
},
},
.dev_attr = &mmu_iva_dev_attr,
.flags = HWMOD_NO_IDLEST,
};
#endif
/* l4_per -> gpio4 */
static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
{
@ -3855,9 +3855,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__hdq1w,
&omap3xxx_sad2d__l3,
&omap3xxx_l4_core__mmu_isp,
#ifdef CONFIG_OMAP_IOMMU_IVA2
&omap3xxx_l3_main__mmu_iva,
#endif
&omap34xx_l4_core__ssi,
NULL
};
@ -3881,9 +3879,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__hdq1w,
&omap3xxx_sad2d__l3,
&omap3xxx_l4_core__mmu_isp,
#ifdef CONFIG_OMAP_IOMMU_IVA2
&omap3xxx_l3_main__mmu_iva,
#endif
NULL
};

83
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
View File

@ -1121,6 +1121,71 @@ static struct omap_hwmod omap54xx_mmc5_hwmod = {
},
};
/*
* 'mmu' class
* The memory management unit performs virtual to physical address translation
* for its requestors.
*/
static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
.name = "mmu",
.sysc = &omap54xx_mmu_sysc,
};
static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
{ .name = "mmu_cache", .rst_shift = 1 },
};
static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
.name = "mmu_dsp",
.class = &omap54xx_mmu_hwmod_class,
.clkdm_name = "dsp_clkdm",
.rst_lines = omap54xx_mmu_dsp_resets,
.rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
.main_clk = "dpll_iva_h11x2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
.rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
.context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/* mmu ipu */
static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
{ .name = "mmu_cache", .rst_shift = 2 },
};
static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
.name = "mmu_ipu",
.class = &omap54xx_mmu_hwmod_class,
.clkdm_name = "ipu_clkdm",
.rst_lines = omap54xx_mmu_ipu_resets,
.rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
.main_clk = "dpll_core_h22x2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
.rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
.context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'mpu' class
* mpu sub-system
@ -1763,6 +1828,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> mmu_dsp */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
.master = &omap54xx_l4_cfg_hwmod,
.slave = &omap54xx_mmu_dsp_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* mpu -> l3_main_1 */
static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
.master = &omap54xx_mpu_hwmod,
@ -1787,6 +1860,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> mmu_ipu */
static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
.master = &omap54xx_l3_main_2_hwmod,
.slave = &omap54xx_mmu_ipu_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
.master = &omap54xx_l3_main_1_hwmod,
@ -2345,6 +2426,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_l4_wkup__counter_32k,
&omap54xx_l4_cfg__dma_system,
&omap54xx_l4_abe__dmic,
&omap54xx_l4_cfg__mmu_dsp,
&omap54xx_mpu__emif1,
&omap54xx_mpu__emif2,
&omap54xx_l4_wkup__gpio1,
@ -2360,6 +2442,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_l4_per__i2c3,
&omap54xx_l4_per__i2c4,
&omap54xx_l4_per__i2c5,
&omap54xx_l3_main_2__mmu_ipu,
&omap54xx_l4_wkup__kbd,
&omap54xx_l4_cfg__mailbox,
&omap54xx_l4_abe__mcbsp1,

24
arch/arm/mach-omap2/pdata-quirks.c
View File

@ -16,12 +16,14 @@
#include <linux/wl12xx.h>
#include <linux/platform_data/pinctrl-single.h>
#include <linux/platform_data/iommu-omap.h>
#include "am35xx.h"
#include "common.h"
#include "common-board-devices.h"
#include "dss-common.h"
#include "control.h"
#include "omap_device.h"
struct pdata_init {
const char *compatible;
@ -78,6 +80,12 @@ static void __init hsmmc2_internal_input_clk(void)
omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1);
}
static struct iommu_platform_data omap3_iommu_pdata = {
.reset_name = "mmu",
.assert_reset = omap_device_assert_hardreset,
.deassert_reset = omap_device_deassert_hardreset,
};
static int omap3_sbc_t3730_twl_callback(struct device *dev,
unsigned gpio,
unsigned ngpio)
@ -233,6 +241,14 @@ static void __init omap4_panda_legacy_init(void)
}
#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
static struct iommu_platform_data omap4_iommu_pdata = {
.reset_name = "mmu_cache",
.assert_reset = omap_device_assert_hardreset,
.deassert_reset = omap_device_deassert_hardreset,
};
#endif
#ifdef CONFIG_SOC_AM33XX
static void __init am335x_evmsk_legacy_init(void)
{
@ -292,6 +308,8 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
#ifdef CONFIG_ARCH_OMAP3
OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata),
OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata),
OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu",
&omap3_iommu_pdata),
/* Only on am3517 */
OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL),
OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0",
@ -300,6 +318,12 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
#ifdef CONFIG_ARCH_OMAP4
OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata),
OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata),
#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu",
&omap4_iommu_pdata),
OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu",
&omap4_iommu_pdata),
#endif
{ /* sentinel */ },
};

3
arch/arm/plat-omap/Kconfig
View File

@ -86,9 +86,6 @@ config OMAP_MUX_WARNINGS
to change the pin multiplexing setup. When there are no warnings
printed, it's safe to deselect OMAP_MUX for your product.
config OMAP_IOMMU_IVA2
bool
config OMAP_MPU_TIMER
bool "Use mpu timer"
depends on ARCH_OMAP1