mirror of https://gitee.com/openkylin/linux.git
staging: r8188eu: Fix smatch warning in hal/HalPhyRf_8188e.c
Smatch reported the following warning: drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c:1876 PHY_APCalibrate_8188E() info: ignoring unreachable code. Once the unreachable code was removed, the entire routine was removed, which led to the warning that phy_APCalibrate_8188E() was not used. It was also deleted along with some unused defines. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Larry Finger
Greg Kroah-Hartman
parent
473803650d
commit
937ebbdec5
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@ -1276,407 +1276,6 @@ static void phy_LCCalibrate_8188E(struct adapter *adapt, bool is2t)
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}
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}
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/* Analog Pre-distortion calibration */
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#define APK_BB_REG_NUM 8
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#define APK_CURVE_REG_NUM 4
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#define PATH_NUM 2
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static void phy_APCalibrate_8188E(struct adapter *adapt, s8 delta, bool is2t)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt);
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struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
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u32 regD[PATH_NUM];
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u32 tmpreg, index, offset, apkbound;
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u8 path, i, pathbound = PATH_NUM;
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u32 BB_backup[APK_BB_REG_NUM];
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u32 BB_REG[APK_BB_REG_NUM] = {
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rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
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rFPGA0_RFMOD, rOFDM0_TRMuxPar,
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rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW,
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rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE };
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u32 BB_AP_MODE[APK_BB_REG_NUM] = {
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0x00000020, 0x00a05430, 0x02040000,
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0x000800e4, 0x00204000 };
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u32 BB_normal_AP_MODE[APK_BB_REG_NUM] = {
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0x00000020, 0x00a05430, 0x02040000,
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0x000800e4, 0x22204000 };
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u32 AFE_backup[IQK_ADDA_REG_NUM];
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u32 AFE_REG[IQK_ADDA_REG_NUM] = {
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rFPGA0_XCD_SwitchControl, rBlue_Tooth,
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rRx_Wait_CCA, rTx_CCK_RFON,
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rTx_CCK_BBON, rTx_OFDM_RFON,
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rTx_OFDM_BBON, rTx_To_Rx,
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rTx_To_Tx, rRx_CCK,
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rRx_OFDM, rRx_Wait_RIFS,
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rRx_TO_Rx, rStandby,
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rSleep, rPMPD_ANAEN };
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u32 MAC_backup[IQK_MAC_REG_NUM];
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u32 MAC_REG[IQK_MAC_REG_NUM] = {
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REG_TXPAUSE, REG_BCN_CTRL,
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REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
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u32 APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
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{0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
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{0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
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};
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u32 APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
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{0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, /* path settings equal to path b settings */
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{0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
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};
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u32 APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
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{0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
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{0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
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};
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u32 APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
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{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, /* path settings equal to path b settings */
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{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
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};
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u32 AFE_on_off[PATH_NUM] = {
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0x04db25a4, 0x0b1b25a4}; /* path A on path B off / path A off path B on */
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u32 APK_offset[PATH_NUM] = {
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rConfig_AntA, rConfig_AntB};
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u32 APK_normal_offset[PATH_NUM] = {
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rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};
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u32 APK_value[PATH_NUM] = {
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0x92fc0000, 0x12fc0000};
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u32 APK_normal_value[PATH_NUM] = {
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0x92680000, 0x12680000};
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s8 APK_delta_mapping[APK_BB_REG_NUM][13] = {
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{-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
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{-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
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{-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
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{-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
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{-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
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};
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u32 APK_normal_setting_value_1[13] = {
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0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
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0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
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0x12680000, 0x00880000, 0x00880000
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};
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u32 APK_normal_setting_value_2[16] = {
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0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
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0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
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0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
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0x00050006
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};
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u32 APK_result[PATH_NUM][APK_BB_REG_NUM]; /* val_1_1a, val_1_2a, val_2a, val_3a, val_4a */
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s32 BB_offset, delta_V, delta_offset;
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if (*(dm_odm->mp_mode) == 1) {
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struct mpt_context *pMptCtx = &(adapt->mppriv.MptCtx);
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pMptCtx->APK_bound[0] = 45;
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pMptCtx->APK_bound[1] = 52;
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}
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta));
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2t ? "2T2R" : "1T1R")));
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if (!is2t)
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pathbound = 1;
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/* 2 FOR NORMAL CHIP SETTINGS */
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/* Temporarily do not allow normal driver to do the following settings
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* because these offset and value will cause RF internal PA to be
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* unpredictably disabled by HW, such that RF Tx signal will disappear
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* after disable/enable card many times on 88CU. RF SD and DD have not
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* find the root cause, so we remove these actions temporarily.
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*/
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if (*(dm_odm->mp_mode) != 1)
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return;
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/* settings adjust for normal chip */
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for (index = 0; index < PATH_NUM; index++) {
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APK_offset[index] = APK_normal_offset[index];
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APK_value[index] = APK_normal_value[index];
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AFE_on_off[index] = 0x6fdb25a4;
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}
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for (index = 0; index < APK_BB_REG_NUM; index++) {
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for (path = 0; path < pathbound; path++) {
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APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];
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APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];
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}
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BB_AP_MODE[index] = BB_normal_AP_MODE[index];
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}
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apkbound = 6;
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/* save BB default value */
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for (index = 0; index < APK_BB_REG_NUM; index++) {
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if (index == 0) /* skip */
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continue;
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BB_backup[index] = ODM_GetBBReg(dm_odm, BB_REG[index], bMaskDWord);
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}
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/* save MAC default value */
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_PHY_SaveMACRegisters(adapt, MAC_REG, MAC_backup);
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/* save AFE default value */
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_PHY_SaveADDARegisters(adapt, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
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for (path = 0; path < pathbound; path++) {
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if (path == RF_PATH_A) {
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/* path A APK */
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/* load APK setting */
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/* path-A */
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offset = rPdp_AntA;
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for (index = 0; index < 11; index++) {
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ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
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("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",
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offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));
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offset += 0x04;
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}
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ODM_SetBBReg(dm_odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
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offset = rConfig_AntA;
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for (; index < 13; index++) {
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ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
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("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",
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offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));
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offset += 0x04;
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}
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/* page-B1 */
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ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
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/* path A */
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offset = rPdp_AntA;
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for (index = 0; index < 16; index++) {
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ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
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("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",
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offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));
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offset += 0x04;
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}
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ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
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} else if (path == RF_PATH_B) {
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/* path B APK */
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/* load APK setting */
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/* path-B */
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offset = rPdp_AntB;
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for (index = 0; index < 10; index++) {
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ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
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("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",
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offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));
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offset += 0x04;
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}
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ODM_SetBBReg(dm_odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);
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PHY_SetBBReg(adapt, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
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offset = rConfig_AntA;
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index = 11;
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for (; index < 13; index++) { /* offset 0xb68, 0xb6c */
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ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
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("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",
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offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));
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offset += 0x04;
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}
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/* page-B1 */
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ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
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/* path B */
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offset = 0xb60;
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for (index = 0; index < 16; index++) {
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ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
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("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",
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offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));
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offset += 0x04;
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}
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ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0);
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}
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/* save RF default value */
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regD[path] = PHY_QueryRFReg(adapt, path, RF_TXBIAS_A, bMaskDWord);
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/* Path A AFE all on, path B AFE All off or vise versa */
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for (index = 0; index < IQK_ADDA_REG_NUM; index++)
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ODM_SetBBReg(dm_odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]);
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
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("phy_APCalibrate_8188E() offset 0xe70 %x\n",
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ODM_GetBBReg(dm_odm, rRx_Wait_CCA, bMaskDWord)));
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/* BB to AP mode */
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if (path == 0) {
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for (index = 0; index < APK_BB_REG_NUM; index++) {
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if (index == 0) /* skip */
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continue;
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else if (index < 5)
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ODM_SetBBReg(dm_odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);
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else if (BB_REG[index] == 0x870)
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ODM_SetBBReg(dm_odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
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else
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ODM_SetBBReg(dm_odm, BB_REG[index], BIT10, 0x0);
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}
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ODM_SetBBReg(dm_odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
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ODM_SetBBReg(dm_odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
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} else {
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/* path B */
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ODM_SetBBReg(dm_odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
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ODM_SetBBReg(dm_odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
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}
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
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("phy_APCalibrate_8188E() offset 0x800 %x\n",
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ODM_GetBBReg(dm_odm, 0x800, bMaskDWord)));
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/* MAC settings */
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_PHY_MACSettingCalibration(adapt, MAC_REG, MAC_backup);
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if (path == RF_PATH_A) {
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/* Path B to standby mode */
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ODM_SetRFReg(dm_odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
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} else {
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/* Path A to standby mode */
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ODM_SetRFReg(dm_odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000);
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ODM_SetRFReg(dm_odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
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ODM_SetRFReg(dm_odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103);
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}
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delta_offset = ((delta+14)/2);
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if (delta_offset < 0)
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delta_offset = 0;
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else if (delta_offset > 12)
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delta_offset = 12;
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/* AP calibration */
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for (index = 0; index < APK_BB_REG_NUM; index++) {
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if (index != 1) /* only DO PA11+PAD01001, AP RF setting */
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continue;
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tmpreg = APK_RF_init_value[path][index];
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if (!dm_odm->RFCalibrateInfo.bAPKThermalMeterIgnore) {
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BB_offset = (tmpreg & 0xF0000) >> 16;
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if (!(tmpreg & BIT15)) /* sign bit 0 */
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BB_offset = -BB_offset;
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delta_V = APK_delta_mapping[index][delta_offset];
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BB_offset += delta_V;
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
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("phy_APCalibrate_8188E() APK index %d tmpreg 0x%x delta_V %d delta_offset %d\n",
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index, tmpreg, delta_V, delta_offset));
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if (BB_offset < 0) {
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tmpreg = tmpreg & (~BIT15);
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BB_offset = -BB_offset;
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} else {
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tmpreg = tmpreg | BIT15;
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}
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tmpreg = (tmpreg & 0xFFF0FFFF) | (BB_offset << 16);
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}
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ODM_SetRFReg(dm_odm, path, RF_IPA_A, bMaskDWord, 0x8992e);
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(adapt, path, RF_IPA_A, bMaskDWord)));
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ODM_SetRFReg(dm_odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(adapt, path, RF_AC, bMaskDWord)));
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ODM_SetRFReg(dm_odm, path, RF_TXBIAS_A, bMaskDWord, tmpreg);
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(adapt, path, RF_TXBIAS_A, bMaskDWord)));
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/* PA11+PAD01111, one shot */
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i = 0;
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do {
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ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x80000000);
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ODM_SetBBReg(dm_odm, APK_offset[path], bMaskDWord, APK_value[0]);
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(dm_odm, APK_offset[path], bMaskDWord)));
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ODM_delay_ms(3);
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ODM_SetBBReg(dm_odm, APK_offset[path], bMaskDWord, APK_value[1]);
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ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(dm_odm, APK_offset[path], bMaskDWord)));
|
||||
|
||||
ODM_delay_ms(20);
|
||||
ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
|
||||
|
||||
if (path == RF_PATH_A)
|
||||
tmpreg = ODM_GetBBReg(dm_odm, rAPK, 0x03E00000);
|
||||
else
|
||||
tmpreg = ODM_GetBBReg(dm_odm, rAPK, 0xF8000000);
|
||||
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpreg));
|
||||
|
||||
i++;
|
||||
} while (tmpreg > apkbound && i < 4);
|
||||
|
||||
APK_result[path][index] = tmpreg;
|
||||
}
|
||||
}
|
||||
|
||||
/* reload MAC default value */
|
||||
_PHY_ReloadMACRegisters(adapt, MAC_REG, MAC_backup);
|
||||
|
||||
/* reload BB default value */
|
||||
for (index = 0; index < APK_BB_REG_NUM; index++) {
|
||||
if (index == 0) /* skip */
|
||||
continue;
|
||||
ODM_SetBBReg(dm_odm, BB_REG[index], bMaskDWord, BB_backup[index]);
|
||||
}
|
||||
|
||||
/* reload AFE default value */
|
||||
reload_adda_reg(adapt, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
|
||||
/* reload RF path default value */
|
||||
for (path = 0; path < pathbound; path++) {
|
||||
ODM_SetRFReg(dm_odm, path, 0xd, bMaskDWord, regD[path]);
|
||||
if (path == RF_PATH_B) {
|
||||
ODM_SetRFReg(dm_odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
|
||||
ODM_SetRFReg(dm_odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);
|
||||
}
|
||||
|
||||
/* note no index == 0 */
|
||||
if (APK_result[path][1] > 6)
|
||||
APK_result[path][1] = 6;
|
||||
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n"));
|
||||
|
||||
for (path = 0; path < pathbound; path++) {
|
||||
ODM_SetRFReg(dm_odm, path, 0x3, bMaskDWord,
|
||||
((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
|
||||
if (path == RF_PATH_A)
|
||||
ODM_SetRFReg(dm_odm, path, 0x4, bMaskDWord,
|
||||
((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));
|
||||
else
|
||||
ODM_SetRFReg(dm_odm, path, 0x4, bMaskDWord,
|
||||
((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));
|
||||
ODM_SetRFReg(dm_odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord,
|
||||
((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));
|
||||
}
|
||||
|
||||
dm_odm->RFCalibrateInfo.bAPKdone = true;
|
||||
|
||||
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n"));
|
||||
}
|
||||
|
||||
#define DP_BB_REG_NUM 7
|
||||
#define DP_RF_REG_NUM 1
|
||||
#define DP_RETRY_LIMIT 10
|
||||
#define DP_PATH_NUM 2
|
||||
#define DP_DPK_NUM 3
|
||||
#define DP_DPK_VALUE_NUM 2
|
||||
|
||||
void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt);
|
||||
|
|
@ -1867,28 +1466,6 @@ void PHY_LCCalibrate_8188E(struct adapter *adapt)
|
|||
("LCK:Finish!!!interface %d\n", dm_odm->InterfaceIndex));
|
||||
}
|
||||
|
||||
void PHY_APCalibrate_8188E(struct adapter *adapt, s8 delta)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt);
|
||||
struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
|
||||
|
||||
return;
|
||||
if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION))
|
||||
return;
|
||||
|
||||
#if FOR_BRAZIL_PRETEST != 1
|
||||
if (dm_odm->RFCalibrateInfo.bAPKdone)
|
||||
#endif
|
||||
return;
|
||||
|
||||
if (dm_odm->RFType == ODM_2T2R) {
|
||||
phy_APCalibrate_8188E(adapt, delta, true);
|
||||
} else {
|
||||
/* For 88C 1T1R */
|
||||
phy_APCalibrate_8188E(adapt, delta, false);
|
||||
}
|
||||
}
|
||||
|
||||
static void phy_setrfpathswitch_8188e(struct adapter *adapt, bool main, bool is2t)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt);
|
||||
|
|
|
|||
|
|
@ -45,8 +45,6 @@ void PHY_IQCalibrate_8188E(struct adapter *Adapter, bool ReCovery);
|
|||
void PHY_LCCalibrate_8188E(struct adapter *pAdapter);
|
||||
|
||||
/* AP calibrate */
|
||||
void PHY_APCalibrate_8188E(struct adapter *pAdapter, s8 delta);
|
||||
|
||||
void PHY_DigitalPredistortion_8188E(struct adapter *pAdapter);
|
||||
|
||||
void _PHY_SaveADDARegisters(struct adapter *pAdapter, u32 *ADDAReg,
|
||||
|
|
|
|||
Loading…
Reference in New Issue