mirror of https://gitee.com/openkylin/linux.git
Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c fixes from Wolfram Sang: "Two bugfixes, one v4.16 regression fix, and two documentation fixes" * 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: i2c: designware: Consider SCL GPIO optional i2c: busses: i2c-sirf: Fix spelling: "formular" -> "formula". i2c: bcm2835: Set up the rising/falling edge delays i2c: i801: Add missing documentation entries for Braswell and Kaby Lake i2c: designware: must wait for enable
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commit
938e1426e2
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@ -28,8 +28,10 @@ Supported adapters:
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* Intel Wildcat Point (PCH)
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* Intel Wildcat Point-LP (PCH)
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* Intel BayTrail (SOC)
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* Intel Braswell (SOC)
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* Intel Sunrise Point-H (PCH)
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* Intel Sunrise Point-LP (PCH)
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* Intel Kaby Lake-H (PCH)
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* Intel DNV (SOC)
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* Intel Broxton (SOC)
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* Intel Lewisburg (PCH)
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@ -123,8 +123,10 @@ config I2C_I801
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Wildcat Point (PCH)
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Wildcat Point-LP (PCH)
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BayTrail (SOC)
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Braswell (SOC)
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Sunrise Point-H (PCH)
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Sunrise Point-LP (PCH)
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Kaby Lake-H (PCH)
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DNV (SOC)
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Broxton (SOC)
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Lewisburg (PCH)
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@ -50,6 +50,9 @@
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#define BCM2835_I2C_S_CLKT BIT(9)
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#define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */
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#define BCM2835_I2C_FEDL_SHIFT 16
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#define BCM2835_I2C_REDL_SHIFT 0
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#define BCM2835_I2C_CDIV_MIN 0x0002
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#define BCM2835_I2C_CDIV_MAX 0xFFFE
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@ -81,7 +84,7 @@ static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
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static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
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{
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u32 divider;
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u32 divider, redl, fedl;
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divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk),
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i2c_dev->bus_clk_rate);
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@ -100,6 +103,22 @@ static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
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bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider);
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/*
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* Number of core clocks to wait after falling edge before
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* outputting the next data bit. Note that both FEDL and REDL
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* can't be greater than CDIV/2.
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*/
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fedl = max(divider / 16, 1u);
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/*
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* Number of core clocks to wait after rising edge before
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* sampling the next incoming data bit.
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*/
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redl = max(divider / 4, 1u);
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bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DEL,
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(fedl << BCM2835_I2C_FEDL_SHIFT) |
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(redl << BCM2835_I2C_REDL_SHIFT));
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return 0;
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}
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@ -209,7 +209,7 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
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i2c_dw_disable_int(dev);
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/* Enable the adapter */
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__i2c_dw_enable(dev, true);
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__i2c_dw_enable_and_wait(dev, true);
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/* Clear and enable interrupts */
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dw_readl(dev, DW_IC_CLR_INTR);
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@ -644,7 +644,7 @@ static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
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gpio = devm_gpiod_get(dev->dev, "scl", GPIOD_OUT_HIGH);
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if (IS_ERR(gpio)) {
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r = PTR_ERR(gpio);
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if (r == -ENOENT)
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if (r == -ENOENT || r == -ENOSYS)
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return 0;
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return r;
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}
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@ -58,6 +58,7 @@
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* Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
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* Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
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* BayTrail (SOC) 0x0f12 32 hard yes yes yes
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* Braswell (SOC) 0x2292 32 hard yes yes yes
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* Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
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* Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
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* DNV (SOC) 0x19df 32 hard yes yes yes
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@ -341,7 +341,7 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, adap);
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init_completion(&siic->done);
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/* Controller Initalisation */
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/* Controller initialisation */
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writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
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while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
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@ -369,7 +369,7 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev)
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* but they start to affect the speed when clock is set to faster
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* frequencies.
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* Through the actual tests, use the different user_div value(which
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* in the divider formular 'Fio / (Fi2c * user_div)') to adapt
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* in the divider formula 'Fio / (Fi2c * user_div)') to adapt
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* the different ranges of i2c bus clock frequency, to make the SCL
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* more accurate.
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*/
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