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arm64: tegra: Fix base address for SOR1 on Tegra194 

The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg property lists a
wrong value, likely because it was copy-and-pasted from SOR0 but not
correctly updated.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2019-07-26 12:16:18 +02:00
parent 1aaa769867
commit 939e7430de
1 changed files with 1 additions and 1 deletions
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2
arch/arm64/boot/dts/nvidia/tegra194.dtsi
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@ -1078,7 +1078,7 @@ sor0: sor@15b00000 {
sor1: sor@15b40000 {
compatible = "nvidia,tegra194-sor";
reg = <0x155c0000 0x40000>;
reg = <0x15b40000 0x40000>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
<&bpmp TEGRA194_CLK_SOR1_OUT>,