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dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator 

Add new properties to configure the DFLL PWM regulator support.

Cc: devicetree@vger.kernel.org
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Peter De Schrijver 2019-01-04 11:06:43 +08:00 committed by Thierry Reding
parent 22daf91049
commit 93caec0042
1 changed files with 77 additions and 2 deletions
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79
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
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@ -8,7 +8,6 @@ the fast CPU cluster. It consists of a free-running voltage controlled
oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
control module that will automatically adjust the VDD_CPU voltage by
communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
Currently only the I2C mode is supported by these bindings.
Required properties:
- compatible : should be "nvidia,tegra124-dfll"
@ -45,10 +44,31 @@ Required properties for the control loop parameters:
Optional properties for the control loop parameters:
- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
Optional properties for mode selection:
- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
Required properties for I2C mode:
- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
Example:
Required properties for PWM mode:
- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM
control is disabled and the PWM output is tristated. Note that this voltage is
configured in hardware, typically via a resistor divider.
- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control
is enabled and PWM output is low. Hence, this is the minimum output voltage
that the regulator supports when PWM control is enabled.
- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts
corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th
duty cycle would be: nvidia,pwm-min-microvolts +
nvidia,pwm-voltage-step-microvolts * 2.
- pinctrl-0: I/O pad configuration when PWM control is enabled.
- pinctrl-1: I/O pad configuration when PWM control is disabled.
- pinctrl-names: must include the following entries:
- dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
- dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.
Example for I2C:
clock@70110000 {
compatible = "nvidia,tegra124-dfll";
@ -76,3 +96,58 @@ clock@70110000 {
nvidia,i2c-fs-rate = <400000>;
};
Example for PWM:
clock@70110000 {
compatible = "nvidia,tegra124-dfll";
reg = <0 0x70110000 0 0x100>, /* DFLL control */
<0 0x70110000 0 0x100>, /* I2C output control */
<0 0x70110100 0 0x100>, /* Integrated I2C controller */
<0 0x70110200 0 0x100>; /* Look-up table RAM */
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
<&tegra_car TEGRA210_CLK_DFLL_REF>,
<&tegra_car TEGRA124_CLK_I2C5>;;
clock-names = "soc", "ref", "i2c";
resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
reset-names = "dvco";
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
nvidia,sample-rate = <25000>;
nvidia,droop-ctrl = <0x00000f00>;
nvidia,force-mode = <1>;
nvidia,cf = <6>;
nvidia,ci = <0>;
nvidia,cg = <2>;
nvidia,pwm-min-microvolts = <708000>; /* 708mV */
nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
nvidia,pwm-to-pmic;
nvidia,pwm-tristate-microvolts = <1000000>;
nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
pinctrl-0 = <&dvfs_pwm_active_state>;
pinctrl-1 = <&dvfs_pwm_inactive_state>;
};
/* pinmux nodes added for completeness. Binding doc can be found in:
* Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
*/
pinmux: pinmux@700008d4 {
dvfs_pwm_active_state: dvfs_pwm_active {
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
};
dvfs_pwm_inactive_state: dvfs_pwm_inactive {
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
};
};