mirror of https://gitee.com/openkylin/linux.git
powerpc/perf: Cleanup of PM_BR_CMPL vs. PM_BRU_CMPL in Power9 event list
Fixes: 34922527a2
("powerpc/perf: Add power9 event list macros for generic and cache events")
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
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91e0bd1e62
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@ -16,7 +16,7 @@ EVENT(PM_CYC, 0x0001e)
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EVENT(PM_ICT_NOSLOT_CYC, 0x100f8)
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EVENT(PM_CMPLU_STALL, 0x1e054)
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EVENT(PM_INST_CMPL, 0x00002)
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EVENT(PM_BRU_CMPL, 0x4d05e)
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EVENT(PM_BR_CMPL, 0x4d05e)
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EVENT(PM_BR_MPRED_CMPL, 0x400f6)
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/* All L1 D cache load references counted at finish, gated by reject */
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@ -128,7 +128,7 @@ GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
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GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_ICT_NOSLOT_CYC);
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GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
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GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
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GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_CMPL);
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GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL);
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GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
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GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
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GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN);
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@ -146,7 +146,7 @@ CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);
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CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);
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CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);
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CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
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CACHE_EVENT_ATTR(branch-loads, PM_BRU_CMPL);
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CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL);
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CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
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CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
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@ -155,7 +155,7 @@ static struct attribute *power9_events_attr[] = {
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GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC),
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GENERIC_EVENT_PTR(PM_CMPLU_STALL),
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GENERIC_EVENT_PTR(PM_INST_CMPL),
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GENERIC_EVENT_PTR(PM_BRU_CMPL),
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GENERIC_EVENT_PTR(PM_BR_CMPL),
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GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
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GENERIC_EVENT_PTR(PM_LD_REF_L1),
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GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
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@ -172,7 +172,7 @@ static struct attribute *power9_events_attr[] = {
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CACHE_EVENT_PTR(PM_L2_ST_MISS),
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CACHE_EVENT_PTR(PM_L2_ST),
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CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
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CACHE_EVENT_PTR(PM_BRU_CMPL),
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CACHE_EVENT_PTR(PM_BR_CMPL),
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CACHE_EVENT_PTR(PM_DTLB_MISS),
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CACHE_EVENT_PTR(PM_ITLB_MISS),
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NULL
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@ -247,7 +247,7 @@ static int power9_generic_events[] = {
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
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[PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_CMPL,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL,
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[PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
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[PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
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[PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN,
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@ -373,7 +373,7 @@ static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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},
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[ C(BPU) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = PM_BRU_CMPL,
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[ C(RESULT_ACCESS) ] = PM_BR_CMPL,
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[ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
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},
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[ C(OP_WRITE) ] = {
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@ -462,8 +462,8 @@ static int __init init_power9_pmu(void)
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* Power9 DD1 should use PM_BR_CMPL_ALT event code for
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* "branches" to provide correct counter value.
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*/
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EVENT_VAR(PM_BRU_CMPL, _g).id = PM_BR_CMPL_ALT;
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EVENT_VAR(PM_BRU_CMPL, _c).id = PM_BR_CMPL_ALT;
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EVENT_VAR(PM_BR_CMPL, _g).id = PM_BR_CMPL_ALT;
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EVENT_VAR(PM_BR_CMPL, _c).id = PM_BR_CMPL_ALT;
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rc = register_power_pmu(&power9_isa207_pmu);
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} else {
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rc = register_power_pmu(&power9_pmu);
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