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media: ccs-pll: Use correct VT divisor for calculating VT SYS divisor 

Use the correct video timing divisor to calculate the SYS divisor. Instead
of the current value, the minimum was used. This could have resulted in a
too low SYS divisor.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Sakari Ailus 2020-09-01 13:08:26 +02:00 committed by Mauro Carvalho Chehab
parent 415ddd9939
commit 9454432af0
1 changed files with 2 additions and 2 deletions
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4
drivers/media/i2c/ccs-pll.c
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@ -365,14 +365,14 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
/* Check if this one is better. */
if (pix_div * sys_div
<= roundup(min_vt_div, best_pix_div))
<= roundup(vt_div, best_pix_div))
best_pix_div = pix_div;
}
if (best_pix_div < INT_MAX >> 1)
break;
}
pll->vt_bk.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div);
pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
pll->vt_bk.pix_clk_div = best_pix_div;
pll->vt_bk.sys_clk_freq_hz =