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x86/platform/atom/punit: Enable support for Merrifield 

Intel Merrifield platform has Punit generation that somehow compatible to what
is already supported by punit_atom_debug driver.

Add necessary bits to enable that support.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1465842481-136852-2-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Andy Shevchenko 2016-06-13 21:28:01 +03:00 committed by Ingo Molnar
parent bb27570525
commit 9485f8b6a7
1 changed files with 13 additions and 2 deletions
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15
arch/x86/platform/atom/punit_atom_debug.c
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@ -26,8 +26,6 @@
#include <asm/intel-family.h> #include <asm/intel-family.h>
#include <asm/iosf_mbi.h> #include <asm/iosf_mbi.h>
/* Power gate status reg */
#define PWRGT_STATUS 0x61
/* Subsystem config/status Video processor */ /* Subsystem config/status Video processor */
#define VED_SS_PM0 0x32 #define VED_SS_PM0 0x32
/* Subsystem config/status ISP (Image Signal Processor) */ /* Subsystem config/status ISP (Image Signal Processor) */
@ -36,12 +34,16 @@
#define MIO_SS_PM 0x3B #define MIO_SS_PM 0x3B
/* Shift bits for getting status for video, isp and i/o */ /* Shift bits for getting status for video, isp and i/o */
#define SSS_SHIFT 24 #define SSS_SHIFT 24
/* Power gate status reg */
#define PWRGT_STATUS 0x61
/* Shift bits for getting status for graphics rendering */ /* Shift bits for getting status for graphics rendering */
#define RENDER_POS 0 #define RENDER_POS 0
/* Shift bits for getting status for media control */ /* Shift bits for getting status for media control */
#define MEDIA_POS 2 #define MEDIA_POS 2
/* Shift bits for getting status for Valley View/Baytrail display */ /* Shift bits for getting status for Valley View/Baytrail display */
#define VLV_DISPLAY_POS 6 #define VLV_DISPLAY_POS 6
/* Subsystem config/status display for Cherry Trail SOC */ /* Subsystem config/status display for Cherry Trail SOC */
#define CHT_DSP_SSS 0x36 #define CHT_DSP_SSS 0x36
/* Shift bits for getting status for display */ /* Shift bits for getting status for display */
@ -53,6 +55,14 @@ struct punit_device {
int sss_pos; int sss_pos;
}; };
static const struct punit_device punit_device_tng[] = {
{ "DISPLAY", CHT_DSP_SSS, SSS_SHIFT },
{ "VED", VED_SS_PM0, SSS_SHIFT },
{ "ISP", ISP_SS_PM0, SSS_SHIFT },
{ "MIO", MIO_SS_PM, SSS_SHIFT },
{ NULL }
};
static const struct punit_device punit_device_byt[] = { static const struct punit_device punit_device_byt[] = {
{ "GFX RENDER", PWRGT_STATUS, RENDER_POS }, { "GFX RENDER", PWRGT_STATUS, RENDER_POS },
{ "GFX MEDIA", PWRGT_STATUS, MEDIA_POS }, { "GFX MEDIA", PWRGT_STATUS, MEDIA_POS },
@ -145,6 +155,7 @@ static void punit_dbgfs_unregister(void)
static const struct x86_cpu_id intel_punit_cpu_ids[] = { static const struct x86_cpu_id intel_punit_cpu_ids[] = {
ICPU(INTEL_FAM6_ATOM_SILVERMONT1, punit_device_byt), ICPU(INTEL_FAM6_ATOM_SILVERMONT1, punit_device_byt),
ICPU(INTEL_FAM6_ATOM_MERRIFIELD1, punit_device_tng),
ICPU(INTEL_FAM6_ATOM_AIRMONT, punit_device_cht), ICPU(INTEL_FAM6_ATOM_AIRMONT, punit_device_cht),
{} {}
}; };