mirror of https://gitee.com/openkylin/linux.git
i2c: tegra: Clean up and improve comments
Make all comments to be consistent in regards to capitalization and punctuation, correct spelling and grammar errors, improve wording. Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
Dmitry Osipenko
Wolfram Sang
parent
76d06443cc
commit
94a5573f07
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@ -136,7 +136,7 @@
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/* configuration load timeout in microseconds */
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#define I2C_CONFIG_LOAD_TIMEOUT 1000000
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/* Packet header size in bytes */
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/* packet header size in bytes */
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#define I2C_PACKET_HEADER_SIZE 12
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/*
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@ -148,11 +148,10 @@
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#define I2C_PIO_MODE_PREFERRED_LEN 32
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/*
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* msg_end_type: The bus control which need to be send at end of transfer.
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* @MSG_END_STOP: Send stop pulse at end of transfer.
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* @MSG_END_REPEAT_START: Send repeat start at end of transfer.
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* @MSG_END_CONTINUE: The following on message is coming and so do not send
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* stop or repeat start.
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* msg_end_type: The bus control which needs to be sent at end of transfer.
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* @MSG_END_STOP: Send stop pulse.
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* @MSG_END_REPEAT_START: Send repeat-start.
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* @MSG_END_CONTINUE: Don't send stop or repeat-start.
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*/
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enum msg_end_type {
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MSG_END_STOP,
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@ -161,10 +160,10 @@ enum msg_end_type {
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};
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/**
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* struct tegra_i2c_hw_feature : Different HW support on Tegra
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* @has_continue_xfer_support: Continue transfer supports.
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* struct tegra_i2c_hw_feature : per hardware generation features
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* @has_continue_xfer_support: continue-transfer supported
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* @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
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* complete interrupt per packet basis.
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* completion interrupt on per packet basis.
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* @has_config_load_reg: Has the config load register to load the new
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* configuration.
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* @clk_divisor_hs_mode: Clock divisor in HS mode.
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@ -184,7 +183,7 @@ enum msg_end_type {
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* @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
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* provides additional features and allows for longer messages to
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* be transferred in one go.
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* @quirks: i2c adapter quirks for limiting write/read transfer size and not
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* @quirks: I2C adapter quirks for limiting write/read transfer size and not
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* allowing 0 length transfers.
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* @supports_bus_clear: Bus Clear support to recover from bus hang during
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* SDA stuck low from device for some unknown reasons.
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@ -245,7 +244,7 @@ struct tegra_i2c_hw_feature {
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* @msg_err: error code for completed message
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* @msg_buf: pointer to current message data
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* @msg_buf_remaining: size of unsent data in the message buffer
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* @msg_read: identifies read transfers
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* @msg_read: indicates that the transfer is a read access
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* @bus_clk_rate: current I2C bus clock rate
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* @multimaster_mode: indicates that I2C controller is in multi-master mode
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* @tx_dma_chan: DMA transmit channel
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@ -307,8 +306,8 @@ static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
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}
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/*
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* i2c_writel and i2c_readl will offset the register if necessary to talk
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* to the I2C block inside the DVC block
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* If necessary, i2c_writel() and i2c_readl() will offset the register
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* in order to talk to the I2C block inside the DVC block.
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*/
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static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
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{
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@ -323,7 +322,7 @@ static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg)
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{
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writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
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/* Read back register to make sure that register writes completed */
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/* read back register to make sure that register writes completed */
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if (reg != I2C_TX_FIFO)
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readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
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}
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@ -475,7 +474,7 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
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* block. This block is identical to the rest of the I2C blocks, except that
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* it only supports master mode, it has registers moved around, and it needs
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* some extra init to get it into I2C mode. The register moves are handled
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* by i2c_readl and i2c_writel
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* by i2c_readl() and i2c_writel().
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*/
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static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
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{
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@ -633,7 +632,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
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break;
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}
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/* Make sure clock divisor programmed correctly */
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/* make sure clock divisor programmed correctly */
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clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
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i2c_dev->hw->clk_divisor_hs_mode) |
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FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
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@ -646,8 +645,8 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
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}
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/*
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* configure setup and hold times only when tsu_thd is non-zero.
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* otherwise, preserve the chip default values
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* Configure setup and hold times only when tsu_thd is non-zero.
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* Otherwise, preserve the chip default values.
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*/
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if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
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i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
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@ -691,7 +690,7 @@ static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
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/*
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* NACK interrupt is generated before the I2C controller generates
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* the STOP condition on the bus. So wait for 2 clock periods
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* the STOP condition on the bus. So, wait for 2 clock periods
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* before disabling the controller so that the STOP condition has
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* been delivered properly.
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*/
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@ -712,8 +711,8 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
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u32 val;
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/*
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* Catch overflow due to message fully sent
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* before the check for RX FIFO availability.
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* Catch overflow due to message fully sent before the check for
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* RX FIFO availability.
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*/
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if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
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return -EINVAL;
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@ -726,7 +725,7 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
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rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val);
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}
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/* Rounds down to not include partial word at the end of buf */
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/* round down to exclude partial word at the end of buffer */
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words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
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if (words_to_transfer > rx_fifo_avail)
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words_to_transfer = rx_fifo_avail;
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@ -738,8 +737,8 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
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rx_fifo_avail -= words_to_transfer;
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/*
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* If there is a partial word at the end of buf, handle it manually to
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* prevent overwriting past the end of buf
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* If there is a partial word at the end of buffer, handle it
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* manually to prevent overwriting past the end of buffer.
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*/
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if (rx_fifo_avail > 0 && buf_remaining > 0) {
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/*
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@ -779,10 +778,15 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
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tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val);
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}
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/* Rounds down to not include partial word at the end of buf */
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/* round down to exclude partial word at the end of buffer */
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words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
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/* It's very common to have < 4 bytes, so optimize that case. */
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/*
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* This hunk pushes 4 bytes at a time into the TX FIFO.
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*
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* It's very common to have < 4 bytes, hence there is no word
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* to push if we have less than 4 bytes to transfer.
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*/
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if (words_to_transfer) {
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if (words_to_transfer > tx_fifo_avail)
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words_to_transfer = tx_fifo_avail;
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@ -806,8 +810,8 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
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}
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/*
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* If there is a partial word at the end of buf, handle it manually to
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* prevent reading past the end of buf, which could cross a page
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* If there is a partial word at the end of buffer, handle it manually
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* to prevent reading past the end of buffer, which could cross a page
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* boundary and fault.
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*/
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if (tx_fifo_avail > 0 && buf_remaining > 0) {
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@ -855,7 +859,7 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
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}
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/*
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* I2C transfer is terminated during the bus clear so skip
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* I2C transfer is terminated during the bus clear, so skip
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* processing the other interrupts.
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*/
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if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
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@ -891,7 +895,8 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
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* During message read XFER_COMPLETE interrupt is triggered prior to
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* DMA completion and during message write XFER_COMPLETE interrupt is
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* triggered after DMA completion.
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* PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer.
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*
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* PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer,
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* so forcing msg_buf_remaining to 0 in DMA mode.
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*/
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if (status & I2C_INT_PACKET_XFER_COMPLETE) {
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@ -909,7 +914,7 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
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}
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goto done;
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err:
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/* An error occurred, mask all interrupts */
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/* mask all interrupts on error */
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tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
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I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
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I2C_INT_RX_FIFO_DATA_REQ);
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@ -1333,6 +1338,7 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
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enum msg_end_type end_type = MSG_END_STOP;
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if (i < (num - 1)) {
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/* check whether follow up message is coming */
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if (msgs[i + 1].flags & I2C_M_NOSTART)
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end_type = MSG_END_CONTINUE;
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else
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@ -1562,7 +1568,6 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
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.has_interface_timing_reg = true,
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};
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/* Match table for of_platform binding */
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static const struct of_device_id tegra_i2c_of_match[] = {
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{ .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
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{ .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
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@ -1586,7 +1591,7 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
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err = of_property_read_u32(np, "clock-frequency",
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&i2c_dev->bus_clk_rate);
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if (err)
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i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */
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i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
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multi_mode = of_property_read_bool(np, "multi-master");
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i2c_dev->multimaster_mode = multi_mode;
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@ -1719,11 +1724,13 @@ static int tegra_i2c_probe(struct platform_device *pdev)
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goto release_clocks;
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/*
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* VI I2C is in VE power domain which is not always on and not
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* an IRQ safe. So, IRQ safe device can't be attached to a non-IRQ
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* safe domain as it prevents powering off the PM domain.
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* Also, VI I2C device don't need to use runtime IRQ safe as it will
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* not be used for atomic transfers.
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* VI I2C is in VE power domain which is not always ON and not
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* IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a
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* non IRQ-safe domain because this prevents powering off the power
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* domain.
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*
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* VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't
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* be used for atomic transfers.
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*/
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if (!i2c_dev->is_vi)
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pm_runtime_irq_safe(i2c_dev->dev);
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@ -1794,9 +1801,8 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
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/*
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* VI I2C device is attached to VE power domain which goes through
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* power ON/OFF during PM runtime resume/suspend. So, controller
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* should go through reset and need to re-initialize after power
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* domain ON.
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* power ON/OFF during runtime PM resume/suspend, meaning that
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* controller needs to be re-initialized after power ON.
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*/
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if (i2c_dev->is_vi) {
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err = tegra_i2c_init(i2c_dev);
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