SoC related changes for omaps to support the realtime

counter on newer omaps, and to fail early for omap5 es1.0
 SoCs that don't have any support merged for them in the
 mainline tree.
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Merge tag 'omap-for-v3.13/soc-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

From Tony Lindgren:
SoC related changes for omaps to support the realtime
counter on newer omaps, and to fail early for omap5 es1.0
SoCs that don't have any support merged for them in the
mainline tree.

* tag 'omap-for-v3.13/soc-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Fix build error for realtime counter init if not enabled
  ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register
  ARM: OMAP5: id: Remove ES1.0 support
  ARM: OMAP2+: DRA7: realtime_counter: Add ratio registers for 20MHZ sys-clk frequency

Signed-off-by: Kevin Hilman <khilman@linaro.org>
This commit is contained in:
Kevin Hilman 2013-10-14 15:42:08 -07:00
commit 94f53f1f08
5 changed files with 32 additions and 6 deletions

View File

@ -576,8 +576,8 @@ void __init omap5xxx_check_revision(void)
case 0xb942:
switch (rev) {
case 0:
omap_revision = OMAP5430_REV_ES1_0;
break;
/* No support for ES1.0 Test chip */
BUG();
case 1:
default:
omap_revision = OMAP5430_REV_ES2_0;
@ -587,8 +587,8 @@ void __init omap5xxx_check_revision(void)
case 0xb998:
switch (rev) {
case 0:
omap_revision = OMAP5432_REV_ES1_0;
break;
/* No support for ES1.0 Test chip */
BUG();
case 1:
default:
omap_revision = OMAP5432_REV_ES2_0;

View File

@ -42,6 +42,8 @@
#define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109
#define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113
#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
/* Secure PPA(Primary Protected Application) APIs */
#define OMAP4_PPA_L2_POR_INDEX 0x23
#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25
@ -60,5 +62,7 @@ extern int omap_barrier_reserve_memblock(void);
static inline void omap_barrier_reserve_memblock(void)
{ }
#endif
void set_cntfreq(void);
#endif /* __ASSEMBLER__ */
#endif /* OMAP_ARCH_OMAP_SECURE_H */

View File

@ -65,6 +65,13 @@ static void omap4_secondary_init(unsigned int cpu)
omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
4, 0, 0, 0, 0, 0);
/*
* Configure the CNTFRQ register for the secondary cpu's which
* indicates the frequency of the cpu local timers.
*/
if (soc_is_omap54xx() || soc_is_dra7xx())
set_cntfreq();
/*
* Synchronise with the boot thread.
*/

View File

@ -455,9 +455,7 @@ IS_OMAP_TYPE(3430, 0x3430)
#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
#define OMAP54XX_CLASS 0x54000054
#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
void omap2xxx_check_revision(void);

View File

@ -55,6 +55,7 @@
#include "soc.h"
#include "common.h"
#include "powerdomain.h"
#include "omap-secure.h"
#define REALTIME_COUNTER_BASE 0x48243200
#define INCREMENTER_NUMERATOR_OFFSET 0x10
@ -66,6 +67,15 @@
static struct omap_dm_timer clkev;
static struct clock_event_device clockevent_gpt;
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
static unsigned long arch_timer_freq;
void set_cntfreq(void)
{
omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
}
#endif
static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &clockevent_gpt;
@ -515,6 +525,10 @@ static void __init realtime_counter_init(void)
num = 8;
den = 25;
break;
case 20000000:
num = 192;
den = 625;
break;
case 2600000:
num = 384;
den = 1625;
@ -542,6 +556,9 @@ static void __init realtime_counter_init(void)
reg |= den;
__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
arch_timer_freq = (rate / den) * num;
set_cntfreq();
iounmap(base);
}
#else