mirror of https://gitee.com/openkylin/linux.git
drm/i915: Convert i915_reset.c over to using uncore mmio
Currently i915_reset.c mixes calls to intel_uncore, pci and our old style I915_READ mmio interfaces. Cast aside the old implicit macros, and harmonise on using uncore throughout. add/remove: 1/1 grow/shrink: 0/4 up/down: 65/-207 (-142) Function old new delta rmw_register - 65 +65 gen8_reset_engines 945 942 -3 g4x_do_reset 407 376 -31 intel_gpu_reset 545 509 -36 clear_register 63 - -63 i915_clear_error_registers 461 387 -74 A little bit of pointer dancing elimination works wonders. v2: Roll up the helpers into intel_uncore for general use With the helpers gcc was a little more eager to inline: add/remove: 0/1 grow/shrink: 1/3 up/down: 99/-133 (-34) Function old new delta i915_clear_error_registers 461 560 +99 gen8_reset_engines 945 942 -3 g4x_do_reset 407 376 -31 intel_gpu_reset 545 509 -36 clear_register 63 - -63 Total: Before=1544400, After=1544366, chg -0.00% Win some, lose some, gcc is gcc. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190405202419.3093-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
fdc4e9267f
commit
95007efbe6
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@ -18,6 +18,26 @@
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/* XXX How to handle concurrent GGTT updates using tiling registers? */
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#define RESET_UNDER_STOP_MACHINE 0
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static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
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{
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intel_uncore_rmw(uncore, reg, 0, set);
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}
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static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
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{
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intel_uncore_rmw(uncore, reg, clr, 0);
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}
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static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
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{
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intel_uncore_rmw_fw(uncore, reg, 0, set);
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}
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static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
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{
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intel_uncore_rmw_fw(uncore, reg, clr, 0);
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}
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static void engine_skip_context(struct i915_request *rq)
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{
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struct intel_engine_cs *engine = rq->engine;
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@ -119,7 +139,7 @@ void i915_reset_request(struct i915_request *rq, bool guilty)
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static void gen3_stop_engine(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct intel_uncore *uncore = engine->uncore;
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const u32 base = engine->mmio_base;
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GEM_TRACE("%s\n", engine->name);
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@ -127,20 +147,23 @@ static void gen3_stop_engine(struct intel_engine_cs *engine)
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if (intel_engine_stop_cs(engine))
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GEM_TRACE("%s: timed out on STOP_RING\n", engine->name);
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I915_WRITE_FW(RING_HEAD(base), I915_READ_FW(RING_TAIL(base)));
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POSTING_READ_FW(RING_HEAD(base)); /* paranoia */
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intel_uncore_write_fw(uncore,
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RING_HEAD(base),
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intel_uncore_read_fw(uncore, RING_TAIL(base)));
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intel_uncore_posting_read_fw(uncore, RING_HEAD(base)); /* paranoia */
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I915_WRITE_FW(RING_HEAD(base), 0);
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I915_WRITE_FW(RING_TAIL(base), 0);
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POSTING_READ_FW(RING_TAIL(base));
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intel_uncore_write_fw(uncore, RING_HEAD(base), 0);
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intel_uncore_write_fw(uncore, RING_TAIL(base), 0);
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intel_uncore_posting_read_fw(uncore, RING_TAIL(base));
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/* The ring must be empty before it is disabled */
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I915_WRITE_FW(RING_CTL(base), 0);
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intel_uncore_write_fw(uncore, RING_CTL(base), 0);
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/* Check acts as a post */
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if (I915_READ_FW(RING_HEAD(base)))
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if (intel_uncore_read_fw(uncore, RING_HEAD(base)))
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GEM_TRACE("%s: ring head [%x] not parked\n",
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engine->name, I915_READ_FW(RING_HEAD(base)));
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engine->name,
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intel_uncore_read_fw(uncore, RING_HEAD(base)));
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}
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static void i915_stop_engines(struct drm_i915_private *i915,
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@ -203,17 +226,17 @@ static int g33_do_reset(struct drm_i915_private *i915,
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return wait_for_atomic(g4x_reset_complete(pdev), 50);
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}
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static int g4x_do_reset(struct drm_i915_private *dev_priv,
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static int g4x_do_reset(struct drm_i915_private *i915,
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intel_engine_mask_t engine_mask,
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unsigned int retry)
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{
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struct pci_dev *pdev = dev_priv->drm.pdev;
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struct pci_dev *pdev = i915->drm.pdev;
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struct intel_uncore *uncore = &i915->uncore;
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int ret;
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/* WaVcpClkGateDisableForMediaReset:ctg,elk */
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I915_WRITE_FW(VDECCLK_GATE_D,
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I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
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POSTING_READ_FW(VDECCLK_GATE_D);
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rmw_set_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
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intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
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pci_write_config_byte(pdev, I915_GDRST,
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GRDOM_MEDIA | GRDOM_RESET_ENABLE);
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@ -234,18 +257,17 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
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out:
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pci_write_config_byte(pdev, I915_GDRST, 0);
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I915_WRITE_FW(VDECCLK_GATE_D,
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I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
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POSTING_READ_FW(VDECCLK_GATE_D);
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rmw_clear_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
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intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
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return ret;
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}
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static int ironlake_do_reset(struct drm_i915_private *dev_priv,
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static int ironlake_do_reset(struct drm_i915_private *i915,
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intel_engine_mask_t engine_mask,
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unsigned int retry)
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{
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struct intel_uncore *uncore = &dev_priv->uncore;
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struct intel_uncore *uncore = &i915->uncore;
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int ret;
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intel_uncore_write_fw(uncore, ILK_GDSR,
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@ -277,10 +299,10 @@ static int ironlake_do_reset(struct drm_i915_private *dev_priv,
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}
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/* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
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static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
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static int gen6_hw_domain_reset(struct drm_i915_private *i915,
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u32 hw_domain_mask)
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{
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struct intel_uncore *uncore = &dev_priv->uncore;
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struct intel_uncore *uncore = &i915->uncore;
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int err;
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/*
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@ -381,7 +403,7 @@ static u32 gen11_lock_sfc(struct intel_engine_cs *engine)
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* ends up being locked to the engine we want to reset, we have to reset
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* it as well (we will unlock it once the reset sequence is completed).
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*/
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intel_uncore_rmw_or_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
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rmw_set_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
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if (__intel_wait_for_register_fw(uncore,
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sfc_forced_lock_ack,
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@ -404,7 +426,6 @@ static void gen11_unlock_sfc(struct intel_engine_cs *engine)
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u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access;
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i915_reg_t sfc_forced_lock;
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u32 sfc_forced_lock_bit;
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u32 val;
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switch (engine->class) {
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case VIDEO_DECODE_CLASS:
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@ -424,9 +445,7 @@ static void gen11_unlock_sfc(struct intel_engine_cs *engine)
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return;
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}
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val = intel_uncore_read_fw(uncore, sfc_forced_lock);
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val &= ~sfc_forced_lock_bit;
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intel_uncore_write_fw(uncore, sfc_forced_lock, val);
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rmw_clear_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
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}
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static int gen11_reset_engines(struct drm_i915_private *i915,
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@ -491,10 +510,9 @@ static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
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static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
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_MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
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intel_uncore_write_fw(engine->uncore,
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RING_RESET_CTL(engine->mmio_base),
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_MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
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}
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static int gen8_reset_engines(struct drm_i915_private *i915,
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@ -1178,49 +1196,49 @@ static void i915_reset_device(struct drm_i915_private *i915,
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kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
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}
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static void clear_register(struct drm_i915_private *dev_priv, i915_reg_t reg)
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static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
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{
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I915_WRITE(reg, I915_READ(reg));
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intel_uncore_rmw(uncore, reg, 0, 0);
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}
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void i915_clear_error_registers(struct drm_i915_private *dev_priv)
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void i915_clear_error_registers(struct drm_i915_private *i915)
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{
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struct intel_uncore *uncore = &i915->uncore;
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u32 eir;
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if (!IS_GEN(dev_priv, 2))
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clear_register(dev_priv, PGTBL_ER);
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if (!IS_GEN(i915, 2))
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clear_register(uncore, PGTBL_ER);
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if (INTEL_GEN(dev_priv) < 4)
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clear_register(dev_priv, IPEIR(RENDER_RING_BASE));
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if (INTEL_GEN(i915) < 4)
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clear_register(uncore, IPEIR(RENDER_RING_BASE));
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else
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clear_register(dev_priv, IPEIR_I965);
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clear_register(uncore, IPEIR_I965);
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clear_register(dev_priv, EIR);
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eir = I915_READ(EIR);
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clear_register(uncore, EIR);
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eir = intel_uncore_read(uncore, EIR);
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if (eir) {
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/*
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* some errors might have become stuck,
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* mask them.
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*/
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DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
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I915_WRITE(EMR, I915_READ(EMR) | eir);
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I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT);
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rmw_set(uncore, EMR, eir);
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intel_uncore_write(uncore, IIR, I915_MASTER_ERROR_INTERRUPT);
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}
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if (INTEL_GEN(dev_priv) >= 8) {
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I915_WRITE(GEN8_RING_FAULT_REG,
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I915_READ(GEN8_RING_FAULT_REG) & ~RING_FAULT_VALID);
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POSTING_READ(GEN8_RING_FAULT_REG);
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} else if (INTEL_GEN(dev_priv) >= 6) {
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if (INTEL_GEN(i915) >= 8) {
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rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
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intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
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} else if (INTEL_GEN(i915) >= 6) {
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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for_each_engine(engine, dev_priv, id) {
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I915_WRITE(RING_FAULT_REG(engine),
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I915_READ(RING_FAULT_REG(engine)) &
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~RING_FAULT_VALID);
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for_each_engine(engine, i915, id) {
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rmw_clear(uncore,
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RING_FAULT_REG(engine), RING_FAULT_VALID);
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intel_uncore_posting_read(uncore,
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RING_FAULT_REG(engine));
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}
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POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS0]));
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}
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}
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@ -369,11 +369,26 @@ intel_uncore_read64_2x32(struct intel_uncore *uncore,
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#define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__)
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#define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__))
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static inline void intel_uncore_rmw_or_fw(struct intel_uncore *uncore,
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i915_reg_t reg, u32 or_val)
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static inline void intel_uncore_rmw(struct intel_uncore *uncore,
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i915_reg_t reg, u32 clear, u32 set)
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{
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intel_uncore_write_fw(uncore, reg,
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intel_uncore_read_fw(uncore, reg) | or_val);
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u32 val;
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val = intel_uncore_read(uncore, reg);
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val &= ~clear;
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val |= set;
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intel_uncore_write(uncore, reg, val);
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}
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static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
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i915_reg_t reg, u32 clear, u32 set)
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{
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u32 val;
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val = intel_uncore_read_fw(uncore, reg);
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val &= ~clear;
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val |= set;
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intel_uncore_write_fw(uncore, reg, val);
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}
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#define raw_reg_read(base, reg) \
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