mirror of https://gitee.com/openkylin/linux.git
usb: dwc2: host: avoid usage of dma_alloc_coherent with irqs disabled
Use Streaming DMA mappings to handle cache coherency of frame list and descriptor list. Cache are always flushed before controller access it or before cpu access it. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Gregory Herrero
Felipe Balbi
parent
fbb9e22b15
commit
95105a998d
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@ -1934,6 +1934,9 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
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dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
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dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
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chan->desc_list_sz, DMA_TO_DEVICE);
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hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK;
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/* Always start from first descriptor */
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@ -685,6 +685,7 @@ struct dwc2_hregs_backup {
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* @otg_port: OTG port number
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* @frame_list: Frame list
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* @frame_list_dma: Frame list DMA address
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* @frame_list_sz: Frame list size
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*
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* These are for peripheral mode:
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*
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@ -804,6 +805,7 @@ struct dwc2_hsotg {
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u8 otg_port;
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u32 *frame_list;
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dma_addr_t frame_list_dma;
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u32 frame_list_sz;
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#ifdef DEBUG
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u32 frrem_samples;
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@ -881,8 +881,10 @@ static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
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*/
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chan->multi_count = dwc2_hb_mult(qh->maxp);
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if (hsotg->core_params->dma_desc_enable > 0)
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if (hsotg->core_params->dma_desc_enable > 0) {
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chan->desc_list_addr = qh->desc_list_dma;
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chan->desc_list_sz = qh->desc_list_sz;
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}
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dwc2_hc_init(hsotg, chan);
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chan->qh = qh;
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@ -107,6 +107,7 @@ struct dwc2_qh;
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* @qh: QH for the transfer being processed by this channel
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* @hc_list_entry: For linking to list of host channels
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* @desc_list_addr: Current QH's descriptor list DMA address
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* @desc_list_sz: Current QH's descriptor list size
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*
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* This structure represents the state of a single host channel when acting in
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* host mode. It contains the data items needed to transfer packets to an
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@ -159,6 +160,7 @@ struct dwc2_host_chan {
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struct dwc2_qh *qh;
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struct list_head hc_list_entry;
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dma_addr_t desc_list_addr;
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u32 desc_list_sz;
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};
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struct dwc2_hcd_pipe_info {
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@ -251,6 +253,7 @@ enum dwc2_transaction_type {
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* schedule
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* @desc_list: List of transfer descriptors
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* @desc_list_dma: Physical address of desc_list
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* @desc_list_sz: Size of descriptors list
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* @n_bytes: Xfer Bytes array. Each element corresponds to a transfer
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* descriptor and indicates original XferSize value for the
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* descriptor
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@ -284,6 +287,7 @@ struct dwc2_qh {
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struct list_head qh_list_entry;
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struct dwc2_hcd_dma_desc *desc_list;
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dma_addr_t desc_list_dma;
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u32 desc_list_sz;
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u32 *n_bytes;
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unsigned tt_buffer_dirty:1;
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};
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@ -87,22 +87,23 @@ static u16 dwc2_frame_incr_val(struct dwc2_qh *qh)
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static int dwc2_desc_list_alloc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
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gfp_t flags)
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{
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qh->desc_list = dma_alloc_coherent(hsotg->dev,
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sizeof(struct dwc2_hcd_dma_desc) *
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dwc2_max_desc_num(qh), &qh->desc_list_dma,
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flags);
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qh->desc_list_sz = sizeof(struct dwc2_hcd_dma_desc) *
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dwc2_max_desc_num(qh);
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qh->desc_list = kzalloc(qh->desc_list_sz, flags | GFP_DMA);
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if (!qh->desc_list)
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return -ENOMEM;
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memset(qh->desc_list, 0,
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sizeof(struct dwc2_hcd_dma_desc) * dwc2_max_desc_num(qh));
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qh->desc_list_dma = dma_map_single(hsotg->dev, qh->desc_list,
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qh->desc_list_sz,
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DMA_TO_DEVICE);
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qh->n_bytes = kzalloc(sizeof(u32) * dwc2_max_desc_num(qh), flags);
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if (!qh->n_bytes) {
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dma_free_coherent(hsotg->dev, sizeof(struct dwc2_hcd_dma_desc)
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* dwc2_max_desc_num(qh), qh->desc_list,
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qh->desc_list_dma);
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dma_unmap_single(hsotg->dev, qh->desc_list_dma,
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qh->desc_list_sz,
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DMA_FROM_DEVICE);
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kfree(qh->desc_list);
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qh->desc_list = NULL;
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return -ENOMEM;
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}
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@ -113,9 +114,9 @@ static int dwc2_desc_list_alloc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
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static void dwc2_desc_list_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
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{
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if (qh->desc_list) {
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dma_free_coherent(hsotg->dev, sizeof(struct dwc2_hcd_dma_desc)
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* dwc2_max_desc_num(qh), qh->desc_list,
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qh->desc_list_dma);
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dma_unmap_single(hsotg->dev, qh->desc_list_dma,
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qh->desc_list_sz, DMA_FROM_DEVICE);
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kfree(qh->desc_list);
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qh->desc_list = NULL;
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}
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@ -128,21 +129,20 @@ static int dwc2_frame_list_alloc(struct dwc2_hsotg *hsotg, gfp_t mem_flags)
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if (hsotg->frame_list)
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return 0;
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hsotg->frame_list = dma_alloc_coherent(hsotg->dev,
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4 * FRLISTEN_64_SIZE,
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&hsotg->frame_list_dma,
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mem_flags);
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hsotg->frame_list_sz = 4 * FRLISTEN_64_SIZE;
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hsotg->frame_list = kzalloc(hsotg->frame_list_sz, GFP_ATOMIC | GFP_DMA);
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if (!hsotg->frame_list)
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return -ENOMEM;
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memset(hsotg->frame_list, 0, 4 * FRLISTEN_64_SIZE);
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hsotg->frame_list_dma = dma_map_single(hsotg->dev, hsotg->frame_list,
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hsotg->frame_list_sz,
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DMA_TO_DEVICE);
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return 0;
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}
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static void dwc2_frame_list_free(struct dwc2_hsotg *hsotg)
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{
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u32 *frame_list;
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dma_addr_t frame_list_dma;
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unsigned long flags;
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spin_lock_irqsave(&hsotg->lock, flags);
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@ -152,14 +152,14 @@ static void dwc2_frame_list_free(struct dwc2_hsotg *hsotg)
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return;
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}
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frame_list = hsotg->frame_list;
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frame_list_dma = hsotg->frame_list_dma;
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dma_unmap_single(hsotg->dev, hsotg->frame_list_dma,
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hsotg->frame_list_sz, DMA_FROM_DEVICE);
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kfree(hsotg->frame_list);
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hsotg->frame_list = NULL;
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spin_unlock_irqrestore(&hsotg->lock, flags);
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dma_free_coherent(hsotg->dev, 4 * FRLISTEN_64_SIZE, frame_list,
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frame_list_dma);
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}
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static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en)
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@ -249,6 +249,15 @@ static void dwc2_update_frame_list(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
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j = (j + inc) & (FRLISTEN_64_SIZE - 1);
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} while (j != i);
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/*
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* Sync frame list since controller will access it if periodic
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* channel is currently enabled.
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*/
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dma_sync_single_for_device(hsotg->dev,
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hsotg->frame_list_dma,
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hsotg->frame_list_sz,
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DMA_TO_DEVICE);
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if (!enable)
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return;
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@ -541,6 +550,11 @@ static void dwc2_fill_host_isoc_dma_desc(struct dwc2_hsotg *hsotg,
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dma_desc->status |= HOST_DMA_IOC;
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#endif
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dma_sync_single_for_device(hsotg->dev,
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qh->desc_list_dma +
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(idx * sizeof(struct dwc2_hcd_dma_desc)),
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sizeof(struct dwc2_hcd_dma_desc),
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DMA_TO_DEVICE);
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}
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static void dwc2_init_isoc_dma_desc(struct dwc2_hsotg *hsotg,
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@ -610,6 +624,11 @@ static void dwc2_init_isoc_dma_desc(struct dwc2_hsotg *hsotg,
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if (qh->ntd == ntd_max) {
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idx = dwc2_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
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qh->desc_list[idx].status |= HOST_DMA_IOC;
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dma_sync_single_for_device(hsotg->dev,
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qh->desc_list_dma + (idx *
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sizeof(struct dwc2_hcd_dma_desc)),
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sizeof(struct dwc2_hcd_dma_desc),
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DMA_TO_DEVICE);
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}
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#else
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/*
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@ -639,6 +658,11 @@ static void dwc2_init_isoc_dma_desc(struct dwc2_hsotg *hsotg,
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idx = dwc2_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
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qh->desc_list[idx].status |= HOST_DMA_IOC;
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dma_sync_single_for_device(hsotg->dev,
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qh->desc_list_dma +
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(idx * sizeof(struct dwc2_hcd_dma_desc)),
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sizeof(struct dwc2_hcd_dma_desc),
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DMA_TO_DEVICE);
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#endif
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}
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@ -676,6 +700,12 @@ static void dwc2_fill_host_dma_desc(struct dwc2_hsotg *hsotg,
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dma_desc->buf = (u32)chan->xfer_dma;
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dma_sync_single_for_device(hsotg->dev,
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qh->desc_list_dma +
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(n_desc * sizeof(struct dwc2_hcd_dma_desc)),
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sizeof(struct dwc2_hcd_dma_desc),
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DMA_TO_DEVICE);
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/*
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* Last (or only) descriptor of IN transfer with actual size less
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* than MaxPacket
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@ -726,6 +756,12 @@ static void dwc2_init_non_isoc_dma_desc(struct dwc2_hsotg *hsotg,
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"set A bit in desc %d (%p)\n",
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n_desc - 1,
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&qh->desc_list[n_desc - 1]);
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dma_sync_single_for_device(hsotg->dev,
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qh->desc_list_dma +
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((n_desc - 1) *
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sizeof(struct dwc2_hcd_dma_desc)),
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sizeof(struct dwc2_hcd_dma_desc),
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DMA_TO_DEVICE);
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}
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dwc2_fill_host_dma_desc(hsotg, chan, qtd, qh, n_desc);
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dev_vdbg(hsotg->dev,
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@ -751,10 +787,19 @@ static void dwc2_init_non_isoc_dma_desc(struct dwc2_hsotg *hsotg,
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HOST_DMA_IOC | HOST_DMA_EOL | HOST_DMA_A;
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dev_vdbg(hsotg->dev, "set IOC/EOL/A bits in desc %d (%p)\n",
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n_desc - 1, &qh->desc_list[n_desc - 1]);
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dma_sync_single_for_device(hsotg->dev,
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qh->desc_list_dma + (n_desc - 1) *
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sizeof(struct dwc2_hcd_dma_desc),
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sizeof(struct dwc2_hcd_dma_desc),
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DMA_TO_DEVICE);
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if (n_desc > 1) {
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qh->desc_list[0].status |= HOST_DMA_A;
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dev_vdbg(hsotg->dev, "set A bit in desc 0 (%p)\n",
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&qh->desc_list[0]);
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dma_sync_single_for_device(hsotg->dev,
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qh->desc_list_dma,
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sizeof(struct dwc2_hcd_dma_desc),
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DMA_TO_DEVICE);
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}
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chan->ntd = n_desc;
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}
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@ -829,7 +874,7 @@ static int dwc2_cmpl_host_isoc_dma_desc(struct dwc2_hsotg *hsotg,
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struct dwc2_qtd *qtd,
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struct dwc2_qh *qh, u16 idx)
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{
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struct dwc2_hcd_dma_desc *dma_desc = &qh->desc_list[idx];
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struct dwc2_hcd_dma_desc *dma_desc;
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struct dwc2_hcd_iso_packet_desc *frame_desc;
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u16 remain = 0;
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int rc = 0;
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@ -837,6 +882,13 @@ static int dwc2_cmpl_host_isoc_dma_desc(struct dwc2_hsotg *hsotg,
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if (!qtd->urb)
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return -EINVAL;
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dma_sync_single_for_cpu(hsotg->dev, qh->desc_list_dma + (idx *
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sizeof(struct dwc2_hcd_dma_desc)),
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sizeof(struct dwc2_hcd_dma_desc),
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DMA_FROM_DEVICE);
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dma_desc = &qh->desc_list[idx];
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frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
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dma_desc->buf = (u32)(qtd->urb->dma + frame_desc->offset);
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if (chan->ep_is_in)
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@ -1092,6 +1144,12 @@ static int dwc2_process_non_isoc_desc(struct dwc2_hsotg *hsotg,
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if (!urb)
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return -EINVAL;
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dma_sync_single_for_cpu(hsotg->dev,
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qh->desc_list_dma + (desc_num *
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sizeof(struct dwc2_hcd_dma_desc)),
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sizeof(struct dwc2_hcd_dma_desc),
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DMA_FROM_DEVICE);
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dma_desc = &qh->desc_list[desc_num];
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n_bytes = qh->n_bytes[desc_num];
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dev_vdbg(hsotg->dev,
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