mirror of https://gitee.com/openkylin/linux.git
[PATCH] skge: whietspace cleanup
Cleanup whitespace around if() and switch() and end of lines Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
020f46a39e
commit
955660652a
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@ -170,7 +170,7 @@ static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
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struct skge_port *skge = netdev_priv(dev);
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struct skge_hw *hw = skge->hw;
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if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
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if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
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return -EOPNOTSUPP;
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if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
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@ -247,7 +247,7 @@ static u32 skge_modes(const struct skge_hw *hw)
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if (iscopper(hw)) {
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modes |= ADVERTISED_TP;
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switch(hw->chip_id) {
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switch (hw->chip_id) {
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case CHIP_ID_GENESIS:
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modes &= ~(ADVERTISED_100baseT_Full
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| ADVERTISED_100baseT_Half
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@ -279,7 +279,7 @@ static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
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if (ecmd->advertising & skge_modes(hw))
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return -EINVAL;
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} else {
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switch(ecmd->speed) {
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switch (ecmd->speed) {
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case SPEED_1000:
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if (hw->chip_id == CHIP_ID_YUKON_FE)
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return -EINVAL;
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@ -393,7 +393,7 @@ static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
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{
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int i;
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switch(stringset) {
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switch (stringset) {
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case ETH_SS_STATS:
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for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
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memcpy(data + i * ETH_GSTRING_LEN,
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@ -540,9 +540,9 @@ static int skge_set_pauseparam(struct net_device *dev,
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skge->autoneg = ecmd->autoneg;
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if (ecmd->rx_pause && ecmd->tx_pause)
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skge->flow_control = FLOW_MODE_SYMMETRIC;
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else if(ecmd->rx_pause && !ecmd->tx_pause)
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else if (ecmd->rx_pause && !ecmd->tx_pause)
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skge->flow_control = FLOW_MODE_REM_SEND;
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else if(!ecmd->rx_pause && ecmd->tx_pause)
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else if (!ecmd->rx_pause && ecmd->tx_pause)
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skge->flow_control = FLOW_MODE_LOC_SEND;
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else
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skge->flow_control = FLOW_MODE_NONE;
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@ -730,7 +730,7 @@ static int skge_phys_id(struct net_device *dev, u32 data)
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{
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struct skge_port *skge = netdev_priv(dev);
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if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
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if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
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data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
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/* start blinking */
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@ -1960,7 +1960,7 @@ static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
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if (hw->chip_id == CHIP_ID_YUKON_FE)
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return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
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switch(aux & PHY_M_PS_SPEED_MSK) {
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switch (aux & PHY_M_PS_SPEED_MSK) {
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case PHY_M_PS_SPEED_1000:
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return SPEED_1000;
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case PHY_M_PS_SPEED_100:
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@ -2299,10 +2299,10 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
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local_irq_save(flags);
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if (!spin_trylock(&skge->tx_lock)) {
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/* Collision - tell upper layer to requeue */
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local_irq_restore(flags);
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return NETDEV_TX_LOCKED;
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}
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/* Collision - tell upper layer to requeue */
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local_irq_restore(flags);
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return NETDEV_TX_LOCKED;
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}
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if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
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netif_stop_queue(dev);
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@ -2439,7 +2439,7 @@ static int skge_change_mtu(struct net_device *dev, int new_mtu)
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{
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int err = 0;
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if(new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
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if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
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return -EINVAL;
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dev->mtu = new_mtu;
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@ -2473,7 +2473,7 @@ static void genesis_set_multicast(struct net_device *dev)
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memset(filter, 0xff, sizeof(filter));
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else {
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memset(filter, 0, sizeof(filter));
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for(i = 0; list && i < count; i++, list = list->next) {
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for (i = 0; list && i < count; i++, list = list->next) {
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u32 crc = crc32_le(~0, list->dmi_addr, ETH_ALEN);
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u8 bit = 63 - (crc & 63);
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@ -2510,7 +2510,7 @@ static void yukon_set_multicast(struct net_device *dev)
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int i;
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reg |= GM_RXCR_MCF_ENA;
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for(i = 0; list && i < dev->mc_count; i++, list = list->next) {
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for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
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u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
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filter[bit/8] |= 1 << (bit%8);
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}
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@ -2657,7 +2657,7 @@ static inline void skge_tx_intr(struct net_device *dev)
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struct skge_element *e;
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spin_lock(&skge->tx_lock);
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for(e = ring->to_clean; e != ring->to_use; e = e->next) {
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for (e = ring->to_clean; e != ring->to_use; e = e->next) {
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struct skge_tx_desc *td = e->desc;
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u32 control;
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@ -2712,7 +2712,7 @@ static void skge_pci_clear(struct skge_hw *hw)
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static void skge_mac_intr(struct skge_hw *hw, int port)
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{
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if (hw->chip_id == CHIP_ID_GENESIS)
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if (hw->chip_id == CHIP_ID_GENESIS)
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genesis_mac_intr(hw, port);
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else
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yukon_mac_intr(hw, port);
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@ -2847,7 +2847,7 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
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if (status & IS_MAC1)
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skge_mac_intr(hw, 0);
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if (status & IS_MAC2)
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skge_mac_intr(hw, 1);
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@ -2952,7 +2952,7 @@ static int skge_reset(struct skge_hw *hw)
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hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
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hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
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switch(hw->chip_id) {
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switch (hw->chip_id) {
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case CHIP_ID_GENESIS:
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switch (hw->phy_type) {
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case SK_PHY_XMAC:
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@ -3288,7 +3288,7 @@ static void __devexit skge_remove(struct pci_dev *pdev)
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struct skge_hw *hw = pci_get_drvdata(pdev);
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struct net_device *dev0, *dev1;
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if(!hw)
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if (!hw)
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return;
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if ((dev1 = hw->dev[1]))
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@ -3316,7 +3316,7 @@ static int skge_suspend(struct pci_dev *pdev, u32 state)
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struct skge_hw *hw = pci_get_drvdata(pdev);
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int i, wol = 0;
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for(i = 0; i < 2; i++) {
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for (i = 0; i < 2; i++) {
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struct net_device *dev = hw->dev[i];
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if (dev) {
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@ -3349,11 +3349,11 @@ static int skge_resume(struct pci_dev *pdev)
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skge_reset(hw);
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for(i = 0; i < 2; i++) {
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for (i = 0; i < 2; i++) {
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struct net_device *dev = hw->dev[i];
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if (dev) {
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netif_device_attach(dev);
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if(netif_running(dev))
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if (netif_running(dev))
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skge_up(dev);
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}
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}
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@ -537,7 +537,7 @@ enum {
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/* Queue Register Offsets, use Q_ADDR() to access */
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enum {
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B8_Q_REGS = 0x0400, /* base of Queue registers */
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B8_Q_REGS = 0x0400, /* base of Queue registers */
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Q_D = 0x00, /* 8*32 bit Current Descriptor */
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Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
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Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
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@ -986,7 +986,7 @@ enum {
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LINKLED_BLINK_OFF = 0x10,
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LINKLED_BLINK_ON = 0x20,
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};
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/* GMAC and GPHY Control Registers (YUKON only) */
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enum {
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GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
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@ -1306,7 +1306,7 @@ enum {
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enum {
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PHY_ANE_PAR_DF = 1<<4, /* Bit 4: Parallel Detection Fault */
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PHY_ANE_LP_CAP = 1<<0, /* Bit 0: Link Partner Auto-Neg. Cap. */
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PHY_ANE_LP_CAP = 1<<0, /* Bit 0: Link Partner Auto-Neg. Cap. */
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};
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enum {
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@ -1718,7 +1718,7 @@ enum {
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PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
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};
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#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
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#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
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enum {
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PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
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@ -2105,7 +2105,7 @@ enum {
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GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
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GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
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};
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/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
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enum {
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GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
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@ -2127,7 +2127,7 @@ enum {
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#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
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#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
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/* GM_TX_CTRL 16 bit r/w Transmit Control Register */
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enum {
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GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
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@ -2138,7 +2138,7 @@ enum {
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#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
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#define TX_COL_DEF 0x04
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/* GM_RX_CTRL 16 bit r/w Receive Control Register */
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enum {
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GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
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@ -2146,7 +2146,7 @@ enum {
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GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
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GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
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};
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/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
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enum {
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GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
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@ -2171,7 +2171,7 @@ enum {
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GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
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GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
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};
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#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
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#define DATA_BLIND_DEF 0x04
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@ -2186,7 +2186,7 @@ enum {
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GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
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GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
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};
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#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
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#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
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@ -2195,7 +2195,7 @@ enum {
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GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
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GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
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};
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/* Receive Frame Status Encoding */
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enum {
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GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
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@ -2217,12 +2217,12 @@ enum {
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/*
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* GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
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*/
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GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
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GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
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GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
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GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
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GMR_FS_JABBER,
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/* Rx GMAC FIFO Flush Mask (default) */
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RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
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GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE |
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GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE |
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GMR_FS_JABBER,
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};
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@ -2801,7 +2801,7 @@ struct skge_hw {
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u32 ram_size;
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u32 ram_offset;
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struct tasklet_struct ext_tasklet;
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spinlock_t phy_lock;
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};
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@ -2827,7 +2827,7 @@ enum {
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FLOW_MODE_REM_SEND = 2, /* Symmetric or just remote */
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FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */
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};
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struct skge_port {
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u32 msg_enable;
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struct skge_hw *hw;
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@ -2933,24 +2933,24 @@ static inline void skge_xm_write8(const struct skge_hw *hw, int port, int r, u8
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static inline void skge_xm_outhash(const struct skge_hw *hw, int port, int reg,
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const u8 *hash)
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{
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skge_xm_write16(hw, port, reg,
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skge_xm_write16(hw, port, reg,
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(u16)hash[0] | ((u16)hash[1] << 8));
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skge_xm_write16(hw, port, reg+2,
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skge_xm_write16(hw, port, reg+2,
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(u16)hash[2] | ((u16)hash[3] << 8));
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skge_xm_write16(hw, port, reg+4,
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skge_xm_write16(hw, port, reg+4,
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(u16)hash[4] | ((u16)hash[5] << 8));
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skge_xm_write16(hw, port, reg+6,
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skge_xm_write16(hw, port, reg+6,
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(u16)hash[6] | ((u16)hash[7] << 8));
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}
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static inline void skge_xm_outaddr(const struct skge_hw *hw, int port, int reg,
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const u8 *addr)
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{
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skge_xm_write16(hw, port, reg,
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skge_xm_write16(hw, port, reg,
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(u16)addr[0] | ((u16)addr[1] << 8));
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skge_xm_write16(hw, port, reg,
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skge_xm_write16(hw, port, reg,
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(u16)addr[2] | ((u16)addr[3] << 8));
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skge_xm_write16(hw, port, reg,
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skge_xm_write16(hw, port, reg,
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(u16)addr[4] | ((u16)addr[5] << 8));
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}
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@ -3001,5 +3001,5 @@ static inline void skge_gm_set_addr(struct skge_hw *hw, int port, int reg,
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skge_gma_write16(hw, port, reg+8,
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(u16) addr[4] | ((u16) addr[5] << 8));
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}
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#endif
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