mirror of https://gitee.com/openkylin/linux.git
Merge branch 'pm-hwmod-wdog' into pm-hwmods
This commit is contained in:
commit
963bfb0939
|
@ -232,3 +232,30 @@ static int __init omap1_init_devices(void)
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}
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arch_initcall(omap1_init_devices);
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#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
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static struct resource wdt_resources[] = {
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{
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.start = 0xfffeb000,
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.end = 0xfffeb07F,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device omap_wdt_device = {
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.name = "omap_wdt",
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.id = -1,
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.num_resources = ARRAY_SIZE(wdt_resources),
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.resource = wdt_resources,
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};
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static int __init omap_init_wdt(void)
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{
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if (!cpu_is_omap16xx())
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return;
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platform_device_register(&omap_wdt_device);
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return 0;
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}
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subsys_initcall(omap_init_wdt);
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#endif
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@ -15,6 +15,7 @@
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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@ -28,6 +29,8 @@
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#include <mach/gpio.h>
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#include <plat/mmc.h>
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#include <plat/dma.h>
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#include <plat/omap_hwmod.h>
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#include <plat/omap_device.h>
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#include "mux.h"
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@ -932,3 +935,39 @@ static int __init omap2_init_devices(void)
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return 0;
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}
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arch_initcall(omap2_init_devices);
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#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
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struct omap_device_pm_latency omap_wdt_latency[] = {
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[0] = {
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.deactivate_func = omap_device_idle_hwmods,
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.activate_func = omap_device_enable_hwmods,
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.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
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},
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};
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static int __init omap_init_wdt(void)
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{
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int id = -1;
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struct omap_device *od;
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struct omap_hwmod *oh;
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char *oh_name = "wd_timer2";
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char *dev_name = "omap_wdt";
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if (!cpu_class_is_omap2())
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return 0;
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oh = omap_hwmod_lookup(oh_name);
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if (!oh) {
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pr_err("Could not look up wd_timer%d hwmod\n", id);
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return -EINVAL;
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}
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od = omap_device_build(dev_name, id, oh, NULL, 0,
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omap_wdt_latency,
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ARRAY_SIZE(omap_wdt_latency), 0);
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WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
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dev_name, oh->name);
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return 0;
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}
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subsys_initcall(omap_init_wdt);
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#endif
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@ -19,6 +19,7 @@
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#include "omap_hwmod_common_data.h"
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#include "prm-regbits-24xx.h"
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#include "cm-regbits-24xx.h"
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/*
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* OMAP2420 hardware module integration data
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@ -33,6 +34,7 @@ static struct omap_hwmod omap2420_mpu_hwmod;
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static struct omap_hwmod omap2420_iva_hwmod;
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static struct omap_hwmod omap2420_l3_main_hwmod;
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static struct omap_hwmod omap2420_l4_core_hwmod;
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static struct omap_hwmod omap2420_wd_timer2_hwmod;
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/* L3 -> L4_CORE interface */
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static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
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@ -165,12 +167,74 @@ static struct omap_hwmod omap2420_iva_hwmod = {
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
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};
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/* l4_wkup -> wd_timer2 */
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static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
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{
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.pa_start = 0x48022000,
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.pa_end = 0x4802207f,
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.flags = ADDR_TYPE_RT
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},
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};
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
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.master = &omap2420_l4_wkup_hwmod,
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.slave = &omap2420_wd_timer2_hwmod,
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.clk = "mpu_wdt_ick",
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.addr = omap2420_wd_timer2_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/*
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* 'wd_timer' class
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* 32-bit watchdog upward counter that generates a pulse on the reset pin on
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* overflow condition
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*/
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static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
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.name = "wd_timer",
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.sysc = &omap2420_wd_timer_sysc,
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};
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/* wd_timer2 */
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static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
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&omap2420_l4_wkup__wd_timer2,
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};
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static struct omap_hwmod omap2420_wd_timer2_hwmod = {
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.name = "wd_timer2",
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.class = &omap2420_wd_timer_hwmod_class,
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.main_clk = "mpu_wdt_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
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.module_offs = WKUP_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
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},
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},
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.slaves = omap2420_wd_timer2_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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static __initdata struct omap_hwmod *omap2420_hwmods[] = {
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&omap2420_l3_main_hwmod,
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&omap2420_l4_core_hwmod,
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&omap2420_l4_wkup_hwmod,
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&omap2420_mpu_hwmod,
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&omap2420_iva_hwmod,
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&omap2420_wd_timer2_hwmod,
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NULL,
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};
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@ -19,6 +19,7 @@
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#include "omap_hwmod_common_data.h"
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#include "prm-regbits-24xx.h"
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#include "cm-regbits-24xx.h"
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/*
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* OMAP2430 hardware module integration data
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@ -33,6 +34,7 @@ static struct omap_hwmod omap2430_mpu_hwmod;
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static struct omap_hwmod omap2430_iva_hwmod;
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static struct omap_hwmod omap2430_l3_main_hwmod;
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static struct omap_hwmod omap2430_l4_core_hwmod;
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static struct omap_hwmod omap2430_wd_timer2_hwmod;
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/* L3 -> L4_CORE interface */
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static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
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@ -165,12 +167,74 @@ static struct omap_hwmod omap2430_iva_hwmod = {
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
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};
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/* l4_wkup -> wd_timer2 */
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static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
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{
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.pa_start = 0x49016000,
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.pa_end = 0x4901607f,
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.flags = ADDR_TYPE_RT
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},
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};
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static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
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.master = &omap2430_l4_wkup_hwmod,
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.slave = &omap2430_wd_timer2_hwmod,
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.clk = "mpu_wdt_ick",
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.addr = omap2430_wd_timer2_addrs,
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.addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/*
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* 'wd_timer' class
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* 32-bit watchdog upward counter that generates a pulse on the reset pin on
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* overflow condition
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*/
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static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
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.name = "wd_timer",
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.sysc = &omap2430_wd_timer_sysc,
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};
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/* wd_timer2 */
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static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
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&omap2430_l4_wkup__wd_timer2,
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};
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static struct omap_hwmod omap2430_wd_timer2_hwmod = {
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.name = "wd_timer2",
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.class = &omap2430_wd_timer_hwmod_class,
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.main_clk = "mpu_wdt_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
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.module_offs = WKUP_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
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},
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},
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.slaves = omap2430_wd_timer2_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
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};
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static __initdata struct omap_hwmod *omap2430_hwmods[] = {
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&omap2430_l3_main_hwmod,
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&omap2430_l4_core_hwmod,
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&omap2430_l4_wkup_hwmod,
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&omap2430_mpu_hwmod,
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&omap2430_iva_hwmod,
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&omap2430_wd_timer2_hwmod,
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NULL,
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};
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|
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@ -21,6 +21,7 @@
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#include "omap_hwmod_common_data.h"
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#include "prm-regbits-34xx.h"
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#include "cm-regbits-34xx.h"
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/*
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* OMAP3xxx hardware module integration data
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@ -36,6 +37,7 @@ static struct omap_hwmod omap3xxx_iva_hwmod;
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static struct omap_hwmod omap3xxx_l3_main_hwmod;
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static struct omap_hwmod omap3xxx_l4_core_hwmod;
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static struct omap_hwmod omap3xxx_l4_per_hwmod;
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static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
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/* L3 -> L4_CORE interface */
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static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
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@ -197,6 +199,69 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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};
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|
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/* l4_wkup -> wd_timer2 */
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static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
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{
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.pa_start = 0x48314000,
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.pa_end = 0x4831407f,
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.flags = ADDR_TYPE_RT
|
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},
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};
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static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
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.master = &omap3xxx_l4_wkup_hwmod,
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.slave = &omap3xxx_wd_timer2_hwmod,
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.clk = "wdt2_ick",
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.addr = omap3xxx_wd_timer2_addrs,
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.addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
|
||||
|
||||
/*
|
||||
* 'wd_timer' class
|
||||
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
|
||||
* overflow condition
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
|
||||
.rev_offs = 0x0000,
|
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
|
||||
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
|
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
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.sysc_fields = &omap_hwmod_sysc_type1,
|
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};
|
||||
|
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static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
|
||||
.name = "wd_timer",
|
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.sysc = &omap3xxx_wd_timer_sysc,
|
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};
|
||||
|
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/* wd_timer2 */
|
||||
static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
|
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&omap3xxx_l4_wkup__wd_timer2,
|
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};
|
||||
|
||||
static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
|
||||
.name = "wd_timer2",
|
||||
.class = &omap3xxx_wd_timer_hwmod_class,
|
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.main_clk = "wdt2_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP3430_EN_WDT2_SHIFT,
|
||||
.module_offs = WKUP_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
|
||||
},
|
||||
},
|
||||
.slaves = omap3xxx_wd_timer2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
|
||||
&omap3xxx_l3_main_hwmod,
|
||||
&omap3xxx_l4_core_hwmod,
|
||||
|
@ -204,6 +269,7 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
|
|||
&omap3xxx_l4_wkup_hwmod,
|
||||
&omap3xxx_mpu_hwmod,
|
||||
&omap3xxx_iva_hwmod,
|
||||
&omap3xxx_wd_timer2_hwmod,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
|
@ -452,6 +452,136 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
|
|||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
* 'wd_timer' class
|
||||
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
|
||||
* overflow condition
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
|
||||
SYSC_HAS_SOFTRESET),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
|
||||
.name = "wd_timer",
|
||||
.sysc = &omap44xx_wd_timer_sysc,
|
||||
};
|
||||
|
||||
/* wd_timer2 */
|
||||
static struct omap_hwmod omap44xx_wd_timer2_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
|
||||
{ .irq = 80 + OMAP44XX_IRQ_GIC_START },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a314000,
|
||||
.pa_end = 0x4a31407f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_wkup -> wd_timer2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
|
||||
.master = &omap44xx_l4_wkup_hwmod,
|
||||
.slave = &omap44xx_wd_timer2_hwmod,
|
||||
.clk = "l4_wkup_clk_mux_ck",
|
||||
.addr = omap44xx_wd_timer2_addrs,
|
||||
.addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* wd_timer2 slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
|
||||
&omap44xx_l4_wkup__wd_timer2,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
|
||||
.name = "wd_timer2",
|
||||
.class = &omap44xx_wd_timer_hwmod_class,
|
||||
.mpu_irqs = omap44xx_wd_timer2_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
|
||||
.main_clk = "wd_timer2_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
|
||||
},
|
||||
},
|
||||
.slaves = omap44xx_wd_timer2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* wd_timer3 */
|
||||
static struct omap_hwmod omap44xx_wd_timer3_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
|
||||
{ .irq = 36 + OMAP44XX_IRQ_GIC_START },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x40130000,
|
||||
.pa_end = 0x4013007f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_abe -> wd_timer3 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
|
||||
.master = &omap44xx_l4_abe_hwmod,
|
||||
.slave = &omap44xx_wd_timer3_hwmod,
|
||||
.clk = "ocp_abe_iclk",
|
||||
.addr = omap44xx_wd_timer3_addrs,
|
||||
.addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l4_abe -> wd_timer3 (dma) */
|
||||
static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x49030000,
|
||||
.pa_end = 0x4903007f,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
|
||||
.master = &omap44xx_l4_abe_hwmod,
|
||||
.slave = &omap44xx_wd_timer3_hwmod,
|
||||
.clk = "ocp_abe_iclk",
|
||||
.addr = omap44xx_wd_timer3_dma_addrs,
|
||||
.addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
|
||||
.user = OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* wd_timer3 slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
|
||||
&omap44xx_l4_abe__wd_timer3,
|
||||
&omap44xx_l4_abe__wd_timer3_dma,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
|
||||
.name = "wd_timer3",
|
||||
.class = &omap44xx_wd_timer_hwmod_class,
|
||||
.mpu_irqs = omap44xx_wd_timer3_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
|
||||
.main_clk = "wd_timer3_fck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
|
||||
},
|
||||
},
|
||||
.slaves = omap44xx_wd_timer3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
|
||||
/* dmm class */
|
||||
&omap44xx_dmm_hwmod,
|
||||
|
@ -472,6 +602,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
|
|||
|
||||
/* mpu class */
|
||||
&omap44xx_mpu_hwmod,
|
||||
/* wd_timer class */
|
||||
&omap44xx_wd_timer2_hwmod,
|
||||
&omap44xx_wd_timer3_hwmod,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
|
@ -232,46 +232,6 @@ static void omap_init_uwire(void)
|
|||
static inline void omap_init_uwire(void) {}
|
||||
#endif
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
|
||||
|
||||
static struct resource wdt_resources[] = {
|
||||
{
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device omap_wdt_device = {
|
||||
.name = "omap_wdt",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(wdt_resources),
|
||||
.resource = wdt_resources,
|
||||
};
|
||||
|
||||
static void omap_init_wdt(void)
|
||||
{
|
||||
if (cpu_is_omap16xx())
|
||||
wdt_resources[0].start = 0xfffeb000;
|
||||
else if (cpu_is_omap2420())
|
||||
wdt_resources[0].start = 0x48022000; /* WDT2 */
|
||||
else if (cpu_is_omap2430())
|
||||
wdt_resources[0].start = 0x49016000; /* WDT2 */
|
||||
else if (cpu_is_omap343x())
|
||||
wdt_resources[0].start = 0x48314000; /* WDT2 */
|
||||
else if (cpu_is_omap44xx())
|
||||
wdt_resources[0].start = 0x4a314000;
|
||||
else
|
||||
return;
|
||||
|
||||
wdt_resources[0].end = wdt_resources[0].start + 0x4f;
|
||||
|
||||
(void) platform_device_register(&omap_wdt_device);
|
||||
}
|
||||
#else
|
||||
static inline void omap_init_wdt(void) {}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This gets called after board-specific INIT_MACHINE, and initializes most
|
||||
* on-chip peripherals accessible on this board (except for few like USB):
|
||||
|
@ -300,7 +260,6 @@ static int __init omap_init_devices(void)
|
|||
omap_init_rng();
|
||||
omap_init_mcpdm();
|
||||
omap_init_uwire();
|
||||
omap_init_wdt();
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(omap_init_devices);
|
||||
|
|
|
@ -38,11 +38,11 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <plat/prcm.h>
|
||||
|
||||
|
@ -61,8 +61,6 @@ struct omap_wdt_dev {
|
|||
void __iomem *base; /* physical */
|
||||
struct device *dev;
|
||||
int omap_wdt_users;
|
||||
struct clk *ick;
|
||||
struct clk *fck;
|
||||
struct resource *mem;
|
||||
struct miscdevice omap_wdt_miscdev;
|
||||
};
|
||||
|
@ -146,8 +144,7 @@ static int omap_wdt_open(struct inode *inode, struct file *file)
|
|||
if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
|
||||
return -EBUSY;
|
||||
|
||||
clk_enable(wdev->ick); /* Enable the interface clock */
|
||||
clk_enable(wdev->fck); /* Enable the functional clock */
|
||||
pm_runtime_get_sync(wdev->dev);
|
||||
|
||||
/* initialize prescaler */
|
||||
while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
|
||||
|
@ -177,8 +174,7 @@ static int omap_wdt_release(struct inode *inode, struct file *file)
|
|||
|
||||
omap_wdt_disable(wdev);
|
||||
|
||||
clk_disable(wdev->ick);
|
||||
clk_disable(wdev->fck);
|
||||
pm_runtime_put_sync(wdev->dev);
|
||||
#else
|
||||
printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
|
||||
#endif
|
||||
|
@ -292,19 +288,7 @@ static int __devinit omap_wdt_probe(struct platform_device *pdev)
|
|||
|
||||
wdev->omap_wdt_users = 0;
|
||||
wdev->mem = mem;
|
||||
|
||||
wdev->ick = clk_get(&pdev->dev, "ick");
|
||||
if (IS_ERR(wdev->ick)) {
|
||||
ret = PTR_ERR(wdev->ick);
|
||||
wdev->ick = NULL;
|
||||
goto err_clk;
|
||||
}
|
||||
wdev->fck = clk_get(&pdev->dev, "fck");
|
||||
if (IS_ERR(wdev->fck)) {
|
||||
ret = PTR_ERR(wdev->fck);
|
||||
wdev->fck = NULL;
|
||||
goto err_clk;
|
||||
}
|
||||
wdev->dev = &pdev->dev;
|
||||
|
||||
wdev->base = ioremap(res->start, resource_size(res));
|
||||
if (!wdev->base) {
|
||||
|
@ -314,8 +298,8 @@ static int __devinit omap_wdt_probe(struct platform_device *pdev)
|
|||
|
||||
platform_set_drvdata(pdev, wdev);
|
||||
|
||||
clk_enable(wdev->ick);
|
||||
clk_enable(wdev->fck);
|
||||
pm_runtime_enable(wdev->dev);
|
||||
pm_runtime_get_sync(wdev->dev);
|
||||
|
||||
omap_wdt_disable(wdev);
|
||||
omap_wdt_adjust_timeout(timer_margin);
|
||||
|
@ -333,11 +317,7 @@ static int __devinit omap_wdt_probe(struct platform_device *pdev)
|
|||
__raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
|
||||
timer_margin);
|
||||
|
||||
/* autogate OCP interface clock */
|
||||
__raw_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG);
|
||||
|
||||
clk_disable(wdev->ick);
|
||||
clk_disable(wdev->fck);
|
||||
pm_runtime_put_sync(wdev->dev);
|
||||
|
||||
omap_wdt_dev = pdev;
|
||||
|
||||
|
@ -349,12 +329,6 @@ static int __devinit omap_wdt_probe(struct platform_device *pdev)
|
|||
|
||||
err_ioremap:
|
||||
wdev->base = NULL;
|
||||
|
||||
err_clk:
|
||||
if (wdev->ick)
|
||||
clk_put(wdev->ick);
|
||||
if (wdev->fck)
|
||||
clk_put(wdev->fck);
|
||||
kfree(wdev);
|
||||
|
||||
err_kzalloc:
|
||||
|
@ -386,8 +360,6 @@ static int __devexit omap_wdt_remove(struct platform_device *pdev)
|
|||
release_mem_region(res->start, resource_size(res));
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
clk_put(wdev->ick);
|
||||
clk_put(wdev->fck);
|
||||
iounmap(wdev->base);
|
||||
|
||||
kfree(wdev);
|
||||
|
|
Loading…
Reference in New Issue